drivers/spi/ti_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * TI QSPI driver
   4  *
   5  * Copyright (C) 2013, Texas Instruments, Incorporated
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/omap.h>
  11 #include <malloc.h>
  12 #include <spi.h>
  13 #include <spi-mem.h>
  14 #include <dm.h>
  15 #include <asm/gpio.h>
  16 #include <asm/omap_gpio.h>
  17 #include <asm/omap_common.h>
  18 #include <asm/ti-common/ti-edma3.h>
  19 #include <linux/kernel.h>
  20 #include <regmap.h>
  21 #include <syscon.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 /* ti qpsi register bit masks */
  26 #define QSPI_TIMEOUT                    2000000
  27 #define QSPI_FCLK                       192000000
  28 #define QSPI_DRA7XX_FCLK                76800000
  29 #define QSPI_WLEN_MAX_BITS              128
  30 #define QSPI_WLEN_MAX_BYTES             (QSPI_WLEN_MAX_BITS >> 3)
  31 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  32 /* clock control */
  33 #define QSPI_CLK_EN                     BIT(31)
  34 #define QSPI_CLK_DIV_MAX                0xffff
  35 /* command */
  36 #define QSPI_EN_CS(n)                   (n << 28)
  37 #define QSPI_WLEN(n)                    ((n-1) << 19)
  38 #define QSPI_3_PIN                      BIT(18)
  39 #define QSPI_RD_SNGL                    BIT(16)
  40 #define QSPI_WR_SNGL                    (2 << 16)
  41 #define QSPI_INVAL                      (4 << 16)
  42 #define QSPI_RD_QUAD                    (7 << 16)
  43 /* device control */
  44 #define QSPI_CKPHA(n)                   (1 << (2 + n*8))
  45 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
  46 #define QSPI_CKPOL(n)                   (1 << (n*8))
  47 /* status */
  48 #define QSPI_WC                         BIT(1)
  49 #define QSPI_BUSY                       BIT(0)
  50 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
  51 #define QSPI_XFER_DONE                  QSPI_WC
  52 #define MM_SWITCH                       0x01
  53 #define MEM_CS(cs)                      ((cs + 1) << 8)
  54 #define MEM_CS_UNSELECT                 0xfffff8ff
  55
  56 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
  57 #define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
  58 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
  59 #define QSPI_SETUP0_ADDR_SHIFT          (8)
  60 #define QSPI_SETUP0_DBITS_SHIFT         (10)
  61
  62 /* ti qspi register set */
  63 struct ti_qspi_regs {
  64         u32 pid;
  65         u32 pad0[3];
  66         u32 sysconfig;
  67         u32 pad1[3];
  68         u32 int_stat_raw;
  69         u32 int_stat_en;
  70         u32 int_en_set;
  71         u32 int_en_ctlr;
  72         u32 intc_eoi;
  73         u32 pad2[3];
  74         u32 clk_ctrl;
  75         u32 dc;
  76         u32 cmd;
  77         u32 status;
  78         u32 data;
  79         u32 setup0;
  80         u32 setup1;
  81         u32 setup2;
  82         u32 setup3;
  83         u32 memswitch;
  84         u32 data1;
  85         u32 data2;
  86         u32 data3;
  87 };
  88
  89 /* ti qspi priv */
  90 struct ti_qspi_priv {
  91         void *memory_map;
  92         size_t mmap_size;
  93         uint max_hz;
  94         u32 num_cs;
  95         struct ti_qspi_regs *base;
  96         void *ctrl_mod_mmap;
  97         ulong fclk;
  98         unsigned int mode;
  99         u32 cmd;
 100         u32 dc;
 101 };
 102
 103 static int ti_qspi_set_speed(struct udevice *bus, uint hz)
 104 {
 105         struct ti_qspi_priv *priv = dev_get_priv(bus);
 106         uint clk_div;
 107
 108         if (!hz)
 109                 clk_div = 0;
 110         else
 111                 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
 112
 113         /* truncate clk_div value to QSPI_CLK_DIV_MAX */
 114         if (clk_div > QSPI_CLK_DIV_MAX)
 115                 clk_div = QSPI_CLK_DIV_MAX;
 116
 117         debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 118
 119         /* disable SCLK */
 120         writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 121                &priv->base->clk_ctrl);
 122         /* enable SCLK and program the clk divider */
 123         writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 124
 125         return 0;
 126 }
 127
 128 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
 129 {
 130         writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
 131         /* dummy readl to ensure bus sync */
 132         readl(&priv->base->cmd);
 133 }
 134
 135 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
 136 {
 137         u32 val;
 138
 139         val = readl(ctrl_mod_mmap);
 140         if (enable)
 141                 val |= MEM_CS(cs);
 142         else
 143                 val &= MEM_CS_UNSELECT;
 144         writel(val, ctrl_mod_mmap);
 145 }
 146
 147 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 148                         const void *dout, void *din, unsigned long flags)
 149 {
 150         struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
 151         struct ti_qspi_priv *priv;
 152         struct udevice *bus;
 153         uint words = bitlen >> 3; /* fixed 8-bit word length */
 154         const uchar *txp = dout;
 155         uchar *rxp = din;
 156         uint status;
 157         int timeout;
 158         unsigned int cs = slave->cs;
 159
 160         bus = dev->parent;
 161         priv = dev_get_priv(bus);
 162
 163         if (cs > priv->num_cs) {
 164                 debug("invalid qspi chip select\n");
 165                 return -EINVAL;
 166         }
 167
 168         if (bitlen == 0)
 169                 return -1;
 170
 171         if (bitlen % 8) {
 172                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 173                 return -1;
 174         }
 175
 176         /* Setup command reg */
 177         priv->cmd = 0;
 178         priv->cmd |= QSPI_WLEN(8);
 179         priv->cmd |= QSPI_EN_CS(cs);
 180         if (priv->mode & SPI_3WIRE)
 181                 priv->cmd |= QSPI_3_PIN;
 182         priv->cmd |= 0xfff;
 183
 184         while (words) {
 185                 u8 xfer_len = 0;
 186
 187                 if (txp) {
 188                         u32 cmd = priv->cmd;
 189
 190                         if (words >= QSPI_WLEN_MAX_BYTES) {
 191                                 u32 *txbuf = (u32 *)txp;
 192                                 u32 data;
 193
 194                                 data = cpu_to_be32(*txbuf++);
 195                                 writel(data, &priv->base->data3);
 196                                 data = cpu_to_be32(*txbuf++);
 197                                 writel(data, &priv->base->data2);
 198                                 data = cpu_to_be32(*txbuf++);
 199                                 writel(data, &priv->base->data1);
 200                                 data = cpu_to_be32(*txbuf++);
 201                                 writel(data, &priv->base->data);
 202                                 cmd &= ~QSPI_WLEN_MASK;
 203                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 204                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 205                         } else {
 206                                 writeb(*txp, &priv->base->data);
 207                                 xfer_len = 1;
 208                         }
 209                         debug("tx cmd %08x dc %08x\n",
 210                               cmd | QSPI_WR_SNGL, priv->dc);
 211                         writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
 212                         status = readl(&priv->base->status);
 213                         timeout = QSPI_TIMEOUT;
 214                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 215                                 if (--timeout < 0) {
 216                                         printf("spi_xfer: TX timeout!\n");
 217                                         return -1;
 218                                 }
 219                                 status = readl(&priv->base->status);
 220                         }
 221                         txp += xfer_len;
 222                         debug("tx done, status %08x\n", status);
 223                 }
 224                 if (rxp) {
 225                         debug("rx cmd %08x dc %08x\n",
 226                               ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
 227                         writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
 228                         status = readl(&priv->base->status);
 229                         timeout = QSPI_TIMEOUT;
 230                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 231                                 if (--timeout < 0) {
 232                                         printf("spi_xfer: RX timeout!\n");
 233                                         return -1;
 234                                 }
 235                                 status = readl(&priv->base->status);
 236                         }
 237                         *rxp++ = readl(&priv->base->data);
 238                         xfer_len = 1;
 239                         debug("rx done, status %08x, read %02x\n",
 240                               status, *(rxp-1));
 241                 }
 242                 words -= xfer_len;
 243         }
 244
 245         /* Terminate frame */
 246         if (flags & SPI_XFER_END)
 247                 ti_qspi_cs_deactivate(priv);
 248
 249         return 0;
 250 }
 251
 252 /* TODO: control from sf layer to here through dm-spi */
 253 static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
 254 {
 255 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
 256         unsigned int                    addr = (unsigned int) (data);
 257         unsigned int                    edma_slot_num = 1;
 258
 259         /* Invalidate the area, so no writeback into the RAM races with DMA */
 260         invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
 261
 262         /* enable edma3 clocks */
 263         enable_edma3_clocks();
 264
 265         /* Call edma3 api to do actual DMA transfer     */
 266         edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
 267
 268         /* disable edma3 clocks */
 269         disable_edma3_clocks();
 270 #else
 271         memcpy_fromio(data, offset, len);
 272 #endif
 273
 274         *((unsigned int *)offset) += len;
 275 }
 276
 277 static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, u8 opcode,
 278                                     u8 data_nbits, u8 addr_width,
 279                                     u8 dummy_bytes)
 280 {
 281         u32 memval = opcode;
 282
 283         switch (data_nbits) {
 284         case 4:
 285                 memval |= QSPI_SETUP0_READ_QUAD;
 286                 break;
 287         case 2:
 288                 memval |= QSPI_SETUP0_READ_DUAL;
 289                 break;
 290         default:
 291                 memval |= QSPI_SETUP0_READ_NORMAL;
 292                 break;
 293         }
 294
 295         memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
 296                    dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
 297
 298         writel(memval, &priv->base->setup0);
 299 }
 300
 301 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
 302 {
 303         struct ti_qspi_priv *priv = dev_get_priv(bus);
 304
 305         priv->dc = 0;
 306         if (mode & SPI_CPHA)
 307                 priv->dc |= QSPI_CKPHA(0);
 308         if (mode & SPI_CPOL)
 309                 priv->dc |= QSPI_CKPOL(0);
 310         if (mode & SPI_CS_HIGH)
 311                 priv->dc |= QSPI_CSPOL(0);
 312
 313         return 0;
 314 }
 315
 316 static int ti_qspi_exec_mem_op(struct spi_slave *slave,
 317                                const struct spi_mem_op *op)
 318 {
 319         struct ti_qspi_priv *priv;
 320         struct udevice *bus;
 321
 322         bus = slave->dev->parent;
 323         priv = dev_get_priv(bus);
 324         u32 from = 0;
 325         int ret = 0;
 326
 327         /* Only optimize read path. */
 328         if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
 329             !op->addr.nbytes || op->addr.nbytes > 4)
 330                 return -ENOTSUPP;
 331
 332         /* Address exceeds MMIO window size, fall back to regular mode. */
 333         from = op->addr.val;
 334         if (from + op->data.nbytes > priv->mmap_size)
 335                 return -ENOTSUPP;
 336
 337         ti_qspi_setup_mmap_read(priv, op->cmd.opcode, op->data.buswidth,
 338                                 op->addr.nbytes, op->dummy.nbytes);
 339
 340         ti_qspi_copy_mmap((void *)op->data.buf.in,
 341                           (void *)priv->memory_map + from, op->data.nbytes);
 342
 343         return ret;
 344 }
 345
 346 static int ti_qspi_claim_bus(struct udevice *dev)
 347 {
 348         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 349         struct ti_qspi_priv *priv;
 350         struct udevice *bus;
 351
 352         bus = dev->parent;
 353         priv = dev_get_priv(bus);
 354
 355         if (slave_plat->cs > priv->num_cs) {
 356                 debug("invalid qspi chip select\n");
 357                 return -EINVAL;
 358         }
 359
 360         writel(MM_SWITCH, &priv->base->memswitch);
 361         if (priv->ctrl_mod_mmap)
 362                 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
 363                                        slave_plat->cs, true);
 364
 365         writel(priv->dc, &priv->base->dc);
 366         writel(0, &priv->base->cmd);
 367         writel(0, &priv->base->data);
 368
 369         priv->dc <<= slave_plat->cs * 8;
 370         writel(priv->dc, &priv->base->dc);
 371
 372         return 0;
 373 }
 374
 375 static int ti_qspi_release_bus(struct udevice *dev)
 376 {
 377         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 378         struct ti_qspi_priv *priv;
 379         struct udevice *bus;
 380
 381         bus = dev->parent;
 382         priv = dev_get_priv(bus);
 383
 384         writel(~MM_SWITCH, &priv->base->memswitch);
 385         if (priv->ctrl_mod_mmap)
 386                 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
 387                                        slave_plat->cs, false);
 388
 389         writel(0, &priv->base->dc);
 390         writel(0, &priv->base->cmd);
 391         writel(0, &priv->base->data);
 392         writel(0, &priv->base->setup0);
 393
 394         return 0;
 395 }
 396
 397 static int ti_qspi_probe(struct udevice *bus)
 398 {
 399         struct ti_qspi_priv *priv = dev_get_priv(bus);
 400
 401         priv->fclk = dev_get_driver_data(bus);
 402
 403         return 0;
 404 }
 405
 406 static void *map_syscon_chipselects(struct udevice *bus)
 407 {
 408 #if CONFIG_IS_ENABLED(SYSCON)
 409         struct udevice *syscon;
 410         struct regmap *regmap;
 411         const fdt32_t *cell;
 412         int len, err;
 413
 414         err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
 415                                            "syscon-chipselects", &syscon);
 416         if (err) {
 417                 debug("%s: unable to find syscon device (%d)\n", __func__,
 418                       err);
 419                 return NULL;
 420         }
 421
 422         regmap = syscon_get_regmap(syscon);
 423         if (IS_ERR(regmap)) {
 424                 debug("%s: unable to find regmap (%ld)\n", __func__,
 425                       PTR_ERR(regmap));
 426                 return NULL;
 427         }
 428
 429         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
 430                            "syscon-chipselects", &len);
 431         if (len < 2*sizeof(fdt32_t)) {
 432                 debug("%s: offset not available\n", __func__);
 433                 return NULL;
 434         }
 435
 436         return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
 437 #else
 438         fdt_addr_t addr;
 439         addr = devfdt_get_addr_index(bus, 2);
 440         return (addr == FDT_ADDR_T_NONE) ? NULL :
 441                 map_physmem(addr, 0, MAP_NOCACHE);
 442 #endif
 443 }
 444
 445 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
 446 {
 447         struct ti_qspi_priv *priv = dev_get_priv(bus);
 448         const void *blob = gd->fdt_blob;
 449         int node = dev_of_offset(bus);
 450         fdt_addr_t mmap_addr;
 451         fdt_addr_t mmap_size;
 452
 453         priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
 454         priv->base = map_physmem(devfdt_get_addr(bus),
 455                                  sizeof(struct ti_qspi_regs), MAP_NOCACHE);
 456         mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
 457         priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
 458         priv->mmap_size = mmap_size;
 459
 460         priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
 461         if (priv->max_hz < 0) {
 462                 debug("Error: Max frequency missing\n");
 463                 return -ENODEV;
 464         }
 465         priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
 466
 467         debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
 468               (int)priv->base, priv->max_hz);
 469
 470         return 0;
 471 }
 472
 473 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
 474         .exec_op = ti_qspi_exec_mem_op,
 475 };
 476
 477 static const struct dm_spi_ops ti_qspi_ops = {
 478         .claim_bus      = ti_qspi_claim_bus,
 479         .release_bus    = ti_qspi_release_bus,
 480         .xfer           = ti_qspi_xfer,
 481         .set_speed      = ti_qspi_set_speed,
 482         .set_mode       = ti_qspi_set_mode,
 483         .mem_ops        = &ti_qspi_mem_ops,
 484 };
 485
 486 static const struct udevice_id ti_qspi_ids[] = {
 487         { .compatible = "ti,dra7xxx-qspi",      .data = QSPI_DRA7XX_FCLK},
 488         { .compatible = "ti,am4372-qspi",       .data = QSPI_FCLK},
 489         { }
 490 };
 491
 492 U_BOOT_DRIVER(ti_qspi) = {
 493         .name   = "ti_qspi",
 494         .id     = UCLASS_SPI,
 495         .of_match = ti_qspi_ids,
 496         .ops    = &ti_qspi_ops,
 497         .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
 498         .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
 499         .probe  = ti_qspi_probe,
 500 };