drivers/spi/ti_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * TI QSPI driver
   4  *
   5  * Copyright (C) 2013, Texas Instruments, Incorporated
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/omap.h>
  11 #include <malloc.h>
  12 #include <spi.h>
  13 #include <dm.h>
  14 #include <asm/gpio.h>
  15 #include <asm/omap_gpio.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/ti-common/ti-edma3.h>
  18 #include <linux/kernel.h>
  19 #include <regmap.h>
  20 #include <syscon.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 /* ti qpsi register bit masks */
  25 #define QSPI_TIMEOUT                    2000000
  26 #define QSPI_FCLK                       192000000
  27 #define QSPI_DRA7XX_FCLK                76800000
  28 #define QSPI_WLEN_MAX_BITS              128
  29 #define QSPI_WLEN_MAX_BYTES             (QSPI_WLEN_MAX_BITS >> 3)
  30 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  31 /* clock control */
  32 #define QSPI_CLK_EN                     BIT(31)
  33 #define QSPI_CLK_DIV_MAX                0xffff
  34 /* command */
  35 #define QSPI_EN_CS(n)                   (n << 28)
  36 #define QSPI_WLEN(n)                    ((n-1) << 19)
  37 #define QSPI_3_PIN                      BIT(18)
  38 #define QSPI_RD_SNGL                    BIT(16)
  39 #define QSPI_WR_SNGL                    (2 << 16)
  40 #define QSPI_INVAL                      (4 << 16)
  41 #define QSPI_RD_QUAD                    (7 << 16)
  42 /* device control */
  43 #define QSPI_DD(m, n)                   (m << (3 + n*8))
  44 #define QSPI_CKPHA(n)                   (1 << (2 + n*8))
  45 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
  46 #define QSPI_CKPOL(n)                   (1 << (n*8))
  47 /* status */
  48 #define QSPI_WC                         BIT(1)
  49 #define QSPI_BUSY                       BIT(0)
  50 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
  51 #define QSPI_XFER_DONE                  QSPI_WC
  52 #define MM_SWITCH                       0x01
  53 #define MEM_CS(cs)                      ((cs + 1) << 8)
  54 #define MEM_CS_UNSELECT                 0xfffff8ff
  55
  56 #define QSPI_CMD_READ                   (0x3 << 0)
  57 #define QSPI_CMD_READ_DUAL              (0x6b << 0)
  58 #define QSPI_CMD_READ_QUAD              (0x6c << 0)
  59 #define QSPI_CMD_READ_FAST              (0x0b << 0)
  60 #define QSPI_SETUP0_NUM_A_BYTES         (0x3 << 8)
  61 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
  62 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS  (0x1 << 10)
  63 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
  64 #define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
  65 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
  66 #define QSPI_CMD_WRITE                  (0x12 << 16)
  67 #define QSPI_NUM_DUMMY_BITS             (0x0 << 24)
  68
  69 /* ti qspi register set */
  70 struct ti_qspi_regs {
  71         u32 pid;
  72         u32 pad0[3];
  73         u32 sysconfig;
  74         u32 pad1[3];
  75         u32 int_stat_raw;
  76         u32 int_stat_en;
  77         u32 int_en_set;
  78         u32 int_en_ctlr;
  79         u32 intc_eoi;
  80         u32 pad2[3];
  81         u32 clk_ctrl;
  82         u32 dc;
  83         u32 cmd;
  84         u32 status;
  85         u32 data;
  86         u32 setup0;
  87         u32 setup1;
  88         u32 setup2;
  89         u32 setup3;
  90         u32 memswitch;
  91         u32 data1;
  92         u32 data2;
  93         u32 data3;
  94 };
  95
  96 /* ti qspi priv */
  97 struct ti_qspi_priv {
  98         void *memory_map;
  99         uint max_hz;
 100         u32 num_cs;
 101         struct ti_qspi_regs *base;
 102         void *ctrl_mod_mmap;
 103         ulong fclk;
 104         unsigned int mode;
 105         u32 cmd;
 106         u32 dc;
 107 };
 108
 109 static int ti_qspi_set_speed(struct udevice *bus, uint hz)
 110 {
 111         struct ti_qspi_priv *priv = dev_get_priv(bus);
 112         uint clk_div;
 113
 114         if (!hz)
 115                 clk_div = 0;
 116         else
 117                 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
 118
 119         /* truncate clk_div value to QSPI_CLK_DIV_MAX */
 120         if (clk_div > QSPI_CLK_DIV_MAX)
 121                 clk_div = QSPI_CLK_DIV_MAX;
 122
 123         debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 124
 125         /* disable SCLK */
 126         writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 127                &priv->base->clk_ctrl);
 128         /* enable SCLK and program the clk divider */
 129         writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 130
 131         return 0;
 132 }
 133
 134 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
 135 {
 136         writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
 137         /* dummy readl to ensure bus sync */
 138         readl(&priv->base->cmd);
 139 }
 140
 141 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
 142 {
 143         u32 val;
 144
 145         val = readl(ctrl_mod_mmap);
 146         if (enable)
 147                 val |= MEM_CS(cs);
 148         else
 149                 val &= MEM_CS_UNSELECT;
 150         writel(val, ctrl_mod_mmap);
 151 }
 152
 153 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 154                         const void *dout, void *din, unsigned long flags)
 155 {
 156         struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
 157         struct ti_qspi_priv *priv;
 158         struct udevice *bus;
 159         uint words = bitlen >> 3; /* fixed 8-bit word length */
 160         const uchar *txp = dout;
 161         uchar *rxp = din;
 162         uint status;
 163         int timeout;
 164         unsigned int cs = slave->cs;
 165
 166         bus = dev->parent;
 167         priv = dev_get_priv(bus);
 168
 169         if (cs > priv->num_cs) {
 170                 debug("invalid qspi chip select\n");
 171                 return -EINVAL;
 172         }
 173
 174         /* Setup mmap flags */
 175         if (flags & SPI_XFER_MMAP) {
 176                 writel(MM_SWITCH, &priv->base->memswitch);
 177                 if (priv->ctrl_mod_mmap)
 178                         ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
 179                 return 0;
 180         } else if (flags & SPI_XFER_MMAP_END) {
 181                 writel(~MM_SWITCH, &priv->base->memswitch);
 182                 if (priv->ctrl_mod_mmap)
 183                         ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
 184                 return 0;
 185         }
 186
 187         if (bitlen == 0)
 188                 return -1;
 189
 190         if (bitlen % 8) {
 191                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 192                 return -1;
 193         }
 194
 195         /* Setup command reg */
 196         priv->cmd = 0;
 197         priv->cmd |= QSPI_WLEN(8);
 198         priv->cmd |= QSPI_EN_CS(cs);
 199         if (priv->mode & SPI_3WIRE)
 200                 priv->cmd |= QSPI_3_PIN;
 201         priv->cmd |= 0xfff;
 202
 203         while (words) {
 204                 u8 xfer_len = 0;
 205
 206                 if (txp) {
 207                         u32 cmd = priv->cmd;
 208
 209                         if (words >= QSPI_WLEN_MAX_BYTES) {
 210                                 u32 *txbuf = (u32 *)txp;
 211                                 u32 data;
 212
 213                                 data = cpu_to_be32(*txbuf++);
 214                                 writel(data, &priv->base->data3);
 215                                 data = cpu_to_be32(*txbuf++);
 216                                 writel(data, &priv->base->data2);
 217                                 data = cpu_to_be32(*txbuf++);
 218                                 writel(data, &priv->base->data1);
 219                                 data = cpu_to_be32(*txbuf++);
 220                                 writel(data, &priv->base->data);
 221                                 cmd &= ~QSPI_WLEN_MASK;
 222                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 223                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 224                         } else {
 225                                 writeb(*txp, &priv->base->data);
 226                                 xfer_len = 1;
 227                         }
 228                         debug("tx cmd %08x dc %08x\n",
 229                               cmd | QSPI_WR_SNGL, priv->dc);
 230                         writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
 231                         status = readl(&priv->base->status);
 232                         timeout = QSPI_TIMEOUT;
 233                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 234                                 if (--timeout < 0) {
 235                                         printf("spi_xfer: TX timeout!\n");
 236                                         return -1;
 237                                 }
 238                                 status = readl(&priv->base->status);
 239                         }
 240                         txp += xfer_len;
 241                         debug("tx done, status %08x\n", status);
 242                 }
 243                 if (rxp) {
 244                         debug("rx cmd %08x dc %08x\n",
 245                               ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
 246                         writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
 247                         status = readl(&priv->base->status);
 248                         timeout = QSPI_TIMEOUT;
 249                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 250                                 if (--timeout < 0) {
 251                                         printf("spi_xfer: RX timeout!\n");
 252                                         return -1;
 253                                 }
 254                                 status = readl(&priv->base->status);
 255                         }
 256                         *rxp++ = readl(&priv->base->data);
 257                         xfer_len = 1;
 258                         debug("rx done, status %08x, read %02x\n",
 259                               status, *(rxp-1));
 260                 }
 261                 words -= xfer_len;
 262         }
 263
 264         /* Terminate frame */
 265         if (flags & SPI_XFER_END)
 266                 ti_qspi_cs_deactivate(priv);
 267
 268         return 0;
 269 }
 270
 271 /* TODO: control from sf layer to here through dm-spi */
 272 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
 273 void spi_flash_copy_mmap(void *data, void *offset, size_t len)
 274 {
 275         unsigned int                    addr = (unsigned int) (data);
 276         unsigned int                    edma_slot_num = 1;
 277
 278         /* Invalidate the area, so no writeback into the RAM races with DMA */
 279         invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
 280
 281         /* enable edma3 clocks */
 282         enable_edma3_clocks();
 283
 284         /* Call edma3 api to do actual DMA transfer     */
 285         edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
 286
 287         /* disable edma3 clocks */
 288         disable_edma3_clocks();
 289
 290         *((unsigned int *)offset) += len;
 291 }
 292 #endif
 293
 294 static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
 295                                       struct spi_slave *slave,
 296                                       bool enable)
 297 {
 298         u32 memval;
 299         u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
 300
 301         if (!enable) {
 302                 writel(0, &priv->base->setup0);
 303                 return;
 304         }
 305
 306         memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
 307
 308         switch (mode) {
 309         case SPI_RX_QUAD:
 310                 memval |= QSPI_CMD_READ_QUAD;
 311                 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
 312                 memval |= QSPI_SETUP0_READ_QUAD;
 313                 slave->mode |= SPI_RX_QUAD;
 314                 break;
 315         case SPI_RX_DUAL:
 316                 memval |= QSPI_CMD_READ_DUAL;
 317                 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
 318                 memval |= QSPI_SETUP0_READ_DUAL;
 319                 break;
 320         default:
 321                 memval |= QSPI_CMD_READ;
 322                 memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
 323                 memval |= QSPI_SETUP0_READ_NORMAL;
 324                 break;
 325         }
 326
 327         writel(memval, &priv->base->setup0);
 328 }
 329
 330 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
 331 {
 332         struct ti_qspi_priv *priv = dev_get_priv(bus);
 333
 334         priv->dc = 0;
 335         if (mode & SPI_CPHA)
 336                 priv->dc |= QSPI_CKPHA(0);
 337         if (mode & SPI_CPOL)
 338                 priv->dc |= QSPI_CKPOL(0);
 339         if (mode & SPI_CS_HIGH)
 340                 priv->dc |= QSPI_CSPOL(0);
 341
 342         return 0;
 343 }
 344
 345 static int ti_qspi_claim_bus(struct udevice *dev)
 346 {
 347         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 348         struct spi_slave *slave = dev_get_parent_priv(dev);
 349         struct ti_qspi_priv *priv;
 350         struct udevice *bus;
 351
 352         bus = dev->parent;
 353         priv = dev_get_priv(bus);
 354
 355         if (slave_plat->cs > priv->num_cs) {
 356                 debug("invalid qspi chip select\n");
 357                 return -EINVAL;
 358         }
 359
 360         __ti_qspi_setup_memorymap(priv, slave, true);
 361
 362         writel(priv->dc, &priv->base->dc);
 363         writel(0, &priv->base->cmd);
 364         writel(0, &priv->base->data);
 365
 366         priv->dc <<= slave_plat->cs * 8;
 367         writel(priv->dc, &priv->base->dc);
 368
 369         return 0;
 370 }
 371
 372 static int ti_qspi_release_bus(struct udevice *dev)
 373 {
 374         struct spi_slave *slave = dev_get_parent_priv(dev);
 375         struct ti_qspi_priv *priv;
 376         struct udevice *bus;
 377
 378         bus = dev->parent;
 379         priv = dev_get_priv(bus);
 380
 381         __ti_qspi_setup_memorymap(priv, slave, false);
 382
 383         writel(0, &priv->base->dc);
 384         writel(0, &priv->base->cmd);
 385         writel(0, &priv->base->data);
 386
 387         return 0;
 388 }
 389
 390 static int ti_qspi_probe(struct udevice *bus)
 391 {
 392         struct ti_qspi_priv *priv = dev_get_priv(bus);
 393
 394         priv->fclk = dev_get_driver_data(bus);
 395
 396         return 0;
 397 }
 398
 399 static void *map_syscon_chipselects(struct udevice *bus)
 400 {
 401 #if CONFIG_IS_ENABLED(SYSCON)
 402         struct udevice *syscon;
 403         struct regmap *regmap;
 404         const fdt32_t *cell;
 405         int len, err;
 406
 407         err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
 408                                            "syscon-chipselects", &syscon);
 409         if (err) {
 410                 debug("%s: unable to find syscon device (%d)\n", __func__,
 411                       err);
 412                 return NULL;
 413         }
 414
 415         regmap = syscon_get_regmap(syscon);
 416         if (IS_ERR(regmap)) {
 417                 debug("%s: unable to find regmap (%ld)\n", __func__,
 418                       PTR_ERR(regmap));
 419                 return NULL;
 420         }
 421
 422         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
 423                            "syscon-chipselects", &len);
 424         if (len < 2*sizeof(fdt32_t)) {
 425                 debug("%s: offset not available\n", __func__);
 426                 return NULL;
 427         }
 428
 429         return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
 430 #else
 431         fdt_addr_t addr;
 432         addr = devfdt_get_addr_index(bus, 2);
 433         return (addr == FDT_ADDR_T_NONE) ? NULL :
 434                 map_physmem(addr, 0, MAP_NOCACHE);
 435 #endif
 436 }
 437
 438 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
 439 {
 440         struct ti_qspi_priv *priv = dev_get_priv(bus);
 441         const void *blob = gd->fdt_blob;
 442         int node = dev_of_offset(bus);
 443
 444         priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
 445         priv->base = map_physmem(devfdt_get_addr(bus),
 446                                  sizeof(struct ti_qspi_regs), MAP_NOCACHE);
 447         priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0,
 448                                        MAP_NOCACHE);
 449
 450         priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
 451         if (priv->max_hz < 0) {
 452                 debug("Error: Max frequency missing\n");
 453                 return -ENODEV;
 454         }
 455         priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
 456
 457         debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
 458               (int)priv->base, priv->max_hz);
 459
 460         return 0;
 461 }
 462
 463 static int ti_qspi_child_pre_probe(struct udevice *dev)
 464 {
 465         struct spi_slave *slave = dev_get_parent_priv(dev);
 466         struct udevice *bus = dev_get_parent(dev);
 467         struct ti_qspi_priv *priv = dev_get_priv(bus);
 468
 469         slave->memory_map = priv->memory_map;
 470         return 0;
 471 }
 472
 473 static const struct dm_spi_ops ti_qspi_ops = {
 474         .claim_bus      = ti_qspi_claim_bus,
 475         .release_bus    = ti_qspi_release_bus,
 476         .xfer           = ti_qspi_xfer,
 477         .set_speed      = ti_qspi_set_speed,
 478         .set_mode       = ti_qspi_set_mode,
 479 };
 480
 481 static const struct udevice_id ti_qspi_ids[] = {
 482         { .compatible = "ti,dra7xxx-qspi",      .data = QSPI_DRA7XX_FCLK},
 483         { .compatible = "ti,am4372-qspi",       .data = QSPI_FCLK},
 484         { }
 485 };
 486
 487 U_BOOT_DRIVER(ti_qspi) = {
 488         .name   = "ti_qspi",
 489         .id     = UCLASS_SPI,
 490         .of_match = ti_qspi_ids,
 491         .ops    = &ti_qspi_ops,
 492         .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
 493         .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
 494         .probe  = ti_qspi_probe,
 495         .child_pre_probe = ti_qspi_child_pre_probe,
 496 };