drivers/spi/ti_qspi.c

   1 /*
   2  * TI QSPI driver
   3  *
   4  * Copyright (C) 2013, Texas Instruments, Incorporated
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/omap.h>
  12 #include <malloc.h>
  13 #include <spi.h>
  14 #include <asm/gpio.h>
  15 #include <asm/omap_gpio.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/ti-common/ti-edma3.h>
  18
  19 /* ti qpsi register bit masks */
  20 #define QSPI_TIMEOUT                    2000000
  21 #define QSPI_FCLK                       192000000
  22 /* clock control */
  23 #define QSPI_CLK_EN                     BIT(31)
  24 #define QSPI_CLK_DIV_MAX                0xffff
  25 /* command */
  26 #define QSPI_EN_CS(n)                   (n << 28)
  27 #define QSPI_WLEN(n)                    ((n-1) << 19)
  28 #define QSPI_3_PIN                      BIT(18)
  29 #define QSPI_RD_SNGL                    BIT(16)
  30 #define QSPI_WR_SNGL                    (2 << 16)
  31 #define QSPI_INVAL                      (4 << 16)
  32 #define QSPI_RD_QUAD                    (7 << 16)
  33 /* device control */
  34 #define QSPI_DD(m, n)                   (m << (3 + n*8))
  35 #define QSPI_CKPHA(n)                   (1 << (2 + n*8))
  36 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
  37 #define QSPI_CKPOL(n)                   (1 << (n*8))
  38 /* status */
  39 #define QSPI_WC                         BIT(1)
  40 #define QSPI_BUSY                       BIT(0)
  41 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
  42 #define QSPI_XFER_DONE                  QSPI_WC
  43 #define MM_SWITCH                       0x01
  44 #define MEM_CS                          0x100
  45 #define MEM_CS_UNSELECT                 0xfffff0ff
  46 #define MMAP_START_ADDR_DRA             0x5c000000
  47 #define MMAP_START_ADDR_AM43x           0x30000000
  48 #define CORE_CTRL_IO                    0x4a002558
  49
  50 #define QSPI_CMD_READ                   (0x3 << 0)
  51 #define QSPI_CMD_READ_QUAD              (0x6b << 0)
  52 #define QSPI_CMD_READ_FAST              (0x0b << 0)
  53 #define QSPI_SETUP0_NUM_A_BYTES         (0x2 << 8)
  54 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
  55 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS  (0x1 << 10)
  56 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
  57 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
  58 #define QSPI_CMD_WRITE                  (0x2 << 16)
  59 #define QSPI_NUM_DUMMY_BITS             (0x0 << 24)
  60
  61 /* ti qspi register set */
  62 struct ti_qspi_regs {
  63         u32 pid;
  64         u32 pad0[3];
  65         u32 sysconfig;
  66         u32 pad1[3];
  67         u32 int_stat_raw;
  68         u32 int_stat_en;
  69         u32 int_en_set;
  70         u32 int_en_ctlr;
  71         u32 intc_eoi;
  72         u32 pad2[3];
  73         u32 clk_ctrl;
  74         u32 dc;
  75         u32 cmd;
  76         u32 status;
  77         u32 data;
  78         u32 setup0;
  79         u32 setup1;
  80         u32 setup2;
  81         u32 setup3;
  82         u32 memswitch;
  83         u32 data1;
  84         u32 data2;
  85         u32 data3;
  86 };
  87
  88 /* ti qspi slave */
  89 struct ti_qspi_slave {
  90         struct spi_slave slave;
  91         struct ti_qspi_regs *base;
  92         unsigned int mode;
  93         u32 cmd;
  94         u32 dc;
  95 };
  96
  97 static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
  98 {
  99         return container_of(slave, struct ti_qspi_slave, slave);
 100 }
 101
 102 static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
 103 {
 104         struct spi_slave *slave = &qslave->slave;
 105         u32 memval = 0;
 106
 107 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 108         slave->memory_map = (void *)MMAP_START_ADDR_DRA;
 109 #else
 110         slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
 111 #endif
 112
 113 #ifdef CONFIG_QSPI_QUAD_SUPPORT
 114         memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
 115                         QSPI_SETUP0_NUM_D_BYTES_8_BITS |
 116                         QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
 117                         QSPI_NUM_DUMMY_BITS);
 118         slave->op_mode_rx = SPI_OPM_RX_QOF;
 119 #else
 120         memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
 121                         QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
 122                         QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
 123                         QSPI_NUM_DUMMY_BITS;
 124 #endif
 125
 126         writel(memval, &qslave->base->setup0);
 127 }
 128
 129 static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
 130 {
 131         struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
 132         uint clk_div;
 133
 134         debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 135
 136         if (!hz)
 137                 clk_div = 0;
 138         else
 139                 clk_div = (QSPI_FCLK / hz) - 1;
 140
 141         /* disable SCLK */
 142         writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN,
 143                &qslave->base->clk_ctrl);
 144
 145         /* assign clk_div values */
 146         if (clk_div < 0)
 147                 clk_div = 0;
 148         else if (clk_div > QSPI_CLK_DIV_MAX)
 149                 clk_div = QSPI_CLK_DIV_MAX;
 150
 151         /* enable SCLK */
 152         writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl);
 153 }
 154
 155 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 156 {
 157         return 1;
 158 }
 159
 160 void spi_cs_activate(struct spi_slave *slave)
 161 {
 162         /* CS handled in xfer */
 163         return;
 164 }
 165
 166 void spi_cs_deactivate(struct spi_slave *slave)
 167 {
 168         struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
 169
 170         debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
 171
 172         writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
 173         /* dummy readl to ensure bus sync */
 174         readl(&qslave->base->cmd);
 175 }
 176
 177 void spi_init(void)
 178 {
 179         /* nothing to do */
 180 }
 181
 182 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 183                                   unsigned int max_hz, unsigned int mode)
 184 {
 185         struct ti_qspi_slave *qslave;
 186
 187 #ifdef CONFIG_AM43XX
 188         gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
 189         gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
 190 #endif
 191
 192         qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
 193         if (!qslave) {
 194                 printf("SPI_error: Fail to allocate ti_qspi_slave\n");
 195                 return NULL;
 196         }
 197
 198         qslave->base = (struct ti_qspi_regs *)QSPI_BASE;
 199         qslave->mode = mode;
 200
 201         ti_spi_set_speed(&qslave->slave, max_hz);
 202
 203 #ifdef CONFIG_TI_SPI_MMAP
 204         ti_spi_setup_spi_register(qslave);
 205 #endif
 206
 207         return &qslave->slave;
 208 }
 209
 210 void spi_free_slave(struct spi_slave *slave)
 211 {
 212         struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
 213         free(qslave);
 214 }
 215
 216 int spi_claim_bus(struct spi_slave *slave)
 217 {
 218         struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
 219
 220         debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
 221
 222         qslave->dc = 0;
 223         if (qslave->mode & SPI_CPHA)
 224                 qslave->dc |= QSPI_CKPHA(slave->cs);
 225         if (qslave->mode & SPI_CPOL)
 226                 qslave->dc |= QSPI_CKPOL(slave->cs);
 227         if (qslave->mode & SPI_CS_HIGH)
 228                 qslave->dc |= QSPI_CSPOL(slave->cs);
 229
 230         writel(qslave->dc, &qslave->base->dc);
 231         writel(0, &qslave->base->cmd);
 232         writel(0, &qslave->base->data);
 233
 234         return 0;
 235 }
 236
 237 void spi_release_bus(struct spi_slave *slave)
 238 {
 239         struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
 240
 241         debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
 242
 243         writel(0, &qslave->base->dc);
 244         writel(0, &qslave->base->cmd);
 245         writel(0, &qslave->base->data);
 246 }
 247
 248 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 249              void *din, unsigned long flags)
 250 {
 251         struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
 252         uint words = bitlen >> 3; /* fixed 8-bit word length */
 253         const uchar *txp = dout;
 254         uchar *rxp = din;
 255         uint status;
 256         int timeout;
 257
 258 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 259         int val;
 260 #endif
 261
 262         debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
 263               slave->bus, slave->cs, bitlen, words, flags);
 264
 265         /* Setup mmap flags */
 266         if (flags & SPI_XFER_MMAP) {
 267                 writel(MM_SWITCH, &qslave->base->memswitch);
 268 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 269                 val = readl(CORE_CTRL_IO);
 270                 val |= MEM_CS;
 271                 writel(val, CORE_CTRL_IO);
 272 #endif
 273                 return 0;
 274         } else if (flags & SPI_XFER_MMAP_END) {
 275                 writel(~MM_SWITCH, &qslave->base->memswitch);
 276 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 277                 val = readl(CORE_CTRL_IO);
 278                 val &= MEM_CS_UNSELECT;
 279                 writel(val, CORE_CTRL_IO);
 280 #endif
 281                 return 0;
 282         }
 283
 284         if (bitlen == 0)
 285                 return -1;
 286
 287         if (bitlen % 8) {
 288                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 289                 return -1;
 290         }
 291
 292         /* Setup command reg */
 293         qslave->cmd = 0;
 294         qslave->cmd |= QSPI_WLEN(8);
 295         qslave->cmd |= QSPI_EN_CS(slave->cs);
 296         if (qslave->mode & SPI_3WIRE)
 297                 qslave->cmd |= QSPI_3_PIN;
 298         qslave->cmd |= 0xfff;
 299
 300 /* FIXME: This delay is required for successfull
 301  * completion of read/write/erase. Once its root
 302  * caused, it will be remove from the driver.
 303  */
 304 #ifdef CONFIG_AM43XX
 305         udelay(100);
 306 #endif
 307         while (words--) {
 308                 if (txp) {
 309                         debug("tx cmd %08x dc %08x data %02x\n",
 310                               qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp);
 311                         writel(*txp++, &qslave->base->data);
 312                         writel(qslave->cmd | QSPI_WR_SNGL,
 313                                &qslave->base->cmd);
 314                         status = readl(&qslave->base->status);
 315                         timeout = QSPI_TIMEOUT;
 316                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 317                                 if (--timeout < 0) {
 318                                         printf("spi_xfer: TX timeout!\n");
 319                                         return -1;
 320                                 }
 321                                 status = readl(&qslave->base->status);
 322                         }
 323                         debug("tx done, status %08x\n", status);
 324                 }
 325                 if (rxp) {
 326                         qslave->cmd |= QSPI_RD_SNGL;
 327                         debug("rx cmd %08x dc %08x\n",
 328                               qslave->cmd, qslave->dc);
 329                         #ifdef CONFIG_DRA7XX
 330                                 udelay(500);
 331                         #endif
 332                         writel(qslave->cmd, &qslave->base->cmd);
 333                         status = readl(&qslave->base->status);
 334                         timeout = QSPI_TIMEOUT;
 335                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 336                                 if (--timeout < 0) {
 337                                         printf("spi_xfer: RX timeout!\n");
 338                                         return -1;
 339                                 }
 340                                 status = readl(&qslave->base->status);
 341                         }
 342                         *rxp++ = readl(&qslave->base->data);
 343                         debug("rx done, status %08x, read %02x\n",
 344                               status, *(rxp-1));
 345                 }
 346         }
 347
 348         /* Terminate frame */
 349         if (flags & SPI_XFER_END)
 350                 spi_cs_deactivate(slave);
 351
 352         return 0;
 353 }
 354
 355 /* TODO: control from sf layer to here through dm-spi */
 356 #ifdef CONFIG_TI_EDMA3
 357 void spi_flash_copy_mmap(void *data, void *offset, size_t len)
 358 {
 359         unsigned int                    addr = (unsigned int) (data);
 360         unsigned int                    edma_slot_num = 1;
 361
 362         /* Invalidate the area, so no writeback into the RAM races with DMA */
 363         invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
 364
 365         /* enable edma3 clocks */
 366         enable_edma3_clocks();
 367
 368         /* Call edma3 api to do actual DMA transfer     */
 369         edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
 370
 371         /* disable edma3 clocks */
 372         disable_edma3_clocks();
 373
 374         *((unsigned int *)offset) += len;
 375 }
 376 #endif