4 * Copyright (C) 2013, Texas Instruments, Incorporated
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/omap.h>
15 #include <asm/omap_gpio.h>
17 /* ti qpsi register bit masks */
18 #define QSPI_TIMEOUT 2000000
19 #define QSPI_FCLK 192000000
21 #define QSPI_CLK_EN (1 << 31)
22 #define QSPI_CLK_DIV_MAX 0xffff
24 #define QSPI_EN_CS(n) (n << 28)
25 #define QSPI_WLEN(n) ((n-1) << 19)
26 #define QSPI_3_PIN (1 << 18)
27 #define QSPI_RD_SNGL (1 << 16)
28 #define QSPI_WR_SNGL (2 << 16)
29 #define QSPI_INVAL (4 << 16)
30 #define QSPI_RD_QUAD (7 << 16)
32 #define QSPI_DD(m, n) (m << (3 + n*8))
33 #define QSPI_CKPHA(n) (1 << (2 + n*8))
34 #define QSPI_CSPOL(n) (1 << (1 + n*8))
35 #define QSPI_CKPOL(n) (1 << (n*8))
37 #define QSPI_WC (1 << 1)
38 #define QSPI_BUSY (1 << 0)
39 #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
40 #define QSPI_XFER_DONE QSPI_WC
41 #define MM_SWITCH 0x01
43 #define MEM_CS_UNSELECT 0xfffff0ff
44 #define MMAP_START_ADDR_DRA 0x5c000000
45 #define MMAP_START_ADDR_AM43x 0x30000000
46 #define CORE_CTRL_IO 0x4a002558
48 #define QSPI_CMD_READ (0x3 << 0)
49 #define QSPI_CMD_READ_QUAD (0x6b << 0)
50 #define QSPI_CMD_READ_FAST (0x0b << 0)
51 #define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8)
52 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
53 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
54 #define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
55 #define QSPI_SETUP0_READ_QUAD (0x3 << 12)
56 #define QSPI_CMD_WRITE (0x2 << 16)
57 #define QSPI_NUM_DUMMY_BITS (0x0 << 24)
59 /* ti qspi register set */
87 struct ti_qspi_slave {
88 struct spi_slave slave;
89 struct ti_qspi_regs *base;
95 static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
97 return container_of(slave, struct ti_qspi_slave, slave);
100 static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
102 struct spi_slave *slave = &qslave->slave;
105 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
106 slave->memory_map = (void *)MMAP_START_ADDR_DRA;
108 slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
109 slave->op_mode_rx = 8;
112 #ifdef CONFIG_QSPI_QUAD_SUPPORT
113 memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
114 QSPI_SETUP0_NUM_D_BYTES_8_BITS |
115 QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
116 QSPI_NUM_DUMMY_BITS);
118 memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
119 QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
120 QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
124 writel(memval, &qslave->base->setup0);
127 static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
129 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
132 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
137 clk_div = (QSPI_FCLK / hz) - 1;
140 writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN,
141 &qslave->base->clk_ctrl);
143 /* assign clk_div values */
146 else if (clk_div > QSPI_CLK_DIV_MAX)
147 clk_div = QSPI_CLK_DIV_MAX;
150 writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl);
153 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
158 void spi_cs_activate(struct spi_slave *slave)
160 /* CS handled in xfer */
164 void spi_cs_deactivate(struct spi_slave *slave)
166 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
168 debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
170 writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
178 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
179 unsigned int max_hz, unsigned int mode)
181 struct ti_qspi_slave *qslave;
184 gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
185 gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
188 qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
190 printf("SPI_error: Fail to allocate ti_qspi_slave\n");
194 qslave->base = (struct ti_qspi_regs *)QSPI_BASE;
197 ti_spi_set_speed(&qslave->slave, max_hz);
199 #ifdef CONFIG_TI_SPI_MMAP
200 ti_spi_setup_spi_register(qslave);
203 return &qslave->slave;
206 void spi_free_slave(struct spi_slave *slave)
208 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
212 int spi_claim_bus(struct spi_slave *slave)
214 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
216 debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
219 if (qslave->mode & SPI_CPHA)
220 qslave->dc |= QSPI_CKPHA(slave->cs);
221 if (qslave->mode & SPI_CPOL)
222 qslave->dc |= QSPI_CKPOL(slave->cs);
223 if (qslave->mode & SPI_CS_HIGH)
224 qslave->dc |= QSPI_CSPOL(slave->cs);
226 writel(qslave->dc, &qslave->base->dc);
227 writel(0, &qslave->base->cmd);
228 writel(0, &qslave->base->data);
233 void spi_release_bus(struct spi_slave *slave)
235 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
237 debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
239 writel(0, &qslave->base->dc);
240 writel(0, &qslave->base->cmd);
241 writel(0, &qslave->base->data);
244 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
245 void *din, unsigned long flags)
247 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
248 uint words = bitlen >> 3; /* fixed 8-bit word length */
249 const uchar *txp = dout;
254 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
258 debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
259 slave->bus, slave->cs, bitlen, words, flags);
261 /* Setup mmap flags */
262 if (flags & SPI_XFER_MMAP) {
263 writel(MM_SWITCH, &qslave->base->memswitch);
264 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
265 val = readl(CORE_CTRL_IO);
267 writel(val, CORE_CTRL_IO);
270 } else if (flags & SPI_XFER_MMAP_END) {
271 writel(~MM_SWITCH, &qslave->base->memswitch);
272 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
273 val = readl(CORE_CTRL_IO);
274 val &= MEM_CS_UNSELECT;
275 writel(val, CORE_CTRL_IO);
284 debug("spi_xfer: Non byte aligned SPI transfer\n");
288 /* Setup command reg */
290 qslave->cmd |= QSPI_WLEN(8);
291 qslave->cmd |= QSPI_EN_CS(slave->cs);
292 if (flags & SPI_3WIRE)
293 qslave->cmd |= QSPI_3_PIN;
294 qslave->cmd |= 0xfff;
296 /* FIXME: This delay is required for successfull
297 * completion of read/write/erase. Once its root
298 * caused, it will be remove from the driver.
305 debug("tx cmd %08x dc %08x data %02x\n",
306 qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp);
307 writel(*txp++, &qslave->base->data);
308 writel(qslave->cmd | QSPI_WR_SNGL,
310 status = readl(&qslave->base->status);
311 timeout = QSPI_TIMEOUT;
312 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
314 printf("spi_xfer: TX timeout!\n");
317 status = readl(&qslave->base->status);
319 debug("tx done, status %08x\n", status);
322 qslave->cmd |= QSPI_RD_SNGL;
323 debug("rx cmd %08x dc %08x\n",
324 qslave->cmd, qslave->dc);
328 writel(qslave->cmd, &qslave->base->cmd);
329 status = readl(&qslave->base->status);
330 timeout = QSPI_TIMEOUT;
331 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
333 printf("spi_xfer: RX timeout!\n");
336 status = readl(&qslave->base->status);
338 *rxp++ = readl(&qslave->base->data);
339 debug("rx done, status %08x, read %02x\n",
344 /* Terminate frame */
345 if (flags & SPI_XFER_END)
346 spi_cs_deactivate(slave);