1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
5 * Driver for STMicroelectronics Serial peripheral interface (SPI)
14 #include <dm/device_compat.h>
18 #include <linux/bitfield.h>
19 #include <linux/iopoll.h>
21 /* STM32 SPI registers */
22 #define STM32_SPI_CR1 0x00
23 #define STM32_SPI_CR2 0x04
24 #define STM32_SPI_CFG1 0x08
25 #define STM32_SPI_CFG2 0x0C
26 #define STM32_SPI_SR 0x14
27 #define STM32_SPI_IFCR 0x18
28 #define STM32_SPI_TXDR 0x20
29 #define STM32_SPI_RXDR 0x30
30 #define STM32_SPI_I2SCFGR 0x50
32 /* STM32_SPI_CR1 bit fields */
33 #define SPI_CR1_SPE BIT(0)
34 #define SPI_CR1_MASRX BIT(8)
35 #define SPI_CR1_CSTART BIT(9)
36 #define SPI_CR1_CSUSP BIT(10)
37 #define SPI_CR1_HDDIR BIT(11)
38 #define SPI_CR1_SSI BIT(12)
40 /* STM32_SPI_CR2 bit fields */
41 #define SPI_CR2_TSIZE GENMASK(15, 0)
43 /* STM32_SPI_CFG1 bit fields */
44 #define SPI_CFG1_DSIZE GENMASK(4, 0)
45 #define SPI_CFG1_DSIZE_MIN 3
46 #define SPI_CFG1_FTHLV_SHIFT 5
47 #define SPI_CFG1_FTHLV GENMASK(8, 5)
48 #define SPI_CFG1_MBR_SHIFT 28
49 #define SPI_CFG1_MBR GENMASK(30, 28)
50 #define SPI_CFG1_MBR_MIN 0
51 #define SPI_CFG1_MBR_MAX FIELD_GET(SPI_CFG1_MBR, SPI_CFG1_MBR)
53 /* STM32_SPI_CFG2 bit fields */
54 #define SPI_CFG2_COMM_SHIFT 17
55 #define SPI_CFG2_COMM GENMASK(18, 17)
56 #define SPI_CFG2_MASTER BIT(22)
57 #define SPI_CFG2_LSBFRST BIT(23)
58 #define SPI_CFG2_CPHA BIT(24)
59 #define SPI_CFG2_CPOL BIT(25)
60 #define SPI_CFG2_SSM BIT(26)
61 #define SPI_CFG2_AFCNTR BIT(31)
63 /* STM32_SPI_SR bit fields */
64 #define SPI_SR_RXP BIT(0)
65 #define SPI_SR_TXP BIT(1)
66 #define SPI_SR_EOT BIT(3)
67 #define SPI_SR_TXTF BIT(4)
68 #define SPI_SR_OVR BIT(6)
69 #define SPI_SR_SUSP BIT(11)
70 #define SPI_SR_RXPLVL_SHIFT 13
71 #define SPI_SR_RXPLVL GENMASK(14, 13)
72 #define SPI_SR_RXWNE BIT(15)
74 /* STM32_SPI_IFCR bit fields */
75 #define SPI_IFCR_ALL GENMASK(11, 3)
77 /* STM32_SPI_I2SCFGR bit fields */
78 #define SPI_I2SCFGR_I2SMOD BIT(0)
80 #define MAX_CS_COUNT 4
82 /* SPI Master Baud Rate min/max divisor */
83 #define STM32_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
84 #define STM32_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
86 #define STM32_SPI_TIMEOUT_US 100000
88 /* SPI Communication mode */
89 #define SPI_FULL_DUPLEX 0
90 #define SPI_SIMPLEX_TX 1
91 #define SPI_SIMPLEX_RX 2
92 #define SPI_HALF_DUPLEX 3
94 struct stm32_spi_priv {
97 struct reset_ctl rst_ctl;
98 struct gpio_desc cs_gpios[MAX_CS_COUNT];
100 unsigned int fifo_size;
101 unsigned int cur_bpw;
103 unsigned int cur_xferlen; /* current transfer length in bytes */
104 unsigned int tx_len; /* number of data to be written in bytes */
105 unsigned int rx_len; /* number of data to be read in bytes */
106 const void *tx_buf; /* data to be written, or NULL */
107 void *rx_buf; /* data to be read, or NULL */
112 static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
114 while ((priv->tx_len > 0) &&
115 (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) {
116 u32 offs = priv->cur_xferlen - priv->tx_len;
118 if (priv->tx_len >= sizeof(u32) &&
119 IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
120 const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs);
122 writel(*tx_buf32, priv->base + STM32_SPI_TXDR);
123 priv->tx_len -= sizeof(u32);
124 } else if (priv->tx_len >= sizeof(u16) &&
125 IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
126 const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs);
128 writew(*tx_buf16, priv->base + STM32_SPI_TXDR);
129 priv->tx_len -= sizeof(u16);
131 const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs);
133 writeb(*tx_buf8, priv->base + STM32_SPI_TXDR);
134 priv->tx_len -= sizeof(u8);
138 debug("%s: %d bytes left\n", __func__, priv->tx_len);
141 static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
143 u32 sr = readl(priv->base + STM32_SPI_SR);
144 u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
146 while ((priv->rx_len > 0) &&
147 ((sr & SPI_SR_RXP) ||
148 ((sr & SPI_SR_EOT) && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
149 u32 offs = priv->cur_xferlen - priv->rx_len;
151 if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u32)) &&
152 (priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) {
153 u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs);
155 *rx_buf32 = readl(priv->base + STM32_SPI_RXDR);
156 priv->rx_len -= sizeof(u32);
157 } else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
158 (priv->rx_len >= sizeof(u16) ||
159 (!(sr & SPI_SR_RXWNE) &&
160 (rxplvl >= 2 || priv->cur_bpw > 8)))) {
161 u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs);
163 *rx_buf16 = readw(priv->base + STM32_SPI_RXDR);
164 priv->rx_len -= sizeof(u16);
166 u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs);
168 *rx_buf8 = readb(priv->base + STM32_SPI_RXDR);
169 priv->rx_len -= sizeof(u8);
172 sr = readl(priv->base + STM32_SPI_SR);
173 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
176 debug("%s: %d bytes left\n", __func__, priv->rx_len);
179 static int stm32_spi_enable(struct stm32_spi_priv *priv)
181 debug("%s\n", __func__);
183 /* Enable the SPI hardware */
184 setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
189 static int stm32_spi_disable(struct stm32_spi_priv *priv)
191 debug("%s\n", __func__);
193 /* Disable the SPI hardware */
194 clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
199 static int stm32_spi_claim_bus(struct udevice *slave)
201 struct udevice *bus = dev_get_parent(slave);
202 struct stm32_spi_priv *priv = dev_get_priv(bus);
204 debug("%s\n", __func__);
206 /* Enable the SPI hardware */
207 return stm32_spi_enable(priv);
210 static int stm32_spi_release_bus(struct udevice *slave)
212 struct udevice *bus = dev_get_parent(slave);
213 struct stm32_spi_priv *priv = dev_get_priv(bus);
215 debug("%s\n", __func__);
217 /* Disable the SPI hardware */
218 return stm32_spi_disable(priv);
221 static void stm32_spi_stopxfer(struct udevice *dev)
223 struct stm32_spi_priv *priv = dev_get_priv(dev);
227 debug("%s\n", __func__);
229 cr1 = readl(priv->base + STM32_SPI_CR1);
231 if (!(cr1 & SPI_CR1_SPE))
234 /* Wait on EOT or suspend the flow */
235 ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr,
236 !(sr & SPI_SR_EOT), 100000);
238 if (cr1 & SPI_CR1_CSTART) {
239 writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1);
240 if (readl_poll_timeout(priv->base + STM32_SPI_SR,
241 sr, !(sr & SPI_SR_SUSP),
243 dev_err(dev, "Suspend request timeout\n");
247 /* clear status flags */
248 setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
251 static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
253 struct stm32_spi_priv *priv = dev_get_priv(dev);
255 debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
257 if (cs >= MAX_CS_COUNT)
260 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
266 return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
269 static int stm32_spi_set_mode(struct udevice *bus, uint mode)
271 struct stm32_spi_priv *priv = dev_get_priv(bus);
272 u32 cfg2_clrb = 0, cfg2_setb = 0;
274 debug("%s: mode=%d\n", __func__, mode);
277 cfg2_setb |= SPI_CFG2_CPOL;
279 cfg2_clrb |= SPI_CFG2_CPOL;
282 cfg2_setb |= SPI_CFG2_CPHA;
284 cfg2_clrb |= SPI_CFG2_CPHA;
286 if (mode & SPI_LSB_FIRST)
287 cfg2_setb |= SPI_CFG2_LSBFRST;
289 cfg2_clrb |= SPI_CFG2_LSBFRST;
291 if (cfg2_clrb || cfg2_setb)
292 clrsetbits_le32(priv->base + STM32_SPI_CFG2,
293 cfg2_clrb, cfg2_setb);
295 if (mode & SPI_CS_HIGH)
296 priv->cs_high = true;
298 priv->cs_high = false;
302 static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
304 struct stm32_spi_priv *priv = dev_get_priv(dev);
305 u32 fthlv, half_fifo;
307 /* data packet should not exceed 1/2 of fifo space */
308 half_fifo = (priv->fifo_size / 2);
310 /* data_packet should not exceed transfer length */
311 fthlv = (half_fifo > xfer_len) ? xfer_len : half_fifo;
313 /* align packet size with data registers access */
314 fthlv -= (fthlv % 4);
318 clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
319 (fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
324 static int stm32_spi_set_speed(struct udevice *bus, uint hz)
326 struct stm32_spi_priv *priv = dev_get_priv(bus);
330 debug("%s: hz=%d\n", __func__, hz);
332 if (priv->cur_hz == hz)
335 div = DIV_ROUND_UP(priv->bus_clk_rate, hz);
337 if (div < STM32_MBR_DIV_MIN ||
338 div > STM32_MBR_DIV_MAX)
341 /* Determine the first power of 2 greater than or equal to div */
345 mbrdiv = fls(div) - 1;
350 clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
351 (mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
358 static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
359 const void *dout, void *din, unsigned long flags)
361 struct udevice *bus = dev_get_parent(slave);
362 struct dm_spi_slave_platdata *slave_plat;
363 struct stm32_spi_priv *priv = dev_get_priv(bus);
370 xferlen = bitlen / 8;
372 if (xferlen <= SPI_CR2_TSIZE)
373 writel(xferlen, priv->base + STM32_SPI_CR2);
379 priv->tx_len = priv->tx_buf ? bitlen / 8 : 0;
380 priv->rx_len = priv->rx_buf ? bitlen / 8 : 0;
382 mode = SPI_FULL_DUPLEX;
384 mode = SPI_SIMPLEX_RX;
385 else if (!priv->rx_buf)
386 mode = SPI_SIMPLEX_TX;
388 if (priv->cur_xferlen != xferlen || priv->cur_mode != mode) {
389 priv->cur_mode = mode;
390 priv->cur_xferlen = xferlen;
392 /* Disable the SPI hardware to unlock CFG1/CFG2 registers */
393 stm32_spi_disable(priv);
395 clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM,
396 mode << SPI_CFG2_COMM_SHIFT);
398 stm32_spi_set_fthlv(bus, xferlen);
400 /* Enable the SPI hardware */
401 stm32_spi_enable(priv);
404 debug("%s: priv->tx_len=%d priv->rx_len=%d\n", __func__,
405 priv->tx_len, priv->rx_len);
407 slave_plat = dev_get_parent_platdata(slave);
408 if (flags & SPI_XFER_BEGIN)
409 stm32_spi_set_cs(bus, slave_plat->cs, false);
411 /* Be sure to have data in fifo before starting data transfer */
413 stm32_spi_write_txfifo(priv);
415 setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART);
418 sr = readl(priv->base + STM32_SPI_SR);
420 if (sr & SPI_SR_OVR) {
421 dev_err(bus, "Overrun: RX data lost\n");
426 if (sr & SPI_SR_SUSP) {
427 dev_warn(bus, "System too slow is limiting data throughput\n");
429 if (priv->rx_buf && priv->rx_len > 0)
430 stm32_spi_read_rxfifo(priv);
435 if (sr & SPI_SR_TXTF)
439 if (priv->tx_buf && priv->tx_len > 0)
440 stm32_spi_write_txfifo(priv);
443 if (priv->rx_buf && priv->rx_len > 0)
444 stm32_spi_read_rxfifo(priv);
446 if (sr & SPI_SR_EOT) {
447 if (priv->rx_buf && priv->rx_len > 0)
448 stm32_spi_read_rxfifo(priv);
452 writel(ifcr, priv->base + STM32_SPI_IFCR);
455 /* clear status flags */
456 setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
457 stm32_spi_stopxfer(bus);
459 if (flags & SPI_XFER_END)
460 stm32_spi_set_cs(bus, slave_plat->cs, true);
465 static int stm32_spi_get_fifo_size(struct udevice *dev)
467 struct stm32_spi_priv *priv = dev_get_priv(dev);
470 stm32_spi_enable(priv);
472 while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)
473 writeb(++count, priv->base + STM32_SPI_TXDR);
475 stm32_spi_disable(priv);
477 debug("%s %d x 8-bit fifo size\n", __func__, count);
482 static int stm32_spi_probe(struct udevice *dev)
484 struct stm32_spi_priv *priv = dev_get_priv(dev);
485 unsigned long clk_rate;
489 priv->base = dev_remap_addr(dev);
494 ret = clk_get_by_index(dev, 0, &priv->clk);
498 ret = clk_enable(&priv->clk);
502 clk_rate = clk_get_rate(&priv->clk);
508 priv->bus_clk_rate = clk_rate;
511 ret = reset_get_by_index(dev, 0, &priv->rst_ctl);
515 reset_assert(&priv->rst_ctl);
517 reset_deassert(&priv->rst_ctl);
519 ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
520 ARRAY_SIZE(priv->cs_gpios), 0);
522 pr_err("Can't get %s cs gpios: %d", dev->name, ret);
526 priv->fifo_size = stm32_spi_get_fifo_size(dev);
528 priv->cur_mode = SPI_FULL_DUPLEX;
529 priv->cur_xferlen = 0;
530 priv->cur_bpw = SPI_DEFAULT_WORDLEN;
531 clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
534 for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
535 if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
538 dm_gpio_set_dir_flags(&priv->cs_gpios[i],
539 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
542 /* Ensure I2SMOD bit is kept cleared */
543 clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
546 * - SS input value high
547 * - transmitter half duplex direction
548 * - automatic communication suspend when RX-Fifo is full
550 setbits_le32(priv->base + STM32_SPI_CR1,
551 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX);
554 * - Set the master mode (default Motorola mode)
555 * - Consider 1 master/n slaves configuration and
556 * SS input value is determined by the SSI bit
557 * - keep control of all associated GPIOs
559 setbits_le32(priv->base + STM32_SPI_CFG2,
560 SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR);
565 reset_free(&priv->rst_ctl);
568 clk_disable(&priv->clk);
569 clk_free(&priv->clk);
574 static int stm32_spi_remove(struct udevice *dev)
576 struct stm32_spi_priv *priv = dev_get_priv(dev);
579 stm32_spi_stopxfer(dev);
580 stm32_spi_disable(priv);
582 ret = reset_assert(&priv->rst_ctl);
586 reset_free(&priv->rst_ctl);
588 ret = clk_disable(&priv->clk);
592 clk_free(&priv->clk);
597 static const struct dm_spi_ops stm32_spi_ops = {
598 .claim_bus = stm32_spi_claim_bus,
599 .release_bus = stm32_spi_release_bus,
600 .set_mode = stm32_spi_set_mode,
601 .set_speed = stm32_spi_set_speed,
602 .xfer = stm32_spi_xfer,
605 static const struct udevice_id stm32_spi_ids[] = {
606 { .compatible = "st,stm32h7-spi", },
610 U_BOOT_DRIVER(stm32_spi) = {
613 .of_match = stm32_spi_ids,
614 .ops = &stm32_spi_ops,
615 .priv_auto_alloc_size = sizeof(struct stm32_spi_priv),
616 .probe = stm32_spi_probe,
617 .remove = stm32_spi_remove,