4 * Michael Kurz, <michi.kurz@gmail.com>
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <spi_flash.h>
18 #include <asm/arch/stm32.h>
19 #include <asm/arch/stm32_defs.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 struct stm32_qspi_regs {
41 * QUADSPI control register
43 #define STM32_QSPI_CR_EN BIT(0)
44 #define STM32_QSPI_CR_ABORT BIT(1)
45 #define STM32_QSPI_CR_DMAEN BIT(2)
46 #define STM32_QSPI_CR_TCEN BIT(3)
47 #define STM32_QSPI_CR_SSHIFT BIT(4)
48 #define STM32_QSPI_CR_DFM BIT(6)
49 #define STM32_QSPI_CR_FSEL BIT(7)
50 #define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0)
51 #define STM32_QSPI_CR_FTHRES_SHIFT (8)
52 #define STM32_QSPI_CR_TEIE BIT(16)
53 #define STM32_QSPI_CR_TCIE BIT(17)
54 #define STM32_QSPI_CR_FTIE BIT(18)
55 #define STM32_QSPI_CR_SMIE BIT(19)
56 #define STM32_QSPI_CR_TOIE BIT(20)
57 #define STM32_QSPI_CR_APMS BIT(22)
58 #define STM32_QSPI_CR_PMM BIT(23)
59 #define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
60 #define STM32_QSPI_CR_PRESCALER_SHIFT (24)
63 * QUADSPI device configuration register
65 #define STM32_QSPI_DCR_CKMODE BIT(0)
66 #define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
67 #define STM32_QSPI_DCR_CSHT_SHIFT (8)
68 #define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
69 #define STM32_QSPI_DCR_FSIZE_SHIFT (16)
72 * QUADSPI status register
74 #define STM32_QSPI_SR_TEF BIT(0)
75 #define STM32_QSPI_SR_TCF BIT(1)
76 #define STM32_QSPI_SR_FTF BIT(2)
77 #define STM32_QSPI_SR_SMF BIT(3)
78 #define STM32_QSPI_SR_TOF BIT(4)
79 #define STM32_QSPI_SR_BUSY BIT(5)
80 #define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0)
81 #define STM32_QSPI_SR_FLEVEL_SHIFT (8)
84 * QUADSPI flag clear register
86 #define STM32_QSPI_FCR_CTEF BIT(0)
87 #define STM32_QSPI_FCR_CTCF BIT(1)
88 #define STM32_QSPI_FCR_CSMF BIT(3)
89 #define STM32_QSPI_FCR_CTOF BIT(4)
92 * QUADSPI communication configuration register
94 #define STM32_QSPI_CCR_DDRM BIT(31)
95 #define STM32_QSPI_CCR_DHHC BIT(30)
96 #define STM32_QSPI_CCR_SIOO BIT(28)
97 #define STM32_QSPI_CCR_FMODE_SHIFT (26)
98 #define STM32_QSPI_CCR_DMODE_SHIFT (24)
99 #define STM32_QSPI_CCR_DCYC_SHIFT (18)
100 #define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0)
101 #define STM32_QSPI_CCR_ABSIZE_SHIFT (16)
102 #define STM32_QSPI_CCR_ABMODE_SHIFT (14)
103 #define STM32_QSPI_CCR_ADSIZE_SHIFT (12)
104 #define STM32_QSPI_CCR_ADMODE_SHIFT (10)
105 #define STM32_QSPI_CCR_IMODE_SHIFT (8)
106 #define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0)
108 enum STM32_QSPI_CCR_IMODE {
109 STM32_QSPI_CCR_IMODE_NONE = 0,
110 STM32_QSPI_CCR_IMODE_ONE_LINE = 1,
111 STM32_QSPI_CCR_IMODE_TWO_LINE = 2,
112 STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,
115 enum STM32_QSPI_CCR_ADMODE {
116 STM32_QSPI_CCR_ADMODE_NONE = 0,
117 STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,
118 STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,
119 STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,
122 enum STM32_QSPI_CCR_ADSIZE {
123 STM32_QSPI_CCR_ADSIZE_8BIT = 0,
124 STM32_QSPI_CCR_ADSIZE_16BIT = 1,
125 STM32_QSPI_CCR_ADSIZE_24BIT = 2,
126 STM32_QSPI_CCR_ADSIZE_32BIT = 3,
129 enum STM32_QSPI_CCR_ABMODE {
130 STM32_QSPI_CCR_ABMODE_NONE = 0,
131 STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,
132 STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,
133 STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,
136 enum STM32_QSPI_CCR_ABSIZE {
137 STM32_QSPI_CCR_ABSIZE_8BIT = 0,
138 STM32_QSPI_CCR_ABSIZE_16BIT = 1,
139 STM32_QSPI_CCR_ABSIZE_24BIT = 2,
140 STM32_QSPI_CCR_ABSIZE_32BIT = 3,
143 enum STM32_QSPI_CCR_DMODE {
144 STM32_QSPI_CCR_DMODE_NONE = 0,
145 STM32_QSPI_CCR_DMODE_ONE_LINE = 1,
146 STM32_QSPI_CCR_DMODE_TWO_LINE = 2,
147 STM32_QSPI_CCR_DMODE_FOUR_LINE = 3,
150 enum STM32_QSPI_CCR_FMODE {
151 STM32_QSPI_CCR_IND_WRITE = 0,
152 STM32_QSPI_CCR_IND_READ = 1,
153 STM32_QSPI_CCR_AUTO_POLL = 2,
154 STM32_QSPI_CCR_MEM_MAP = 3,
157 /* default SCK frequency, unit: HZ */
158 #define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
160 struct stm32_qspi_platdata {
166 struct stm32_qspi_priv {
167 struct stm32_qspi_regs *regs;
174 #define CMD_HAS_ADR BIT(24)
175 #define CMD_HAS_DUMMY BIT(25)
176 #define CMD_HAS_DATA BIT(26)
179 static void _stm32_qspi_disable(struct stm32_qspi_priv *priv)
181 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
184 static void _stm32_qspi_enable(struct stm32_qspi_priv *priv)
186 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
189 static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
191 while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY)
195 static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv)
197 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF))
201 static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
203 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF))
207 static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
209 u32 fsize = fls(size) - 1;
210 clrsetbits_le32(&priv->regs->dcr,
211 STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
212 fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
215 static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
217 unsigned int ccr_reg = 0;
218 u8 imode, admode, dmode;
219 u32 mode = priv->mode;
220 u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);
222 imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
223 admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
225 if (mode & SPI_RX_QUAD) {
226 dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
227 if (mode & SPI_TX_QUAD) {
228 imode = STM32_QSPI_CCR_IMODE_FOUR_LINE;
229 admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE;
231 } else if (mode & SPI_RX_DUAL) {
232 dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
233 if (mode & SPI_TX_DUAL) {
234 imode = STM32_QSPI_CCR_IMODE_TWO_LINE;
235 admode = STM32_QSPI_CCR_ADMODE_TWO_LINE;
238 dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
241 if (priv->command & CMD_HAS_DATA)
242 ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT);
244 if (priv->command & CMD_HAS_DUMMY)
245 ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK)
246 << STM32_QSPI_CCR_DCYC_SHIFT);
248 if (priv->command & CMD_HAS_ADR) {
249 ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT
250 << STM32_QSPI_CCR_ADSIZE_SHIFT);
251 ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
253 ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
258 static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
259 struct spi_flash *flash)
261 priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA
263 priv->dummycycles = flash->dummy_byte * 8;
265 unsigned int ccr_reg = _stm32_qspi_gen_ccr(priv);
266 ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
268 _stm32_qspi_wait_for_not_busy(priv);
270 writel(ccr_reg, &priv->regs->ccr);
272 priv->dummycycles = 0;
275 static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv)
277 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
280 static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv,
283 writel(length - 1, &priv->regs->dlr);
286 static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
288 writel(cr_reg, &priv->regs->ccr);
290 if (priv->command & CMD_HAS_ADR)
291 writel(priv->address, &priv->regs->ar);
294 static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
295 struct spi_flash *flash, unsigned int bitlen,
296 const u8 *dout, u8 *din, unsigned long flags)
298 unsigned int words = bitlen / 8;
300 if (flags & SPI_XFER_MMAP) {
301 _stm32_qspi_enable_mmap(priv, flash);
303 } else if (flags & SPI_XFER_MMAP_END) {
304 _stm32_qspi_disable_mmap(priv);
312 debug("spi_xfer: Non byte aligned SPI transfer\n");
317 debug("spi_xfer: QSPI cannot have data in and data out set\n");
321 if (!dout && (flags & SPI_XFER_BEGIN)) {
322 debug("spi_xfer: QSPI transfer must begin with command\n");
327 if (flags & SPI_XFER_BEGIN) {
328 /* data is command */
329 priv->command = dout[0] | CMD_HAS_DATA;
331 /* address is here too */
332 priv->address = (dout[1] << 16) |
333 (dout[2] << 8) | dout[3];
334 priv->command |= CMD_HAS_ADR;
338 /* rest is dummy bytes */
339 priv->dummycycles = (words - 4) * 8;
340 priv->command |= CMD_HAS_DUMMY;
343 if (flags & SPI_XFER_END) {
344 /* command without data */
345 priv->command &= ~(CMD_HAS_DATA);
349 if (flags & SPI_XFER_END) {
350 u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
351 ccr_reg |= STM32_QSPI_CCR_IND_WRITE
352 << STM32_QSPI_CCR_FMODE_SHIFT;
354 _stm32_qspi_wait_for_not_busy(priv);
356 if (priv->command & CMD_HAS_DATA)
357 _stm32_qspi_set_xfer_length(priv, words);
359 _stm32_qspi_start_xfer(priv, ccr_reg);
361 debug("%s: write: ccr:0x%08x adr:0x%08x\n",
362 __func__, priv->regs->ccr, priv->regs->ar);
364 if (priv->command & CMD_HAS_DATA) {
365 _stm32_qspi_wait_for_ftf(priv);
367 debug("%s: words:%d data:", __func__, words);
371 writeb(dout[i], &priv->regs->dr);
372 debug("%02x ", dout[i]);
377 _stm32_qspi_wait_for_complete(priv);
379 _stm32_qspi_wait_for_not_busy(priv);
383 u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
384 ccr_reg |= STM32_QSPI_CCR_IND_READ
385 << STM32_QSPI_CCR_FMODE_SHIFT;
387 _stm32_qspi_wait_for_not_busy(priv);
389 _stm32_qspi_set_xfer_length(priv, words);
391 _stm32_qspi_start_xfer(priv, ccr_reg);
393 debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__,
394 priv->regs->ccr, priv->regs->ar, priv->regs->dlr);
396 debug("%s: data:", __func__);
400 din[i] = readb(&priv->regs->dr);
401 debug("%02x ", din[i]);
410 static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
412 struct fdt_resource res_regs, res_mem;
413 struct stm32_qspi_platdata *plat = bus->platdata;
414 const void *blob = gd->fdt_blob;
415 int node = dev_of_offset(bus);
418 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
419 "QuadSPI", &res_regs);
421 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
424 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
425 "QuadSPI-memory", &res_mem);
427 debug("Error: can't get mmap base address(ret = %d)!\n", ret);
431 plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
432 STM32_QSPI_DEFAULT_SCK_FREQ);
434 plat->base = res_regs.start;
435 plat->memory_map = res_mem.start;
437 debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n",
447 static int stm32_qspi_probe(struct udevice *bus)
449 struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
450 struct stm32_qspi_priv *priv = dev_get_priv(bus);
451 struct dm_spi_bus *dm_spi_bus;
453 dm_spi_bus = bus->uclass_priv;
455 dm_spi_bus->max_hz = plat->max_hz;
457 priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base;
459 priv->max_hz = plat->max_hz;
464 ret = clk_get_by_index(bus, 0, &clk);
468 ret = clk_enable(&clk);
471 dev_err(bus, "failed to enable clock\n");
476 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
481 static int stm32_qspi_remove(struct udevice *bus)
486 static int stm32_qspi_claim_bus(struct udevice *dev)
488 struct stm32_qspi_priv *priv;
490 struct spi_flash *flash;
493 priv = dev_get_priv(bus);
494 flash = dev_get_uclass_priv(dev);
496 _stm32_qspi_set_flash_size(priv, flash->size);
498 _stm32_qspi_enable(priv);
503 static int stm32_qspi_release_bus(struct udevice *dev)
505 struct stm32_qspi_priv *priv;
509 priv = dev_get_priv(bus);
511 _stm32_qspi_disable(priv);
516 static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
517 const void *dout, void *din, unsigned long flags)
519 struct stm32_qspi_priv *priv;
521 struct spi_flash *flash;
524 priv = dev_get_priv(bus);
525 flash = dev_get_uclass_priv(dev);
527 return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout,
531 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
533 struct stm32_qspi_platdata *plat = bus->platdata;
534 struct stm32_qspi_priv *priv = dev_get_priv(bus);
536 if (speed > plat->max_hz)
537 speed = plat->max_hz;
539 u32 qspi_clk = clock_get(CLOCK_AHB);
542 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
545 else if (prescaler < 0)
549 u32 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
550 csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
552 _stm32_qspi_wait_for_not_busy(priv);
554 clrsetbits_le32(&priv->regs->cr,
555 STM32_QSPI_CR_PRESCALER_MASK <<
556 STM32_QSPI_CR_PRESCALER_SHIFT,
557 prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
560 clrsetbits_le32(&priv->regs->dcr,
561 STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
562 csht << STM32_QSPI_DCR_CSHT_SHIFT);
564 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
565 (qspi_clk / (prescaler + 1)));
570 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
572 struct stm32_qspi_priv *priv = dev_get_priv(bus);
574 _stm32_qspi_wait_for_not_busy(priv);
576 if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
577 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
578 else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
579 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
583 if (mode & SPI_CS_HIGH)
586 if (mode & SPI_RX_QUAD)
587 priv->mode |= SPI_RX_QUAD;
588 else if (mode & SPI_RX_DUAL)
589 priv->mode |= SPI_RX_DUAL;
591 priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL);
593 if (mode & SPI_TX_QUAD)
594 priv->mode |= SPI_TX_QUAD;
595 else if (mode & SPI_TX_DUAL)
596 priv->mode |= SPI_TX_DUAL;
598 priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL);
600 debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
602 if (mode & SPI_RX_QUAD)
604 else if (mode & SPI_RX_DUAL)
607 debug("single, tx: ");
609 if (mode & SPI_TX_QUAD)
611 else if (mode & SPI_TX_DUAL)
619 static const struct dm_spi_ops stm32_qspi_ops = {
620 .claim_bus = stm32_qspi_claim_bus,
621 .release_bus = stm32_qspi_release_bus,
622 .xfer = stm32_qspi_xfer,
623 .set_speed = stm32_qspi_set_speed,
624 .set_mode = stm32_qspi_set_mode,
627 static const struct udevice_id stm32_qspi_ids[] = {
628 { .compatible = "st,stm32-qspi" },
632 U_BOOT_DRIVER(stm32_qspi) = {
633 .name = "stm32_qspi",
635 .of_match = stm32_qspi_ids,
636 .ops = &stm32_qspi_ops,
637 .ofdata_to_platdata = stm32_qspi_ofdata_to_platdata,
638 .platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata),
639 .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
640 .probe = stm32_qspi_probe,
641 .remove = stm32_qspi_remove,