1 // SPDX-License-Identifier: GPL-2.0+
5 * Michael Kurz, <michi.kurz@gmail.com>
14 #include <dm/device_compat.h>
15 #include <linux/iopoll.h>
16 #include <linux/ioport.h>
17 #include <linux/sizes.h>
19 struct stm32_qspi_regs {
36 * QUADSPI control register
38 #define STM32_QSPI_CR_EN BIT(0)
39 #define STM32_QSPI_CR_ABORT BIT(1)
40 #define STM32_QSPI_CR_DMAEN BIT(2)
41 #define STM32_QSPI_CR_TCEN BIT(3)
42 #define STM32_QSPI_CR_SSHIFT BIT(4)
43 #define STM32_QSPI_CR_DFM BIT(6)
44 #define STM32_QSPI_CR_FSEL BIT(7)
45 #define STM32_QSPI_CR_FTHRES_SHIFT 8
46 #define STM32_QSPI_CR_TEIE BIT(16)
47 #define STM32_QSPI_CR_TCIE BIT(17)
48 #define STM32_QSPI_CR_FTIE BIT(18)
49 #define STM32_QSPI_CR_SMIE BIT(19)
50 #define STM32_QSPI_CR_TOIE BIT(20)
51 #define STM32_QSPI_CR_APMS BIT(22)
52 #define STM32_QSPI_CR_PMM BIT(23)
53 #define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
54 #define STM32_QSPI_CR_PRESCALER_SHIFT 24
57 * QUADSPI device configuration register
59 #define STM32_QSPI_DCR_CKMODE BIT(0)
60 #define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
61 #define STM32_QSPI_DCR_CSHT_SHIFT 8
62 #define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
63 #define STM32_QSPI_DCR_FSIZE_SHIFT 16
66 * QUADSPI status register
68 #define STM32_QSPI_SR_TEF BIT(0)
69 #define STM32_QSPI_SR_TCF BIT(1)
70 #define STM32_QSPI_SR_FTF BIT(2)
71 #define STM32_QSPI_SR_SMF BIT(3)
72 #define STM32_QSPI_SR_TOF BIT(4)
73 #define STM32_QSPI_SR_BUSY BIT(5)
76 * QUADSPI flag clear register
78 #define STM32_QSPI_FCR_CTEF BIT(0)
79 #define STM32_QSPI_FCR_CTCF BIT(1)
80 #define STM32_QSPI_FCR_CSMF BIT(3)
81 #define STM32_QSPI_FCR_CTOF BIT(4)
84 * QUADSPI communication configuration register
86 #define STM32_QSPI_CCR_DDRM BIT(31)
87 #define STM32_QSPI_CCR_DHHC BIT(30)
88 #define STM32_QSPI_CCR_SIOO BIT(28)
89 #define STM32_QSPI_CCR_FMODE_SHIFT 26
90 #define STM32_QSPI_CCR_DMODE_SHIFT 24
91 #define STM32_QSPI_CCR_DCYC_SHIFT 18
92 #define STM32_QSPI_CCR_ABSIZE_SHIFT 16
93 #define STM32_QSPI_CCR_ABMODE_SHIFT 14
94 #define STM32_QSPI_CCR_ADSIZE_SHIFT 12
95 #define STM32_QSPI_CCR_ADMODE_SHIFT 10
96 #define STM32_QSPI_CCR_IMODE_SHIFT 8
98 #define STM32_QSPI_CCR_IND_WRITE 0
99 #define STM32_QSPI_CCR_IND_READ 1
100 #define STM32_QSPI_CCR_MEM_MAP 3
102 #define STM32_QSPI_MAX_MMAP_SZ SZ_256M
103 #define STM32_QSPI_MAX_CHIP 2
105 #define STM32_QSPI_FIFO_TIMEOUT_US 30000
106 #define STM32_QSPI_CMD_TIMEOUT_US 1000000
107 #define STM32_BUSY_TIMEOUT_US 100000
108 #define STM32_ABT_TIMEOUT_US 100000
110 struct stm32_qspi_flash {
116 struct stm32_qspi_priv {
117 struct stm32_qspi_regs *regs;
118 struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
119 void __iomem *mm_base;
120 resource_size_t mm_size;
125 static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
130 ret = readl_poll_timeout(&priv->regs->sr, sr,
131 !(sr & STM32_QSPI_SR_BUSY),
132 STM32_BUSY_TIMEOUT_US);
134 pr_err("busy timeout (stat:%#x)\n", sr);
139 static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
140 const struct spi_mem_op *op)
145 if (!op->data.nbytes)
146 return _stm32_qspi_wait_for_not_busy(priv);
148 ret = readl_poll_timeout(&priv->regs->sr, sr,
149 sr & STM32_QSPI_SR_TCF,
150 STM32_QSPI_CMD_TIMEOUT_US);
152 pr_err("cmd timeout (stat:%#x)\n", sr);
153 } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
154 pr_err("transfer error (stat:%#x)\n", sr);
159 writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
164 static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
169 static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
174 static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
175 const struct spi_mem_op *op)
177 void (*fifo)(u8 *val, void __iomem *addr);
178 u32 len = op->data.nbytes, sr;
182 if (op->data.dir == SPI_MEM_DATA_IN) {
183 fifo = _stm32_qspi_read_fifo;
184 buf = op->data.buf.in;
187 fifo = _stm32_qspi_write_fifo;
188 buf = (u8 *)op->data.buf.out;
192 ret = readl_poll_timeout(&priv->regs->sr, sr,
193 sr & STM32_QSPI_SR_FTF,
194 STM32_QSPI_FIFO_TIMEOUT_US);
196 pr_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
200 fifo(buf++, &priv->regs->dr);
206 static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
207 const struct spi_mem_op *op)
209 memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
215 static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
216 const struct spi_mem_op *op,
219 if (!op->data.nbytes)
222 if (mode == STM32_QSPI_CCR_MEM_MAP)
223 return stm32_qspi_mm(priv, op);
225 return _stm32_qspi_poll(priv, op);
228 static int _stm32_qspi_get_mode(u8 buswidth)
236 static int stm32_qspi_exec_op(struct spi_slave *slave,
237 const struct spi_mem_op *op)
239 struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
240 u32 cr, ccr, addr_max;
241 u8 mode = STM32_QSPI_CCR_IND_WRITE;
244 debug("%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
245 __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
246 op->dummy.buswidth, op->data.buswidth,
247 op->addr.val, op->data.nbytes);
249 ret = _stm32_qspi_wait_for_not_busy(priv);
253 addr_max = op->addr.val + op->data.nbytes + 1;
255 if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
256 if (addr_max < priv->mm_size && op->addr.buswidth)
257 mode = STM32_QSPI_CCR_MEM_MAP;
259 mode = STM32_QSPI_CCR_IND_READ;
263 writel(op->data.nbytes - 1, &priv->regs->dlr);
265 ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
266 ccr |= op->cmd.opcode;
267 ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
268 << STM32_QSPI_CCR_IMODE_SHIFT);
270 if (op->addr.nbytes) {
271 ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
272 ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
273 << STM32_QSPI_CCR_ADMODE_SHIFT);
276 if (op->dummy.buswidth && op->dummy.nbytes)
277 ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
278 << STM32_QSPI_CCR_DCYC_SHIFT);
281 ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
282 << STM32_QSPI_CCR_DMODE_SHIFT);
284 writel(ccr, &priv->regs->ccr);
286 if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
287 writel(op->addr.val, &priv->regs->ar);
289 ret = _stm32_qspi_tx(priv, op, mode);
293 * -read memory map: prefetching must be stopped if we read the last
294 * byte of device (device size - fifo size). like device size is not
295 * knows, the prefetching is always stop.
297 if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
300 /* Wait end of tx in indirect mode */
301 ret = _stm32_qspi_wait_cmd(priv, op);
308 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
310 /* Wait clear of abort bit by hw */
311 timeout = readl_poll_timeout(&priv->regs->cr, cr,
312 !(cr & STM32_QSPI_CR_ABORT),
313 STM32_ABT_TIMEOUT_US);
315 writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
318 pr_err("%s ret:%d abort timeout:%d\n", __func__, ret, timeout);
323 static int stm32_qspi_probe(struct udevice *bus)
325 struct stm32_qspi_priv *priv = dev_get_priv(bus);
328 struct reset_ctl reset_ctl;
331 ret = dev_read_resource_byname(bus, "qspi", &res);
333 dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
337 priv->regs = (struct stm32_qspi_regs *)res.start;
339 ret = dev_read_resource_byname(bus, "qspi_mm", &res);
341 dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
345 priv->mm_base = (void __iomem *)res.start;
347 priv->mm_size = resource_size(&res);
348 if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
351 debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
352 __func__, priv->regs, priv->mm_base, priv->mm_size);
354 ret = clk_get_by_index(bus, 0, &clk);
358 ret = clk_enable(&clk);
360 dev_err(bus, "failed to enable clock\n");
364 priv->clock_rate = clk_get_rate(&clk);
365 if (!priv->clock_rate) {
370 ret = reset_get_by_index(bus, 0, &reset_ctl);
372 if (ret != -ENOENT) {
373 dev_err(bus, "failed to get reset\n");
378 /* Reset QSPI controller */
379 reset_assert(&reset_ctl);
381 reset_deassert(&reset_ctl);
386 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
388 /* Set dcr fsize to max address */
389 setbits_le32(&priv->regs->dcr,
390 STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
395 static int stm32_qspi_claim_bus(struct udevice *dev)
397 struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
398 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
399 int slave_cs = slave_plat->cs;
401 if (slave_cs >= STM32_QSPI_MAX_CHIP)
404 if (priv->cs_used != slave_cs) {
405 struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
407 priv->cs_used = slave_cs;
409 if (flash->initialized) {
410 /* Set the configuration: speed + cs */
411 writel(flash->cr, &priv->regs->cr);
412 writel(flash->dcr, &priv->regs->dcr);
414 /* Set chip select */
415 clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
416 priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
418 /* Save the configuration: speed + cs */
419 flash->cr = readl(&priv->regs->cr);
420 flash->dcr = readl(&priv->regs->dcr);
422 flash->initialized = true;
426 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
431 static int stm32_qspi_release_bus(struct udevice *dev)
433 struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
435 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
440 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
442 struct stm32_qspi_priv *priv = dev_get_priv(bus);
443 u32 qspi_clk = priv->clock_rate;
451 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
457 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
458 csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
460 ret = _stm32_qspi_wait_for_not_busy(priv);
464 clrsetbits_le32(&priv->regs->cr,
465 STM32_QSPI_CR_PRESCALER_MASK <<
466 STM32_QSPI_CR_PRESCALER_SHIFT,
467 prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
469 clrsetbits_le32(&priv->regs->dcr,
470 STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
471 csht << STM32_QSPI_DCR_CSHT_SHIFT);
473 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
474 (qspi_clk / (prescaler + 1)));
479 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
481 struct stm32_qspi_priv *priv = dev_get_priv(bus);
484 ret = _stm32_qspi_wait_for_not_busy(priv);
488 if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
489 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
490 else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
491 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
495 if (mode & SPI_CS_HIGH)
498 debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
500 if (mode & SPI_RX_QUAD)
502 else if (mode & SPI_RX_DUAL)
505 debug("single, tx: ");
507 if (mode & SPI_TX_QUAD)
509 else if (mode & SPI_TX_DUAL)
517 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
518 .exec_op = stm32_qspi_exec_op,
521 static const struct dm_spi_ops stm32_qspi_ops = {
522 .claim_bus = stm32_qspi_claim_bus,
523 .release_bus = stm32_qspi_release_bus,
524 .set_speed = stm32_qspi_set_speed,
525 .set_mode = stm32_qspi_set_mode,
526 .mem_ops = &stm32_qspi_mem_ops,
529 static const struct udevice_id stm32_qspi_ids[] = {
530 { .compatible = "st,stm32f469-qspi" },
534 U_BOOT_DRIVER(stm32_qspi) = {
535 .name = "stm32_qspi",
537 .of_match = stm32_qspi_ids,
538 .ops = &stm32_qspi_ops,
539 .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
540 .probe = stm32_qspi_probe,