2 * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
3 * S.J.R. van Schaik <stephan@whiteboxsystems.nl>
4 * M.B.W. Wajer <merlijn@whiteboxsystems.nl>
6 * (C) Copyright 2017 Olimex Ltd..
7 * Stefan Mavrodiev <stefan@olimex.com>
9 * Based on linux spi driver. Original copyright follows:
10 * linux/drivers/spi/spi-sun4i.c
12 * Copyright (C) 2012 - 2014 Allwinner Tech
13 * Pan Nan <pannan@allwinnertech.com>
15 * Copyright (C) 2014 Maxime Ripard
16 * Maxime Ripard <maxime.ripard@free-electrons.com>
18 * SPDX-License-Identifier: GPL-2.0+
26 #include <fdt_support.h>
30 #include <asm/bitops.h>
34 #include <linux/iopoll.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 /* sun4i spi registers */
39 #define SUN4I_RXDATA_REG 0x00
40 #define SUN4I_TXDATA_REG 0x04
41 #define SUN4I_CTL_REG 0x08
42 #define SUN4I_CLK_CTL_REG 0x1c
43 #define SUN4I_BURST_CNT_REG 0x20
44 #define SUN4I_XMIT_CNT_REG 0x24
45 #define SUN4I_FIFO_STA_REG 0x28
47 /* sun6i spi registers */
48 #define SUN6I_GBL_CTL_REG 0x04
49 #define SUN6I_TFR_CTL_REG 0x08
50 #define SUN6I_FIFO_CTL_REG 0x18
51 #define SUN6I_FIFO_STA_REG 0x1c
52 #define SUN6I_CLK_CTL_REG 0x24
53 #define SUN6I_BURST_CNT_REG 0x30
54 #define SUN6I_XMIT_CNT_REG 0x34
55 #define SUN6I_BURST_CTL_REG 0x38
56 #define SUN6I_TXDATA_REG 0x200
57 #define SUN6I_RXDATA_REG 0x300
60 #define SUN4I_CTL_ENABLE BIT(0)
61 #define SUN4I_CTL_MASTER BIT(1)
62 #define SUN4I_CLK_CTL_CDR2_MASK 0xff
63 #define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
64 #define SUN4I_CLK_CTL_CDR1_MASK 0xf
65 #define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
66 #define SUN4I_CLK_CTL_DRS BIT(12)
67 #define SUN4I_MAX_XFER_SIZE 0xffffff
68 #define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
69 #define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
70 #define SUN4I_FIFO_STA_RF_CNT_BITS 0
72 #define SUN4I_SPI_MAX_RATE 24000000
73 #define SUN4I_SPI_MIN_RATE 3000
74 #define SUN4I_SPI_DEFAULT_RATE 1000000
75 #define SUN4I_SPI_TIMEOUT_US 1000000
77 #define SPI_REG(priv, reg) ((priv)->base + \
78 (priv)->variant->regs[reg])
79 #define SPI_BIT(priv, bit) ((priv)->variant->bits[bit])
80 #define SPI_CS(priv, cs) (((cs) << SPI_BIT(priv, SPI_TCR_CS_SEL)) & \
81 SPI_BIT(priv, SPI_TCR_CS_MASK))
83 /* sun spi register set */
97 /* sun spi register bits */
103 SPI_TCR_CS_ACTIVE_LOW,
114 struct sun4i_spi_variant {
115 const unsigned long *regs;
122 struct sun4i_spi_platdata {
123 struct sun4i_spi_variant *variant;
128 struct sun4i_spi_priv {
129 struct sun4i_spi_variant *variant;
130 struct clk clk_ahb, clk_mod;
131 struct reset_ctl reset;
140 static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
145 byte = readb(SPI_REG(priv, SPI_RXD));
147 *priv->rx_buf++ = byte;
151 static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len)
156 byte = priv->tx_buf ? *priv->tx_buf++ : 0;
157 writeb(byte, SPI_REG(priv, SPI_TXD));
161 static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
163 struct sun4i_spi_priv *priv = dev_get_priv(bus);
166 reg = readl(SPI_REG(priv, SPI_TCR));
168 reg &= ~SPI_BIT(priv, SPI_TCR_CS_MASK);
169 reg |= SPI_CS(priv, cs);
172 reg &= ~SPI_BIT(priv, SPI_TCR_CS_LEVEL);
174 reg |= SPI_BIT(priv, SPI_TCR_CS_LEVEL);
176 writel(reg, SPI_REG(priv, SPI_TCR));
179 static int sun4i_spi_parse_pins(struct udevice *dev)
181 const void *fdt = gd->fdt_blob;
182 const char *pin_name;
185 int drive, pull = 0, pin, i;
189 list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size);
191 printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n");
196 phandle = fdt32_to_cpu(*list++);
197 size -= sizeof(*list);
199 offset = fdt_node_offset_by_phandle(fdt, phandle);
203 drive = fdt_getprop_u32_default_node(fdt, offset, 0,
204 "drive-strength", 0);
208 else if (drive <= 20)
210 else if (drive <= 30)
215 drive = fdt_getprop_u32_default_node(fdt, offset, 0,
218 drive = min(drive, 3);
221 if (fdt_get_property(fdt, offset, "bias-disable", NULL))
223 else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL))
225 else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL))
228 pull = fdt_getprop_u32_default_node(fdt, offset, 0,
234 pin_name = fdt_stringlist_get(fdt, offset,
237 pin_name = fdt_stringlist_get(fdt, offset,
244 pin = name_to_gpio(pin_name);
248 if (IS_ENABLED(CONFIG_MACH_SUN50I))
249 sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0);
251 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
252 sunxi_gpio_set_drv(pin, drive);
253 sunxi_gpio_set_pull(pin, pull);
259 static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable)
261 struct sun4i_spi_priv *priv = dev_get_priv(dev);
265 clk_disable(&priv->clk_ahb);
266 clk_disable(&priv->clk_mod);
267 if (reset_valid(&priv->reset))
268 reset_assert(&priv->reset);
272 ret = clk_enable(&priv->clk_ahb);
274 dev_err(dev, "failed to enable ahb clock (ret=%d)\n", ret);
278 ret = clk_enable(&priv->clk_mod);
280 dev_err(dev, "failed to enable mod clock (ret=%d)\n", ret);
284 if (reset_valid(&priv->reset)) {
285 ret = reset_deassert(&priv->reset);
287 dev_err(dev, "failed to deassert reset\n");
295 clk_disable(&priv->clk_mod);
297 clk_disable(&priv->clk_ahb);
301 static int sun4i_spi_claim_bus(struct udevice *dev)
303 struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
306 ret = sun4i_spi_set_clock(dev->parent, true);
310 setbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE |
311 SUN4I_CTL_MASTER | SPI_BIT(priv, SPI_GCR_TP));
313 if (priv->variant->has_soft_reset)
314 setbits_le32(SPI_REG(priv, SPI_GCR),
315 SPI_BIT(priv, SPI_GCR_SRST));
317 setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
318 SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
323 static int sun4i_spi_release_bus(struct udevice *dev)
325 struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
327 clrbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE);
329 sun4i_spi_set_clock(dev->parent, false);
334 static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
335 const void *dout, void *din, unsigned long flags)
337 struct udevice *bus = dev->parent;
338 struct sun4i_spi_priv *priv = dev_get_priv(bus);
339 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
341 u32 len = bitlen / 8;
350 debug("%s: non byte-aligned SPI transfer.\n", __func__);
354 if (flags & SPI_XFER_BEGIN)
355 sun4i_spi_set_cs(bus, slave_plat->cs, true);
358 setbits_le32(SPI_REG(priv, SPI_FCR), SPI_BIT(priv, SPI_FCR_RF_RST) |
359 SPI_BIT(priv, SPI_FCR_TF_RST));
362 /* Setup the transfer now... */
363 nbytes = min(len, (priv->variant->fifo_depth - 1));
365 /* Setup the counters */
366 writel(SUN4I_BURST_CNT(nbytes), SPI_REG(priv, SPI_BC));
367 writel(SUN4I_XMIT_CNT(nbytes), SPI_REG(priv, SPI_TC));
369 if (priv->variant->has_burst_ctl)
370 writel(SUN4I_BURST_CNT(nbytes),
371 SPI_REG(priv, SPI_BCTL));
373 /* Fill the TX FIFO */
374 sun4i_spi_fill_fifo(priv, nbytes);
376 /* Start the transfer */
377 setbits_le32(SPI_REG(priv, SPI_TCR),
378 SPI_BIT(priv, SPI_TCR_XCH));
380 /* Wait till RX FIFO to be empty */
381 ret = readl_poll_timeout(SPI_REG(priv, SPI_FSR),
384 SPI_BIT(priv, SPI_FSR_RF_CNT_MASK)) >>
385 SUN4I_FIFO_STA_RF_CNT_BITS) >= nbytes),
386 SUN4I_SPI_TIMEOUT_US);
388 printf("ERROR: sun4i_spi: Timeout transferring data\n");
389 sun4i_spi_set_cs(bus, slave_plat->cs, false);
393 /* Drain the RX FIFO */
394 sun4i_spi_drain_fifo(priv, nbytes);
399 if (flags & SPI_XFER_END)
400 sun4i_spi_set_cs(bus, slave_plat->cs, false);
405 static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
407 struct sun4i_spi_platdata *plat = dev_get_platdata(dev);
408 struct sun4i_spi_priv *priv = dev_get_priv(dev);
412 if (speed > plat->max_hz)
413 speed = plat->max_hz;
415 if (speed < SUN4I_SPI_MIN_RATE)
416 speed = SUN4I_SPI_MIN_RATE;
418 * Setup clock divider.
420 * We have two choices there. Either we can use the clock
421 * divide rate 1, which is calculated thanks to this formula:
422 * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
423 * Or we can use CDR2, which is calculated with the formula:
424 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
425 * Whether we use the former or the latter is set through the
428 * First try CDR2, and if we can't reach the expected
429 * frequency, fall back to CDR1.
432 div = SUN4I_SPI_MAX_RATE / (2 * speed);
433 reg = readl(SPI_REG(priv, SPI_CCR));
435 if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
439 reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
440 reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
442 div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed);
443 reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
444 reg |= SUN4I_CLK_CTL_CDR1(div);
448 writel(reg, SPI_REG(priv, SPI_CCR));
453 static int sun4i_spi_set_mode(struct udevice *dev, uint mode)
455 struct sun4i_spi_priv *priv = dev_get_priv(dev);
458 reg = readl(SPI_REG(priv, SPI_TCR));
459 reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA));
462 reg |= SPI_BIT(priv, SPI_TCR_CPOL);
465 reg |= SPI_BIT(priv, SPI_TCR_CPHA);
468 writel(reg, SPI_REG(priv, SPI_TCR));
473 static const struct dm_spi_ops sun4i_spi_ops = {
474 .claim_bus = sun4i_spi_claim_bus,
475 .release_bus = sun4i_spi_release_bus,
476 .xfer = sun4i_spi_xfer,
477 .set_speed = sun4i_spi_set_speed,
478 .set_mode = sun4i_spi_set_mode,
481 static int sun4i_spi_probe(struct udevice *bus)
483 struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
484 struct sun4i_spi_priv *priv = dev_get_priv(bus);
487 ret = clk_get_by_name(bus, "ahb", &priv->clk_ahb);
489 dev_err(dev, "failed to get ahb clock\n");
493 ret = clk_get_by_name(bus, "mod", &priv->clk_mod);
495 dev_err(dev, "failed to get mod clock\n");
499 ret = reset_get_by_index(bus, 0, &priv->reset);
500 if (ret && ret != -ENOENT) {
501 dev_err(dev, "failed to get reset\n");
505 sun4i_spi_parse_pins(bus);
507 priv->variant = plat->variant;
508 priv->base = plat->base;
509 priv->freq = plat->max_hz;
514 static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
516 struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
517 int node = dev_of_offset(bus);
519 plat->base = devfdt_get_addr(bus);
520 plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus);
521 plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
523 SUN4I_SPI_DEFAULT_RATE);
525 if (plat->max_hz > SUN4I_SPI_MAX_RATE)
526 plat->max_hz = SUN4I_SPI_MAX_RATE;
531 static const unsigned long sun4i_spi_regs[] = {
532 [SPI_GCR] = SUN4I_CTL_REG,
533 [SPI_TCR] = SUN4I_CTL_REG,
534 [SPI_FCR] = SUN4I_CTL_REG,
535 [SPI_FSR] = SUN4I_FIFO_STA_REG,
536 [SPI_CCR] = SUN4I_CLK_CTL_REG,
537 [SPI_BC] = SUN4I_BURST_CNT_REG,
538 [SPI_TC] = SUN4I_XMIT_CNT_REG,
539 [SPI_TXD] = SUN4I_TXDATA_REG,
540 [SPI_RXD] = SUN4I_RXDATA_REG,
543 static const u32 sun4i_spi_bits[] = {
544 [SPI_GCR_TP] = BIT(18),
545 [SPI_TCR_CPHA] = BIT(2),
546 [SPI_TCR_CPOL] = BIT(3),
547 [SPI_TCR_CS_ACTIVE_LOW] = BIT(4),
548 [SPI_TCR_XCH] = BIT(10),
549 [SPI_TCR_CS_SEL] = 12,
550 [SPI_TCR_CS_MASK] = 0x3000,
551 [SPI_TCR_CS_MANUAL] = BIT(16),
552 [SPI_TCR_CS_LEVEL] = BIT(17),
553 [SPI_FCR_TF_RST] = BIT(8),
554 [SPI_FCR_RF_RST] = BIT(9),
555 [SPI_FSR_RF_CNT_MASK] = GENMASK(6, 0),
558 static const unsigned long sun6i_spi_regs[] = {
559 [SPI_GCR] = SUN6I_GBL_CTL_REG,
560 [SPI_TCR] = SUN6I_TFR_CTL_REG,
561 [SPI_FCR] = SUN6I_FIFO_CTL_REG,
562 [SPI_FSR] = SUN6I_FIFO_STA_REG,
563 [SPI_CCR] = SUN6I_CLK_CTL_REG,
564 [SPI_BC] = SUN6I_BURST_CNT_REG,
565 [SPI_TC] = SUN6I_XMIT_CNT_REG,
566 [SPI_BCTL] = SUN6I_BURST_CTL_REG,
567 [SPI_TXD] = SUN6I_TXDATA_REG,
568 [SPI_RXD] = SUN6I_RXDATA_REG,
571 static const u32 sun6i_spi_bits[] = {
572 [SPI_GCR_TP] = BIT(7),
573 [SPI_GCR_SRST] = BIT(31),
574 [SPI_TCR_CPHA] = BIT(0),
575 [SPI_TCR_CPOL] = BIT(1),
576 [SPI_TCR_CS_ACTIVE_LOW] = BIT(2),
577 [SPI_TCR_CS_SEL] = 4,
578 [SPI_TCR_CS_MASK] = 0x30,
579 [SPI_TCR_CS_MANUAL] = BIT(6),
580 [SPI_TCR_CS_LEVEL] = BIT(7),
581 [SPI_TCR_XCH] = BIT(31),
582 [SPI_FCR_RF_RST] = BIT(15),
583 [SPI_FCR_TF_RST] = BIT(31),
584 [SPI_FSR_RF_CNT_MASK] = GENMASK(7, 0),
587 static const struct sun4i_spi_variant sun4i_a10_spi_variant = {
588 .regs = sun4i_spi_regs,
589 .bits = sun4i_spi_bits,
593 static const struct sun4i_spi_variant sun6i_a31_spi_variant = {
594 .regs = sun6i_spi_regs,
595 .bits = sun6i_spi_bits,
597 .has_soft_reset = true,
598 .has_burst_ctl = true,
601 static const struct sun4i_spi_variant sun8i_h3_spi_variant = {
602 .regs = sun6i_spi_regs,
603 .bits = sun6i_spi_bits,
605 .has_soft_reset = true,
606 .has_burst_ctl = true,
609 static const struct udevice_id sun4i_spi_ids[] = {
611 .compatible = "allwinner,sun4i-a10-spi",
612 .data = (ulong)&sun4i_a10_spi_variant,
615 .compatible = "allwinner,sun6i-a31-spi",
616 .data = (ulong)&sun6i_a31_spi_variant,
619 .compatible = "allwinner,sun8i-h3-spi",
620 .data = (ulong)&sun8i_h3_spi_variant,
625 U_BOOT_DRIVER(sun4i_spi) = {
628 .of_match = sun4i_spi_ids,
629 .ops = &sun4i_spi_ops,
630 .ofdata_to_platdata = sun4i_spi_ofdata_to_platdata,
631 .platdata_auto_alloc_size = sizeof(struct sun4i_spi_platdata),
632 .priv_auto_alloc_size = sizeof(struct sun4i_spi_priv),
633 .probe = sun4i_spi_probe,