1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018 SiFive, Inc.
4 * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
6 * SiFive SPI controller driver (master mode only)
11 #include <dm/device_compat.h>
16 #include <linux/bitops.h>
17 #include <linux/log2.h>
20 #define SIFIVE_SPI_MAX_CS 32
22 #define SIFIVE_SPI_DEFAULT_DEPTH 8
23 #define SIFIVE_SPI_DEFAULT_BITS 8
25 /* register offsets */
26 #define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
27 #define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
28 #define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
29 #define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
30 #define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
31 #define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
32 #define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
33 #define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
34 #define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
35 #define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
36 #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
37 #define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
38 #define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
39 #define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
40 #define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */
41 #define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
44 #define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
47 #define SIFIVE_SPI_SCKMODE_PHA BIT(0)
48 #define SIFIVE_SPI_SCKMODE_POL BIT(1)
49 #define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
50 SIFIVE_SPI_SCKMODE_POL)
53 #define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
54 #define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
55 #define SIFIVE_SPI_CSMODE_MODE_OFF 3U
58 #define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
59 #define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
60 #define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
61 #define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
64 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
65 #define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
66 #define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
67 #define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
70 #define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
71 #define SIFIVE_SPI_FMT_PROTO_DUAL 1U
72 #define SIFIVE_SPI_FMT_PROTO_QUAD 2U
73 #define SIFIVE_SPI_FMT_PROTO_MASK 3U
74 #define SIFIVE_SPI_FMT_ENDIAN BIT(2)
75 #define SIFIVE_SPI_FMT_DIR BIT(3)
76 #define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
77 #define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
80 #define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
81 #define SIFIVE_SPI_TXDATA_FULL BIT(31)
84 #define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
85 #define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
88 #define SIFIVE_SPI_IP_TXWM BIT(0)
89 #define SIFIVE_SPI_IP_RXWM BIT(1)
92 #define SIFIVE_SPI_PROTO_QUAD 4 /* 4 lines I/O protocol transfer */
93 #define SIFIVE_SPI_PROTO_DUAL 2 /* 2 lines I/O protocol transfer */
94 #define SIFIVE_SPI_PROTO_SINGLE 1 /* 1 line I/O protocol transfer */
97 void *regs; /* base address of the registers */
100 u32 cs_inactive; /* Level of the CS pins when inactive*/
106 static void sifive_spi_prep_device(struct sifive_spi *spi,
107 struct dm_spi_slave_platdata *slave_plat)
109 /* Update the chip select polarity */
110 if (slave_plat->mode & SPI_CS_HIGH)
111 spi->cs_inactive &= ~BIT(slave_plat->cs);
113 spi->cs_inactive |= BIT(slave_plat->cs);
114 writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
116 /* Select the correct device */
117 writel(slave_plat->cs, spi->regs + SIFIVE_SPI_REG_CSID);
120 static int sifive_spi_set_cs(struct sifive_spi *spi,
121 struct dm_spi_slave_platdata *slave_plat)
123 u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
125 if (slave_plat->mode & SPI_CS_HIGH)
126 cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;
128 writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE);
133 static void sifive_spi_clear_cs(struct sifive_spi *spi)
135 writel(SIFIVE_SPI_CSMODE_MODE_AUTO, spi->regs + SIFIVE_SPI_REG_CSMODE);
138 static void sifive_spi_prep_transfer(struct sifive_spi *spi,
139 struct dm_spi_slave_platdata *slave_plat,
144 /* Modify the SPI protocol mode */
145 cr = readl(spi->regs + SIFIVE_SPI_REG_FMT);
147 /* Bits per word ? */
148 cr &= ~SIFIVE_SPI_FMT_LEN_MASK;
149 cr |= SIFIVE_SPI_FMT_LEN(spi->bits_per_word);
152 cr &= ~SIFIVE_SPI_FMT_ENDIAN;
153 if (slave_plat->mode & SPI_LSB_FIRST)
154 cr |= SIFIVE_SPI_FMT_ENDIAN;
156 /* Number of wires ? */
157 cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
158 switch (spi->fmt_proto) {
159 case SIFIVE_SPI_PROTO_QUAD:
160 cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
162 case SIFIVE_SPI_PROTO_DUAL:
163 cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
166 cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
170 /* SPI direction in/out ? */
171 cr &= ~SIFIVE_SPI_FMT_DIR;
173 cr |= SIFIVE_SPI_FMT_DIR;
175 writel(cr, spi->regs + SIFIVE_SPI_REG_FMT);
178 static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
183 data = readl(spi->regs + SIFIVE_SPI_REG_RXDATA);
184 } while (data & SIFIVE_SPI_RXDATA_EMPTY);
187 *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
190 static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
193 u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK :
194 SIFIVE_SPI_TXDATA_DATA_MASK;
197 data = readl(spi->regs + SIFIVE_SPI_REG_TXDATA);
198 } while (data & SIFIVE_SPI_TXDATA_FULL);
200 writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA);
203 static int sifive_spi_wait(struct sifive_spi *spi, u32 bit)
205 return wait_for_bit_le32(spi->regs + SIFIVE_SPI_REG_IP,
206 bit, true, 100, false);
209 static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
210 const void *dout, void *din, unsigned long flags)
212 struct udevice *bus = dev->parent;
213 struct sifive_spi *spi = dev_get_priv(bus);
214 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
215 const u8 *tx_ptr = dout;
220 if (flags & SPI_XFER_BEGIN) {
221 sifive_spi_prep_device(spi, slave_plat);
223 ret = sifive_spi_set_cs(spi, slave_plat);
228 sifive_spi_prep_transfer(spi, slave_plat, rx_ptr);
230 remaining_len = bitlen / 8;
232 while (remaining_len) {
233 unsigned int n_words = min(remaining_len, spi->fifo_depth);
234 unsigned int tx_words, rx_words;
236 /* Enqueue n_words for transmission */
237 for (tx_words = 0; tx_words < n_words; tx_words++) {
239 sifive_spi_tx(spi, NULL);
241 sifive_spi_tx(spi, tx_ptr++);
245 /* Wait for transmission + reception to complete */
246 writel(n_words - 1, spi->regs + SIFIVE_SPI_REG_RXMARK);
247 ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM);
251 /* Read out all the data from the RX FIFO */
252 for (rx_words = 0; rx_words < n_words; rx_words++)
253 sifive_spi_rx(spi, rx_ptr++);
255 /* Wait for transmission to complete */
256 ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM);
261 remaining_len -= n_words;
264 if (flags & SPI_XFER_END)
265 sifive_spi_clear_cs(spi);
270 static int sifive_spi_exec_op(struct spi_slave *slave,
271 const struct spi_mem_op *op)
273 struct udevice *dev = slave->dev;
274 struct sifive_spi *spi = dev_get_priv(dev->parent);
275 unsigned long flags = SPI_XFER_BEGIN;
276 u8 opcode = op->cmd.opcode;
277 unsigned int pos = 0;
278 const void *tx_buf = NULL;
283 if (!op->addr.nbytes && !op->dummy.nbytes && !op->data.nbytes)
284 flags |= SPI_XFER_END;
286 spi->fmt_proto = op->cmd.buswidth;
288 /* send the opcode */
289 ret = sifive_spi_xfer(dev, 8, (void *)&opcode, NULL, flags);
291 dev_err(dev, "failed to xfer opcode\n");
295 op_len = op->addr.nbytes + op->dummy.nbytes;
298 /* send the addr + dummy */
299 if (op->addr.nbytes) {
301 for (i = 0; i < op->addr.nbytes; i++)
302 op_buf[pos + i] = op->addr.val >>
303 (8 * (op->addr.nbytes - i - 1));
305 pos += op->addr.nbytes;
308 if (op->dummy.nbytes)
309 memset(op_buf + pos, 0xff, op->dummy.nbytes);
311 /* make sure to set end flag, if no data bytes */
312 if (!op->data.nbytes)
313 flags |= SPI_XFER_END;
315 spi->fmt_proto = op->addr.buswidth;
317 ret = sifive_spi_xfer(dev, op_len * 8, op_buf, NULL, flags);
319 dev_err(dev, "failed to xfer addr + dummy\n");
324 /* send/received the data */
325 if (op->data.nbytes) {
326 if (op->data.dir == SPI_MEM_DATA_IN)
327 rx_buf = op->data.buf.in;
329 tx_buf = op->data.buf.out;
331 spi->fmt_proto = op->data.buswidth;
333 ret = sifive_spi_xfer(dev, op->data.nbytes * 8,
334 tx_buf, rx_buf, SPI_XFER_END);
336 dev_err(dev, "failed to xfer data\n");
344 static int sifive_spi_set_speed(struct udevice *bus, uint speed)
346 struct sifive_spi *spi = dev_get_priv(bus);
349 if (speed > spi->freq)
352 /* Cofigure max speed */
353 scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1)
354 & SIFIVE_SPI_SCKDIV_DIV_MASK;
355 writel(scale, spi->regs + SIFIVE_SPI_REG_SCKDIV);
360 static int sifive_spi_set_mode(struct udevice *bus, uint mode)
362 struct sifive_spi *spi = dev_get_priv(bus);
365 /* Switch clock mode bits */
366 cr = readl(spi->regs + SIFIVE_SPI_REG_SCKMODE) &
367 ~SIFIVE_SPI_SCKMODE_MODE_MASK;
369 cr |= SIFIVE_SPI_SCKMODE_PHA;
371 cr |= SIFIVE_SPI_SCKMODE_POL;
373 writel(cr, spi->regs + SIFIVE_SPI_REG_SCKMODE);
378 static int sifive_spi_cs_info(struct udevice *bus, uint cs,
379 struct spi_cs_info *info)
381 struct sifive_spi *spi = dev_get_priv(bus);
383 if (cs >= spi->num_cs)
389 static void sifive_spi_init_hw(struct sifive_spi *spi)
393 /* probe the number of CS lines */
394 spi->cs_inactive = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
395 writel(0xffffffffU, spi->regs + SIFIVE_SPI_REG_CSDEF);
396 cs_bits = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
397 writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
399 printf("Could not auto probe CS lines\n");
403 spi->num_cs = ilog2(cs_bits) + 1;
404 if (spi->num_cs > SIFIVE_SPI_MAX_CS) {
405 printf("Invalid number of spi slaves\n");
409 /* Watermark interrupts are disabled by default */
410 writel(0, spi->regs + SIFIVE_SPI_REG_IE);
412 /* Default watermark FIFO threshold values */
413 writel(1, spi->regs + SIFIVE_SPI_REG_TXMARK);
414 writel(0, spi->regs + SIFIVE_SPI_REG_RXMARK);
416 /* Set CS/SCK Delays and Inactive Time to defaults */
417 writel(SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1),
418 spi->regs + SIFIVE_SPI_REG_DELAY0);
419 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0),
420 spi->regs + SIFIVE_SPI_REG_DELAY1);
422 /* Exit specialized memory-mapped SPI flash mode */
423 writel(0, spi->regs + SIFIVE_SPI_REG_FCTRL);
426 static int sifive_spi_probe(struct udevice *bus)
428 struct sifive_spi *spi = dev_get_priv(bus);
432 spi->regs = (void *)(ulong)dev_remap_addr(bus);
436 spi->fifo_depth = dev_read_u32_default(bus,
438 SIFIVE_SPI_DEFAULT_DEPTH);
440 spi->bits_per_word = dev_read_u32_default(bus,
441 "sifive,max-bits-per-word",
442 SIFIVE_SPI_DEFAULT_BITS);
444 ret = clk_get_by_index(bus, 0, &clkdev);
447 spi->freq = clk_get_rate(&clkdev);
449 /* init the sifive spi hw */
450 sifive_spi_init_hw(spi);
455 static const struct spi_controller_mem_ops sifive_spi_mem_ops = {
456 .exec_op = sifive_spi_exec_op,
459 static const struct dm_spi_ops sifive_spi_ops = {
460 .xfer = sifive_spi_xfer,
461 .set_speed = sifive_spi_set_speed,
462 .set_mode = sifive_spi_set_mode,
463 .cs_info = sifive_spi_cs_info,
464 .mem_ops = &sifive_spi_mem_ops,
467 static const struct udevice_id sifive_spi_ids[] = {
468 { .compatible = "sifive,spi0" },
472 U_BOOT_DRIVER(sifive_spi) = {
473 .name = "sifive_spi",
475 .of_match = sifive_spi_ids,
476 .ops = &sifive_spi_ops,
477 .priv_auto_alloc_size = sizeof(struct sifive_spi),
478 .probe = sifive_spi_probe,