drivers/spi/spi-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   4  * Author: Addy Ke <addy.ke@rock-chips.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/pinctrl/consumer.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/scatterlist.h>
  17
  18 #define DRIVER_NAME "rockchip-spi"
  19
  20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
  21                 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
  22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
  23                 writel_relaxed(readl_relaxed(reg) | (bits), reg)
  24
  25 /* SPI register offsets */
  26 #define ROCKCHIP_SPI_CTRLR0                     0x0000
  27 #define ROCKCHIP_SPI_CTRLR1                     0x0004
  28 #define ROCKCHIP_SPI_SSIENR                     0x0008
  29 #define ROCKCHIP_SPI_SER                        0x000c
  30 #define ROCKCHIP_SPI_BAUDR                      0x0010
  31 #define ROCKCHIP_SPI_TXFTLR                     0x0014
  32 #define ROCKCHIP_SPI_RXFTLR                     0x0018
  33 #define ROCKCHIP_SPI_TXFLR                      0x001c
  34 #define ROCKCHIP_SPI_RXFLR                      0x0020
  35 #define ROCKCHIP_SPI_SR                         0x0024
  36 #define ROCKCHIP_SPI_IPR                        0x0028
  37 #define ROCKCHIP_SPI_IMR                        0x002c
  38 #define ROCKCHIP_SPI_ISR                        0x0030
  39 #define ROCKCHIP_SPI_RISR                       0x0034
  40 #define ROCKCHIP_SPI_ICR                        0x0038
  41 #define ROCKCHIP_SPI_DMACR                      0x003c
  42 #define ROCKCHIP_SPI_DMATDLR            0x0040
  43 #define ROCKCHIP_SPI_DMARDLR            0x0044
  44 #define ROCKCHIP_SPI_TXDR                       0x0400
  45 #define ROCKCHIP_SPI_RXDR                       0x0800
  46
  47 /* Bit fields in CTRLR0 */
  48 #define CR0_DFS_OFFSET                          0
  49 #define CR0_DFS_4BIT                            0x0
  50 #define CR0_DFS_8BIT                            0x1
  51 #define CR0_DFS_16BIT                           0x2
  52
  53 #define CR0_CFS_OFFSET                          2
  54
  55 #define CR0_SCPH_OFFSET                         6
  56
  57 #define CR0_SCPOL_OFFSET                        7
  58
  59 #define CR0_CSM_OFFSET                          8
  60 #define CR0_CSM_KEEP                            0x0
  61 /* ss_n be high for half sclk_out cycles */
  62 #define CR0_CSM_HALF                            0X1
  63 /* ss_n be high for one sclk_out cycle */
  64 #define CR0_CSM_ONE                                     0x2
  65
  66 /* ss_n to sclk_out delay */
  67 #define CR0_SSD_OFFSET                          10
  68 /*
  69  * The period between ss_n active and
  70  * sclk_out active is half sclk_out cycles
  71  */
  72 #define CR0_SSD_HALF                            0x0
  73 /*
  74  * The period between ss_n active and
  75  * sclk_out active is one sclk_out cycle
  76  */
  77 #define CR0_SSD_ONE                                     0x1
  78
  79 #define CR0_EM_OFFSET                           11
  80 #define CR0_EM_LITTLE                           0x0
  81 #define CR0_EM_BIG                                      0x1
  82
  83 #define CR0_FBM_OFFSET                          12
  84 #define CR0_FBM_MSB                                     0x0
  85 #define CR0_FBM_LSB                                     0x1
  86
  87 #define CR0_BHT_OFFSET                          13
  88 #define CR0_BHT_16BIT                           0x0
  89 #define CR0_BHT_8BIT                            0x1
  90
  91 #define CR0_RSD_OFFSET                          14
  92 #define CR0_RSD_MAX                             0x3
  93
  94 #define CR0_FRF_OFFSET                          16
  95 #define CR0_FRF_SPI                                     0x0
  96 #define CR0_FRF_SSP                                     0x1
  97 #define CR0_FRF_MICROWIRE                       0x2
  98
  99 #define CR0_XFM_OFFSET                          18
 100 #define CR0_XFM_MASK                            (0x03 << SPI_XFM_OFFSET)
 101 #define CR0_XFM_TR                                      0x0
 102 #define CR0_XFM_TO                                      0x1
 103 #define CR0_XFM_RO                                      0x2
 104
 105 #define CR0_OPM_OFFSET                          20
 106 #define CR0_OPM_MASTER                          0x0
 107 #define CR0_OPM_SLAVE                           0x1
 108
 109 #define CR0_MTM_OFFSET                          0x21
 110
 111 /* Bit fields in SER, 2bit */
 112 #define SER_MASK                                        0x3
 113
 114 /* Bit fields in BAUDR */
 115 #define BAUDR_SCKDV_MIN                         2
 116 #define BAUDR_SCKDV_MAX                         65534
 117
 118 /* Bit fields in SR, 5bit */
 119 #define SR_MASK                                         0x1f
 120 #define SR_BUSY                                         (1 << 0)
 121 #define SR_TF_FULL                                      (1 << 1)
 122 #define SR_TF_EMPTY                                     (1 << 2)
 123 #define SR_RF_EMPTY                                     (1 << 3)
 124 #define SR_RF_FULL                                      (1 << 4)
 125
 126 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
 127 #define INT_MASK                                        0x1f
 128 #define INT_TF_EMPTY                            (1 << 0)
 129 #define INT_TF_OVERFLOW                         (1 << 1)
 130 #define INT_RF_UNDERFLOW                        (1 << 2)
 131 #define INT_RF_OVERFLOW                         (1 << 3)
 132 #define INT_RF_FULL                                     (1 << 4)
 133
 134 /* Bit fields in ICR, 4bit */
 135 #define ICR_MASK                                        0x0f
 136 #define ICR_ALL                                         (1 << 0)
 137 #define ICR_RF_UNDERFLOW                        (1 << 1)
 138 #define ICR_RF_OVERFLOW                         (1 << 2)
 139 #define ICR_TF_OVERFLOW                         (1 << 3)
 140
 141 /* Bit fields in DMACR */
 142 #define RF_DMA_EN                                       (1 << 0)
 143 #define TF_DMA_EN                                       (1 << 1)
 144
 145 /* Driver state flags */
 146 #define RXDMA                                   (1 << 0)
 147 #define TXDMA                                   (1 << 1)
 148
 149 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 150 #define MAX_SCLK_OUT                            50000000U
 151
 152 /*
 153  * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
 154  * the controller seems to hang when given 0x10000, so stick with this for now.
 155  */
 156 #define ROCKCHIP_SPI_MAX_TRANLEN                0xffff
 157
 158 #define ROCKCHIP_SPI_MAX_CS_NUM                 2
 159
 160 struct rockchip_spi {
 161         struct device *dev;
 162
 163         struct clk *spiclk;
 164         struct clk *apb_pclk;
 165
 166         void __iomem *regs;
 167         dma_addr_t dma_addr_rx;
 168         dma_addr_t dma_addr_tx;
 169
 170         const void *tx;
 171         void *rx;
 172         unsigned int tx_left;
 173         unsigned int rx_left;
 174
 175         atomic_t state;
 176
 177         /*depth of the FIFO buffer */
 178         u32 fifo_len;
 179         /* frequency of spiclk */
 180         u32 freq;
 181
 182         u8 n_bytes;
 183         u8 rsd;
 184
 185         bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
 186 };
 187
 188 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
 189 {
 190         writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
 191 }
 192
 193 static inline void wait_for_idle(struct rockchip_spi *rs)
 194 {
 195         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 196
 197         do {
 198                 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
 199                         return;
 200         } while (!time_after(jiffies, timeout));
 201
 202         dev_warn(rs->dev, "spi controller is in busy state!\n");
 203 }
 204
 205 static u32 get_fifo_len(struct rockchip_spi *rs)
 206 {
 207         u32 fifo;
 208
 209         for (fifo = 2; fifo < 32; fifo++) {
 210                 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
 211                 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
 212                         break;
 213         }
 214
 215         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
 216
 217         return (fifo == 31) ? 0 : fifo;
 218 }
 219
 220 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
 221 {
 222         struct spi_master *master = spi->master;
 223         struct rockchip_spi *rs = spi_master_get_devdata(master);
 224         bool cs_asserted = !enable;
 225
 226         /* Return immediately for no-op */
 227         if (cs_asserted == rs->cs_asserted[spi->chip_select])
 228                 return;
 229
 230         if (cs_asserted) {
 231                 /* Keep things powered as long as CS is asserted */
 232                 pm_runtime_get_sync(rs->dev);
 233
 234                 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER,
 235                                       BIT(spi->chip_select));
 236         } else {
 237                 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER,
 238                                       BIT(spi->chip_select));
 239
 240                 /* Drop reference from when we first asserted CS */
 241                 pm_runtime_put(rs->dev);
 242         }
 243
 244         rs->cs_asserted[spi->chip_select] = cs_asserted;
 245 }
 246
 247 static void rockchip_spi_handle_err(struct spi_master *master,
 248                                     struct spi_message *msg)
 249 {
 250         struct rockchip_spi *rs = spi_master_get_devdata(master);
 251
 252         /* stop running spi transfer
 253          * this also flushes both rx and tx fifos
 254          */
 255         spi_enable_chip(rs, false);
 256
 257         /* make sure all interrupts are masked */
 258         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 259
 260         if (atomic_read(&rs->state) & TXDMA)
 261                 dmaengine_terminate_async(master->dma_tx);
 262
 263         if (atomic_read(&rs->state) & RXDMA)
 264                 dmaengine_terminate_async(master->dma_rx);
 265 }
 266
 267 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
 268 {
 269         u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
 270         u32 words = min(rs->tx_left, tx_free);
 271
 272         rs->tx_left -= words;
 273         for (; words; words--) {
 274                 u32 txw;
 275
 276                 if (rs->n_bytes == 1)
 277                         txw = *(u8 *)rs->tx;
 278                 else
 279                         txw = *(u16 *)rs->tx;
 280
 281                 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
 282                 rs->tx += rs->n_bytes;
 283         }
 284 }
 285
 286 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
 287 {
 288         u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 289         u32 rx_left = rs->rx_left - words;
 290
 291         /* the hardware doesn't allow us to change fifo threshold
 292          * level while spi is enabled, so instead make sure to leave
 293          * enough words in the rx fifo to get the last interrupt
 294          * exactly when all words have been received
 295          */
 296         if (rx_left) {
 297                 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
 298
 299                 if (rx_left < ftl) {
 300                         rx_left = ftl;
 301                         words = rs->rx_left - rx_left;
 302                 }
 303         }
 304
 305         rs->rx_left = rx_left;
 306         for (; words; words--) {
 307                 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 308
 309                 if (!rs->rx)
 310                         continue;
 311
 312                 if (rs->n_bytes == 1)
 313                         *(u8 *)rs->rx = (u8)rxw;
 314                 else
 315                         *(u16 *)rs->rx = (u16)rxw;
 316                 rs->rx += rs->n_bytes;
 317         }
 318 }
 319
 320 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
 321 {
 322         struct spi_master *master = dev_id;
 323         struct rockchip_spi *rs = spi_master_get_devdata(master);
 324
 325         if (rs->tx_left)
 326                 rockchip_spi_pio_writer(rs);
 327
 328         rockchip_spi_pio_reader(rs);
 329         if (!rs->rx_left) {
 330                 spi_enable_chip(rs, false);
 331                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 332                 spi_finalize_current_transfer(master);
 333         }
 334
 335         return IRQ_HANDLED;
 336 }
 337
 338 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
 339                 struct spi_transfer *xfer)
 340 {
 341         rs->tx = xfer->tx_buf;
 342         rs->rx = xfer->rx_buf;
 343         rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
 344         rs->rx_left = xfer->len / rs->n_bytes;
 345
 346         writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
 347         spi_enable_chip(rs, true);
 348
 349         if (rs->tx_left)
 350                 rockchip_spi_pio_writer(rs);
 351
 352         /* 1 means the transfer is in progress */
 353         return 1;
 354 }
 355
 356 static void rockchip_spi_dma_rxcb(void *data)
 357 {
 358         struct spi_master *master = data;
 359         struct rockchip_spi *rs = spi_master_get_devdata(master);
 360         int state = atomic_fetch_andnot(RXDMA, &rs->state);
 361
 362         if (state & TXDMA)
 363                 return;
 364
 365         spi_enable_chip(rs, false);
 366         spi_finalize_current_transfer(master);
 367 }
 368
 369 static void rockchip_spi_dma_txcb(void *data)
 370 {
 371         struct spi_master *master = data;
 372         struct rockchip_spi *rs = spi_master_get_devdata(master);
 373         int state = atomic_fetch_andnot(TXDMA, &rs->state);
 374
 375         if (state & RXDMA)
 376                 return;
 377
 378         /* Wait until the FIFO data completely. */
 379         wait_for_idle(rs);
 380
 381         spi_enable_chip(rs, false);
 382         spi_finalize_current_transfer(master);
 383 }
 384
 385 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
 386                 struct spi_master *master, struct spi_transfer *xfer)
 387 {
 388         struct dma_async_tx_descriptor *rxdesc, *txdesc;
 389
 390         atomic_set(&rs->state, 0);
 391
 392         rxdesc = NULL;
 393         if (xfer->rx_buf) {
 394                 struct dma_slave_config rxconf = {
 395                         .direction = DMA_DEV_TO_MEM,
 396                         .src_addr = rs->dma_addr_rx,
 397                         .src_addr_width = rs->n_bytes,
 398                         .src_maxburst = 1,
 399                 };
 400
 401                 dmaengine_slave_config(master->dma_rx, &rxconf);
 402
 403                 rxdesc = dmaengine_prep_slave_sg(
 404                                 master->dma_rx,
 405                                 xfer->rx_sg.sgl, xfer->rx_sg.nents,
 406                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
 407                 if (!rxdesc)
 408                         return -EINVAL;
 409
 410                 rxdesc->callback = rockchip_spi_dma_rxcb;
 411                 rxdesc->callback_param = master;
 412         }
 413
 414         txdesc = NULL;
 415         if (xfer->tx_buf) {
 416                 struct dma_slave_config txconf = {
 417                         .direction = DMA_MEM_TO_DEV,
 418                         .dst_addr = rs->dma_addr_tx,
 419                         .dst_addr_width = rs->n_bytes,
 420                         .dst_maxburst = rs->fifo_len / 4,
 421                 };
 422
 423                 dmaengine_slave_config(master->dma_tx, &txconf);
 424
 425                 txdesc = dmaengine_prep_slave_sg(
 426                                 master->dma_tx,
 427                                 xfer->tx_sg.sgl, xfer->tx_sg.nents,
 428                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 429                 if (!txdesc) {
 430                         if (rxdesc)
 431                                 dmaengine_terminate_sync(master->dma_rx);
 432                         return -EINVAL;
 433                 }
 434
 435                 txdesc->callback = rockchip_spi_dma_txcb;
 436                 txdesc->callback_param = master;
 437         }
 438
 439         /* rx must be started before tx due to spi instinct */
 440         if (rxdesc) {
 441                 atomic_or(RXDMA, &rs->state);
 442                 dmaengine_submit(rxdesc);
 443                 dma_async_issue_pending(master->dma_rx);
 444         }
 445
 446         spi_enable_chip(rs, true);
 447
 448         if (txdesc) {
 449                 atomic_or(TXDMA, &rs->state);
 450                 dmaengine_submit(txdesc);
 451                 dma_async_issue_pending(master->dma_tx);
 452         }
 453
 454         /* 1 means the transfer is in progress */
 455         return 1;
 456 }
 457
 458 static void rockchip_spi_config(struct rockchip_spi *rs,
 459                 struct spi_device *spi, struct spi_transfer *xfer,
 460                 bool use_dma)
 461 {
 462         u32 cr0 = CR0_FRF_SPI  << CR0_FRF_OFFSET
 463                 | CR0_BHT_8BIT << CR0_BHT_OFFSET
 464                 | CR0_SSD_ONE  << CR0_SSD_OFFSET
 465                 | CR0_EM_BIG   << CR0_EM_OFFSET;
 466         u32 cr1;
 467         u32 dmacr = 0;
 468
 469         cr0 |= rs->rsd << CR0_RSD_OFFSET;
 470         cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
 471         if (spi->mode & SPI_LSB_FIRST)
 472                 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
 473
 474         if (xfer->rx_buf && xfer->tx_buf)
 475                 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
 476         else if (xfer->rx_buf)
 477                 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
 478         else if (use_dma)
 479                 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
 480
 481         switch (xfer->bits_per_word) {
 482         case 4:
 483                 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
 484                 cr1 = xfer->len - 1;
 485                 break;
 486         case 8:
 487                 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
 488                 cr1 = xfer->len - 1;
 489                 break;
 490         case 16:
 491                 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
 492                 cr1 = xfer->len / 2 - 1;
 493                 break;
 494         default:
 495                 /* we only whitelist 4, 8 and 16 bit words in
 496                  * master->bits_per_word_mask, so this shouldn't
 497                  * happen
 498                  */
 499                 unreachable();
 500         }
 501
 502         if (use_dma) {
 503                 if (xfer->tx_buf)
 504                         dmacr |= TF_DMA_EN;
 505                 if (xfer->rx_buf)
 506                         dmacr |= RF_DMA_EN;
 507         }
 508
 509         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 510         writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 511
 512         /* unfortunately setting the fifo threshold level to generate an
 513          * interrupt exactly when the fifo is full doesn't seem to work,
 514          * so we need the strict inequality here
 515          */
 516         if (xfer->len < rs->fifo_len)
 517                 writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 518         else
 519                 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 520
 521         writel_relaxed(rs->fifo_len / 2, rs->regs + ROCKCHIP_SPI_DMATDLR);
 522         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
 523         writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
 524
 525         /* the hardware only supports an even clock divisor, so
 526          * round divisor = spiclk / speed up to nearest even number
 527          * so that the resulting speed is <= the requested speed
 528          */
 529         writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
 530                         rs->regs + ROCKCHIP_SPI_BAUDR);
 531 }
 532
 533 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
 534 {
 535         return ROCKCHIP_SPI_MAX_TRANLEN;
 536 }
 537
 538 static int rockchip_spi_transfer_one(
 539                 struct spi_master *master,
 540                 struct spi_device *spi,
 541                 struct spi_transfer *xfer)
 542 {
 543         struct rockchip_spi *rs = spi_master_get_devdata(master);
 544         bool use_dma;
 545
 546         WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
 547                 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
 548
 549         if (!xfer->tx_buf && !xfer->rx_buf) {
 550                 dev_err(rs->dev, "No buffer for transfer\n");
 551                 return -EINVAL;
 552         }
 553
 554         if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
 555                 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
 556                 return -EINVAL;
 557         }
 558
 559         rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
 560
 561         use_dma = master->can_dma ? master->can_dma(master, spi, xfer) : false;
 562
 563         rockchip_spi_config(rs, spi, xfer, use_dma);
 564
 565         if (use_dma)
 566                 return rockchip_spi_prepare_dma(rs, master, xfer);
 567
 568         return rockchip_spi_prepare_irq(rs, xfer);
 569 }
 570
 571 static bool rockchip_spi_can_dma(struct spi_master *master,
 572                                  struct spi_device *spi,
 573                                  struct spi_transfer *xfer)
 574 {
 575         struct rockchip_spi *rs = spi_master_get_devdata(master);
 576         unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
 577
 578         /* if the numbor of spi words to transfer is less than the fifo
 579          * length we can just fill the fifo and wait for a single irq,
 580          * so don't bother setting up dma
 581          */
 582         return xfer->len / bytes_per_word >= rs->fifo_len;
 583 }
 584
 585 static int rockchip_spi_probe(struct platform_device *pdev)
 586 {
 587         int ret;
 588         struct rockchip_spi *rs;
 589         struct spi_master *master;
 590         struct resource *mem;
 591         u32 rsd_nsecs;
 592
 593         master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
 594         if (!master)
 595                 return -ENOMEM;
 596
 597         platform_set_drvdata(pdev, master);
 598
 599         rs = spi_master_get_devdata(master);
 600
 601         /* Get basic io resource and map it */
 602         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 603         rs->regs = devm_ioremap_resource(&pdev->dev, mem);
 604         if (IS_ERR(rs->regs)) {
 605                 ret =  PTR_ERR(rs->regs);
 606                 goto err_put_master;
 607         }
 608
 609         rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 610         if (IS_ERR(rs->apb_pclk)) {
 611                 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
 612                 ret = PTR_ERR(rs->apb_pclk);
 613                 goto err_put_master;
 614         }
 615
 616         rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
 617         if (IS_ERR(rs->spiclk)) {
 618                 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
 619                 ret = PTR_ERR(rs->spiclk);
 620                 goto err_put_master;
 621         }
 622
 623         ret = clk_prepare_enable(rs->apb_pclk);
 624         if (ret < 0) {
 625                 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
 626                 goto err_put_master;
 627         }
 628
 629         ret = clk_prepare_enable(rs->spiclk);
 630         if (ret < 0) {
 631                 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
 632                 goto err_disable_apbclk;
 633         }
 634
 635         spi_enable_chip(rs, false);
 636
 637         ret = platform_get_irq(pdev, 0);
 638         if (ret < 0)
 639                 goto err_disable_spiclk;
 640
 641         ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
 642                         IRQF_ONESHOT, dev_name(&pdev->dev), master);
 643         if (ret)
 644                 goto err_disable_spiclk;
 645
 646         rs->dev = &pdev->dev;
 647         rs->freq = clk_get_rate(rs->spiclk);
 648
 649         if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
 650                                   &rsd_nsecs)) {
 651                 /* rx sample delay is expressed in parent clock cycles (max 3) */
 652                 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
 653                                 1000000000 >> 8);
 654                 if (!rsd) {
 655                         dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
 656                                         rs->freq, rsd_nsecs);
 657                 } else if (rsd > CR0_RSD_MAX) {
 658                         rsd = CR0_RSD_MAX;
 659                         dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
 660                                         rs->freq, rsd_nsecs,
 661                                         CR0_RSD_MAX * 1000000000U / rs->freq);
 662                 }
 663                 rs->rsd = rsd;
 664         }
 665
 666         rs->fifo_len = get_fifo_len(rs);
 667         if (!rs->fifo_len) {
 668                 dev_err(&pdev->dev, "Failed to get fifo length\n");
 669                 ret = -EINVAL;
 670                 goto err_disable_spiclk;
 671         }
 672
 673         pm_runtime_set_active(&pdev->dev);
 674         pm_runtime_enable(&pdev->dev);
 675
 676         master->auto_runtime_pm = true;
 677         master->bus_num = pdev->id;
 678         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
 679         master->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM;
 680         master->dev.of_node = pdev->dev.of_node;
 681         master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
 682         master->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
 683         master->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
 684
 685         master->set_cs = rockchip_spi_set_cs;
 686         master->transfer_one = rockchip_spi_transfer_one;
 687         master->max_transfer_size = rockchip_spi_max_transfer_size;
 688         master->handle_err = rockchip_spi_handle_err;
 689         master->flags = SPI_MASTER_GPIO_SS;
 690
 691         master->dma_tx = dma_request_chan(rs->dev, "tx");
 692         if (IS_ERR(master->dma_tx)) {
 693                 /* Check tx to see if we need defer probing driver */
 694                 if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) {
 695                         ret = -EPROBE_DEFER;
 696                         goto err_disable_pm_runtime;
 697                 }
 698                 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
 699                 master->dma_tx = NULL;
 700         }
 701
 702         master->dma_rx = dma_request_chan(rs->dev, "rx");
 703         if (IS_ERR(master->dma_rx)) {
 704                 if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) {
 705                         ret = -EPROBE_DEFER;
 706                         goto err_free_dma_tx;
 707                 }
 708                 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
 709                 master->dma_rx = NULL;
 710         }
 711
 712         if (master->dma_tx && master->dma_rx) {
 713                 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
 714                 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
 715                 master->can_dma = rockchip_spi_can_dma;
 716         }
 717
 718         ret = devm_spi_register_master(&pdev->dev, master);
 719         if (ret < 0) {
 720                 dev_err(&pdev->dev, "Failed to register master\n");
 721                 goto err_free_dma_rx;
 722         }
 723
 724         return 0;
 725
 726 err_free_dma_rx:
 727         if (master->dma_rx)
 728                 dma_release_channel(master->dma_rx);
 729 err_free_dma_tx:
 730         if (master->dma_tx)
 731                 dma_release_channel(master->dma_tx);
 732 err_disable_pm_runtime:
 733         pm_runtime_disable(&pdev->dev);
 734 err_disable_spiclk:
 735         clk_disable_unprepare(rs->spiclk);
 736 err_disable_apbclk:
 737         clk_disable_unprepare(rs->apb_pclk);
 738 err_put_master:
 739         spi_master_put(master);
 740
 741         return ret;
 742 }
 743
 744 static int rockchip_spi_remove(struct platform_device *pdev)
 745 {
 746         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
 747         struct rockchip_spi *rs = spi_master_get_devdata(master);
 748
 749         pm_runtime_get_sync(&pdev->dev);
 750
 751         clk_disable_unprepare(rs->spiclk);
 752         clk_disable_unprepare(rs->apb_pclk);
 753
 754         pm_runtime_put_noidle(&pdev->dev);
 755         pm_runtime_disable(&pdev->dev);
 756         pm_runtime_set_suspended(&pdev->dev);
 757
 758         if (master->dma_tx)
 759                 dma_release_channel(master->dma_tx);
 760         if (master->dma_rx)
 761                 dma_release_channel(master->dma_rx);
 762
 763         spi_master_put(master);
 764
 765         return 0;
 766 }
 767
 768 #ifdef CONFIG_PM_SLEEP
 769 static int rockchip_spi_suspend(struct device *dev)
 770 {
 771         int ret;
 772         struct spi_master *master = dev_get_drvdata(dev);
 773
 774         ret = spi_master_suspend(master);
 775         if (ret < 0)
 776                 return ret;
 777
 778         ret = pm_runtime_force_suspend(dev);
 779         if (ret < 0)
 780                 return ret;
 781
 782         pinctrl_pm_select_sleep_state(dev);
 783
 784         return 0;
 785 }
 786
 787 static int rockchip_spi_resume(struct device *dev)
 788 {
 789         int ret;
 790         struct spi_master *master = dev_get_drvdata(dev);
 791         struct rockchip_spi *rs = spi_master_get_devdata(master);
 792
 793         pinctrl_pm_select_default_state(dev);
 794
 795         ret = pm_runtime_force_resume(dev);
 796         if (ret < 0)
 797                 return ret;
 798
 799         ret = spi_master_resume(master);
 800         if (ret < 0) {
 801                 clk_disable_unprepare(rs->spiclk);
 802                 clk_disable_unprepare(rs->apb_pclk);
 803         }
 804
 805         return 0;
 806 }
 807 #endif /* CONFIG_PM_SLEEP */
 808
 809 #ifdef CONFIG_PM
 810 static int rockchip_spi_runtime_suspend(struct device *dev)
 811 {
 812         struct spi_master *master = dev_get_drvdata(dev);
 813         struct rockchip_spi *rs = spi_master_get_devdata(master);
 814
 815         clk_disable_unprepare(rs->spiclk);
 816         clk_disable_unprepare(rs->apb_pclk);
 817
 818         return 0;
 819 }
 820
 821 static int rockchip_spi_runtime_resume(struct device *dev)
 822 {
 823         int ret;
 824         struct spi_master *master = dev_get_drvdata(dev);
 825         struct rockchip_spi *rs = spi_master_get_devdata(master);
 826
 827         ret = clk_prepare_enable(rs->apb_pclk);
 828         if (ret < 0)
 829                 return ret;
 830
 831         ret = clk_prepare_enable(rs->spiclk);
 832         if (ret < 0)
 833                 clk_disable_unprepare(rs->apb_pclk);
 834
 835         return 0;
 836 }
 837 #endif /* CONFIG_PM */
 838
 839 static const struct dev_pm_ops rockchip_spi_pm = {
 840         SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
 841         SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
 842                            rockchip_spi_runtime_resume, NULL)
 843 };
 844
 845 static const struct of_device_id rockchip_spi_dt_match[] = {
 846         { .compatible = "rockchip,rv1108-spi", },
 847         { .compatible = "rockchip,rk3036-spi", },
 848         { .compatible = "rockchip,rk3066-spi", },
 849         { .compatible = "rockchip,rk3188-spi", },
 850         { .compatible = "rockchip,rk3228-spi", },
 851         { .compatible = "rockchip,rk3288-spi", },
 852         { .compatible = "rockchip,rk3368-spi", },
 853         { .compatible = "rockchip,rk3399-spi", },
 854         { },
 855 };
 856 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
 857
 858 static struct platform_driver rockchip_spi_driver = {
 859         .driver = {
 860                 .name   = DRIVER_NAME,
 861                 .pm = &rockchip_spi_pm,
 862                 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
 863         },
 864         .probe = rockchip_spi_probe,
 865         .remove = rockchip_spi_remove,
 866 };
 867
 868 module_platform_driver(rockchip_spi_driver);
 869
 870 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
 871 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
 872 MODULE_LICENSE("GPL v2");