1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Broadcom BCM2835 SPI Controllers
5 * Copyright (C) 2012 Chris Boot
6 * Copyright (C) 2013 Stephen Warren
7 * Copyright (C) 2015 Martin Sperl
9 * This driver is inspired by:
10 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
11 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
14 #include <linux/clk.h>
15 #include <linux/completion.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/err.h>
21 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
26 #include <linux/of_address.h>
27 #include <linux/of_device.h>
28 #include <linux/of_gpio.h>
29 #include <linux/of_irq.h>
30 #include <linux/spi/spi.h>
32 /* SPI register offsets */
33 #define BCM2835_SPI_CS 0x00
34 #define BCM2835_SPI_FIFO 0x04
35 #define BCM2835_SPI_CLK 0x08
36 #define BCM2835_SPI_DLEN 0x0c
37 #define BCM2835_SPI_LTOH 0x10
38 #define BCM2835_SPI_DC 0x14
41 #define BCM2835_SPI_CS_LEN_LONG 0x02000000
42 #define BCM2835_SPI_CS_DMA_LEN 0x01000000
43 #define BCM2835_SPI_CS_CSPOL2 0x00800000
44 #define BCM2835_SPI_CS_CSPOL1 0x00400000
45 #define BCM2835_SPI_CS_CSPOL0 0x00200000
46 #define BCM2835_SPI_CS_RXF 0x00100000
47 #define BCM2835_SPI_CS_RXR 0x00080000
48 #define BCM2835_SPI_CS_TXD 0x00040000
49 #define BCM2835_SPI_CS_RXD 0x00020000
50 #define BCM2835_SPI_CS_DONE 0x00010000
51 #define BCM2835_SPI_CS_LEN 0x00002000
52 #define BCM2835_SPI_CS_REN 0x00001000
53 #define BCM2835_SPI_CS_ADCS 0x00000800
54 #define BCM2835_SPI_CS_INTR 0x00000400
55 #define BCM2835_SPI_CS_INTD 0x00000200
56 #define BCM2835_SPI_CS_DMAEN 0x00000100
57 #define BCM2835_SPI_CS_TA 0x00000080
58 #define BCM2835_SPI_CS_CSPOL 0x00000040
59 #define BCM2835_SPI_CS_CLEAR_RX 0x00000020
60 #define BCM2835_SPI_CS_CLEAR_TX 0x00000010
61 #define BCM2835_SPI_CS_CPOL 0x00000008
62 #define BCM2835_SPI_CS_CPHA 0x00000004
63 #define BCM2835_SPI_CS_CS_10 0x00000002
64 #define BCM2835_SPI_CS_CS_01 0x00000001
66 #define BCM2835_SPI_FIFO_SIZE 64
67 #define BCM2835_SPI_FIFO_SIZE_3_4 48
68 #define BCM2835_SPI_DMA_MIN_LENGTH 96
69 #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
70 | SPI_NO_CS | SPI_3WIRE)
72 #define DRV_NAME "spi-bcm2835"
74 /* define polling limits */
75 unsigned int polling_limit_us = 30;
76 module_param(polling_limit_us, uint, 0664);
77 MODULE_PARM_DESC(polling_limit_us,
78 "time in us to run a transfer in polling mode\n");
81 * struct bcm2835_spi - BCM2835 SPI controller
82 * @regs: base address of register map
83 * @clk: core clock, divided to calculate serial clock
84 * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full
85 * @tfr: SPI transfer currently processed
86 * @tx_buf: pointer whence next transmitted byte is read
87 * @rx_buf: pointer where next received byte is written
88 * @tx_len: remaining bytes to transmit
89 * @rx_len: remaining bytes to receive
90 * @tx_prologue: bytes transmitted without DMA if first TX sglist entry's
91 * length is not a multiple of 4 (to overcome hardware limitation)
92 * @rx_prologue: bytes received without DMA if first RX sglist entry's
93 * length is not a multiple of 4 (to overcome hardware limitation)
94 * @tx_spillover: whether @tx_prologue spills over to second TX sglist entry
95 * @dma_pending: whether a DMA transfer is in progress
96 * @debugfs_dir: the debugfs directory - neede to remove debugfs when
97 * unloading the module
98 * @count_transfer_polling: count of how often polling mode is used
99 * @count_transfer_irq: count of how often interrupt mode is used
100 * @count_transfer_irq_after_polling: count of how often we fall back to
101 * interrupt mode after starting in polling mode.
102 * These are counted as well in @count_transfer_polling and
103 * @count_transfer_irq
104 * @count_transfer_dma: count how often dma mode is used
110 struct spi_transfer *tfr;
117 unsigned int tx_spillover;
118 unsigned int dma_pending;
120 struct dentry *debugfs_dir;
121 u64 count_transfer_polling;
122 u64 count_transfer_irq;
123 u64 count_transfer_irq_after_polling;
124 u64 count_transfer_dma;
127 #if defined(CONFIG_DEBUG_FS)
128 static void bcm2835_debugfs_create(struct bcm2835_spi *bs,
135 snprintf(name, sizeof(name), "spi-bcm2835-%s", dname);
137 /* the base directory */
138 dir = debugfs_create_dir(name, NULL);
139 bs->debugfs_dir = dir;
142 debugfs_create_u64("count_transfer_polling", 0444, dir,
143 &bs->count_transfer_polling);
144 debugfs_create_u64("count_transfer_irq", 0444, dir,
145 &bs->count_transfer_irq);
146 debugfs_create_u64("count_transfer_irq_after_polling", 0444, dir,
147 &bs->count_transfer_irq_after_polling);
148 debugfs_create_u64("count_transfer_dma", 0444, dir,
149 &bs->count_transfer_dma);
152 static void bcm2835_debugfs_remove(struct bcm2835_spi *bs)
154 debugfs_remove_recursive(bs->debugfs_dir);
155 bs->debugfs_dir = NULL;
158 static void bcm2835_debugfs_create(struct bcm2835_spi *bs,
163 static void bcm2835_debugfs_remove(struct bcm2835_spi *bs)
166 #endif /* CONFIG_DEBUG_FS */
168 static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
170 return readl(bs->regs + reg);
173 static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
175 writel(val, bs->regs + reg);
178 static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
182 while ((bs->rx_len) &&
183 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
184 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
186 *bs->rx_buf++ = byte;
191 static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
195 while ((bs->tx_len) &&
196 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
197 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
198 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
204 * bcm2835_rd_fifo_count() - blindly read exactly @count bytes from RX FIFO
205 * @bs: BCM2835 SPI controller
206 * @count: bytes to read from RX FIFO
208 * The caller must ensure that @bs->rx_len is greater than or equal to @count,
209 * that the RX FIFO contains at least @count bytes and that the DMA Enable flag
210 * in the CS register is set (such that a read from the FIFO register receives
211 * 32-bit instead of just 8-bit). Moreover @bs->rx_buf must not be %NULL.
213 static inline void bcm2835_rd_fifo_count(struct bcm2835_spi *bs, int count)
221 val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
223 memcpy(bs->rx_buf, &val, len);
230 * bcm2835_wr_fifo_count() - blindly write exactly @count bytes to TX FIFO
231 * @bs: BCM2835 SPI controller
232 * @count: bytes to write to TX FIFO
234 * The caller must ensure that @bs->tx_len is greater than or equal to @count,
235 * that the TX FIFO can accommodate @count bytes and that the DMA Enable flag
236 * in the CS register is set (such that a write to the FIFO register transmits
237 * 32-bit instead of just 8-bit).
239 static inline void bcm2835_wr_fifo_count(struct bcm2835_spi *bs, int count)
249 memcpy(&val, bs->tx_buf, len);
254 bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
260 * bcm2835_wait_tx_fifo_empty() - busy-wait for TX FIFO to empty
261 * @bs: BCM2835 SPI controller
263 * The caller must ensure that the RX FIFO can accommodate as many bytes
264 * as have been written to the TX FIFO: Transmission is halted once the
265 * RX FIFO is full, causing this function to spin forever.
267 static inline void bcm2835_wait_tx_fifo_empty(struct bcm2835_spi *bs)
269 while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE))
274 * bcm2835_rd_fifo_blind() - blindly read up to @count bytes from RX FIFO
275 * @bs: BCM2835 SPI controller
276 * @count: bytes available for reading in RX FIFO
278 static inline void bcm2835_rd_fifo_blind(struct bcm2835_spi *bs, int count)
282 count = min(count, bs->rx_len);
286 val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
294 * bcm2835_wr_fifo_blind() - blindly write up to @count bytes to TX FIFO
295 * @bs: BCM2835 SPI controller
296 * @count: bytes available for writing in TX FIFO
298 static inline void bcm2835_wr_fifo_blind(struct bcm2835_spi *bs, int count)
302 count = min(count, bs->tx_len);
306 val = bs->tx_buf ? *bs->tx_buf++ : 0;
307 bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
312 static void bcm2835_spi_reset_hw(struct spi_controller *ctlr)
314 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
315 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
317 /* Disable SPI interrupts and transfer */
318 cs &= ~(BCM2835_SPI_CS_INTR |
319 BCM2835_SPI_CS_INTD |
320 BCM2835_SPI_CS_DMAEN |
323 * Transmission sometimes breaks unless the DONE bit is written at the
324 * end of every transfer. The spec says it's a RO bit. Either the
325 * spec is wrong and the bit is actually of type RW1C, or it's a
328 cs |= BCM2835_SPI_CS_DONE;
329 /* and reset RX/TX FIFOS */
330 cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
332 /* and reset the SPI_HW */
333 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
334 /* as well as DLEN */
335 bcm2835_wr(bs, BCM2835_SPI_DLEN, 0);
338 static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
340 struct spi_controller *ctlr = dev_id;
341 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
342 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
345 * An interrupt is signaled either if DONE is set (TX FIFO empty)
346 * or if RXR is set (RX FIFO >= ¾ full).
348 if (cs & BCM2835_SPI_CS_RXF)
349 bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
350 else if (cs & BCM2835_SPI_CS_RXR)
351 bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE_3_4);
353 if (bs->tx_len && cs & BCM2835_SPI_CS_DONE)
354 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
356 /* Read as many bytes as possible from FIFO */
358 /* Write as many bytes as possible to FIFO */
362 /* Transfer complete - reset SPI HW */
363 bcm2835_spi_reset_hw(ctlr);
364 /* wake up the framework */
365 complete(&ctlr->xfer_completion);
371 static int bcm2835_spi_transfer_one_irq(struct spi_controller *ctlr,
372 struct spi_device *spi,
373 struct spi_transfer *tfr,
374 u32 cs, bool fifo_empty)
376 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
378 /* update usage statistics */
379 bs->count_transfer_irq++;
382 * Enable HW block, but with interrupts still disabled.
383 * Otherwise the empty TX FIFO would immediately trigger an interrupt.
385 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
387 /* fill TX FIFO as much as possible */
389 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
392 /* enable interrupts */
393 cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
394 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
396 /* signal that we need to wait for completion */
401 * bcm2835_spi_transfer_prologue() - transfer first few bytes without DMA
402 * @ctlr: SPI master controller
404 * @bs: BCM2835 SPI controller
407 * A limitation in DMA mode is that the FIFO must be accessed in 4 byte chunks.
408 * Only the final write access is permitted to transmit less than 4 bytes, the
409 * SPI controller deduces its intended size from the DLEN register.
411 * If a TX or RX sglist contains multiple entries, one per page, and the first
412 * entry starts in the middle of a page, that first entry's length may not be
413 * a multiple of 4. Subsequent entries are fine because they span an entire
414 * page, hence do have a length that's a multiple of 4.
416 * This cannot happen with kmalloc'ed buffers (which is what most clients use)
417 * because they are contiguous in physical memory and therefore not split on
418 * page boundaries by spi_map_buf(). But it *can* happen with vmalloc'ed
421 * The DMA engine is incapable of combining sglist entries into a continuous
422 * stream of 4 byte chunks, it treats every entry separately: A TX entry is
423 * rounded up a to a multiple of 4 bytes by transmitting surplus bytes, an RX
424 * entry is rounded up by throwing away received bytes.
426 * Overcome this limitation by transferring the first few bytes without DMA:
427 * E.g. if the first TX sglist entry's length is 23 and the first RX's is 42,
428 * write 3 bytes to the TX FIFO but read only 2 bytes from the RX FIFO.
429 * The residue of 1 byte in the RX FIFO is picked up by DMA. Together with
430 * the rest of the first RX sglist entry it makes up a multiple of 4 bytes.
432 * Should the RX prologue be larger, say, 3 vis-à-vis a TX prologue of 1,
433 * write 1 + 4 = 5 bytes to the TX FIFO and read 3 bytes from the RX FIFO.
434 * Caution, the additional 4 bytes spill over to the second TX sglist entry
435 * if the length of the first is *exactly* 1.
437 * At most 6 bytes are written and at most 3 bytes read. Do we know the
438 * transfer has this many bytes? Yes, see BCM2835_SPI_DMA_MIN_LENGTH.
440 * The FIFO is normally accessed with 8-bit width by the CPU and 32-bit width
441 * by the DMA engine. Toggling the DMA Enable flag in the CS register switches
442 * the width but also garbles the FIFO's contents. The prologue must therefore
443 * be transmitted in 32-bit width to ensure that the following DMA transfer can
444 * pick up the residue in the RX FIFO in ungarbled form.
446 static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr,
447 struct spi_transfer *tfr,
448 struct bcm2835_spi *bs,
456 bs->tx_spillover = false;
458 if (!sg_is_last(&tfr->tx_sg.sgl[0]))
459 bs->tx_prologue = sg_dma_len(&tfr->tx_sg.sgl[0]) & 3;
461 if (!sg_is_last(&tfr->rx_sg.sgl[0])) {
462 bs->rx_prologue = sg_dma_len(&tfr->rx_sg.sgl[0]) & 3;
464 if (bs->rx_prologue > bs->tx_prologue) {
465 if (sg_is_last(&tfr->tx_sg.sgl[0])) {
466 bs->tx_prologue = bs->rx_prologue;
468 bs->tx_prologue += 4;
470 !(sg_dma_len(&tfr->tx_sg.sgl[0]) & ~3);
475 /* rx_prologue > 0 implies tx_prologue > 0, so check only the latter */
476 if (!bs->tx_prologue)
479 /* Write and read RX prologue. Adjust first entry in RX sglist. */
480 if (bs->rx_prologue) {
481 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->rx_prologue);
482 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
483 | BCM2835_SPI_CS_DMAEN);
484 bcm2835_wr_fifo_count(bs, bs->rx_prologue);
485 bcm2835_wait_tx_fifo_empty(bs);
486 bcm2835_rd_fifo_count(bs, bs->rx_prologue);
487 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_RX
488 | BCM2835_SPI_CS_CLEAR_TX
489 | BCM2835_SPI_CS_DONE);
491 dma_sync_single_for_device(ctlr->dma_rx->device->dev,
492 sg_dma_address(&tfr->rx_sg.sgl[0]),
493 bs->rx_prologue, DMA_FROM_DEVICE);
495 sg_dma_address(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
496 sg_dma_len(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
500 * Write remaining TX prologue. Adjust first entry in TX sglist.
501 * Also adjust second entry if prologue spills over to it.
503 tx_remaining = bs->tx_prologue - bs->rx_prologue;
505 bcm2835_wr(bs, BCM2835_SPI_DLEN, tx_remaining);
506 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
507 | BCM2835_SPI_CS_DMAEN);
508 bcm2835_wr_fifo_count(bs, tx_remaining);
509 bcm2835_wait_tx_fifo_empty(bs);
510 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX
511 | BCM2835_SPI_CS_DONE);
514 if (likely(!bs->tx_spillover)) {
515 sg_dma_address(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
516 sg_dma_len(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
518 sg_dma_len(&tfr->tx_sg.sgl[0]) = 0;
519 sg_dma_address(&tfr->tx_sg.sgl[1]) += 4;
520 sg_dma_len(&tfr->tx_sg.sgl[1]) -= 4;
525 * bcm2835_spi_undo_prologue() - reconstruct original sglist state
526 * @bs: BCM2835 SPI controller
528 * Undo changes which were made to an SPI transfer's sglist when transmitting
529 * the prologue. This is necessary to ensure the same memory ranges are
530 * unmapped that were originally mapped.
532 static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs)
534 struct spi_transfer *tfr = bs->tfr;
536 if (!bs->tx_prologue)
539 if (bs->rx_prologue) {
540 sg_dma_address(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
541 sg_dma_len(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
544 if (likely(!bs->tx_spillover)) {
545 sg_dma_address(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
546 sg_dma_len(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
548 sg_dma_len(&tfr->tx_sg.sgl[0]) = bs->tx_prologue - 4;
549 sg_dma_address(&tfr->tx_sg.sgl[1]) -= 4;
550 sg_dma_len(&tfr->tx_sg.sgl[1]) += 4;
554 static void bcm2835_spi_dma_done(void *data)
556 struct spi_controller *ctlr = data;
557 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
559 /* reset fifo and HW */
560 bcm2835_spi_reset_hw(ctlr);
562 /* and terminate tx-dma as we do not have an irq for it
563 * because when the rx dma will terminate and this callback
564 * is called the tx-dma must have finished - can't get to this
565 * situation otherwise...
567 if (cmpxchg(&bs->dma_pending, true, false)) {
568 dmaengine_terminate_async(ctlr->dma_tx);
569 bcm2835_spi_undo_prologue(bs);
572 /* and mark as completed */;
573 complete(&ctlr->xfer_completion);
576 static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
577 struct spi_transfer *tfr,
580 struct dma_chan *chan;
581 struct scatterlist *sgl;
583 enum dma_transfer_direction dir;
586 struct dma_async_tx_descriptor *desc;
590 dir = DMA_MEM_TO_DEV;
592 nents = tfr->tx_sg.nents;
593 sgl = tfr->tx_sg.sgl;
594 flags = 0 /* no tx interrupt */;
597 dir = DMA_DEV_TO_MEM;
599 nents = tfr->rx_sg.nents;
600 sgl = tfr->rx_sg.sgl;
601 flags = DMA_PREP_INTERRUPT;
603 /* prepare the channel */
604 desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
608 /* set callback for rx */
610 desc->callback = bcm2835_spi_dma_done;
611 desc->callback_param = ctlr;
614 /* submit it to DMA-engine */
615 cookie = dmaengine_submit(desc);
617 return dma_submit_error(cookie);
620 static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr,
621 struct spi_device *spi,
622 struct spi_transfer *tfr,
625 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
628 /* update usage statistics */
629 bs->count_transfer_dma++;
632 * Transfer first few bytes without DMA if length of first TX or RX
633 * sglist entry is not a multiple of 4 bytes (hardware limitation).
635 bcm2835_spi_transfer_prologue(ctlr, tfr, bs, cs);
638 ret = bcm2835_spi_prepare_sg(ctlr, tfr, true);
643 dma_async_issue_pending(ctlr->dma_tx);
645 /* mark as dma pending */
648 /* set the DMA length */
649 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->tx_len);
652 bcm2835_wr(bs, BCM2835_SPI_CS,
653 cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN);
655 /* setup rx-DMA late - to run transfers while
656 * mapping of the rx buffers still takes place
657 * this saves 10us or more.
659 ret = bcm2835_spi_prepare_sg(ctlr, tfr, false);
661 /* need to reset on errors */
662 dmaengine_terminate_sync(ctlr->dma_tx);
663 bs->dma_pending = false;
667 /* start rx dma late */
668 dma_async_issue_pending(ctlr->dma_rx);
670 /* wait for wakeup in framework */
674 bcm2835_spi_reset_hw(ctlr);
675 bcm2835_spi_undo_prologue(bs);
679 static bool bcm2835_spi_can_dma(struct spi_controller *ctlr,
680 struct spi_device *spi,
681 struct spi_transfer *tfr)
683 /* we start DMA efforts only on bigger transfers */
684 if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH)
691 static void bcm2835_dma_release(struct spi_controller *ctlr)
694 dmaengine_terminate_sync(ctlr->dma_tx);
695 dma_release_channel(ctlr->dma_tx);
699 dmaengine_terminate_sync(ctlr->dma_rx);
700 dma_release_channel(ctlr->dma_rx);
705 static void bcm2835_dma_init(struct spi_controller *ctlr, struct device *dev)
707 struct dma_slave_config slave_config;
709 dma_addr_t dma_reg_base;
712 /* base address in dma-space */
713 addr = of_get_address(ctlr->dev.of_node, 0, NULL, NULL);
715 dev_err(dev, "could not get DMA-register address - not using dma mode\n");
718 dma_reg_base = be32_to_cpup(addr);
721 ctlr->dma_tx = dma_request_slave_channel(dev, "tx");
723 dev_err(dev, "no tx-dma configuration found - not using dma mode\n");
726 ctlr->dma_rx = dma_request_slave_channel(dev, "rx");
728 dev_err(dev, "no rx-dma configuration found - not using dma mode\n");
733 slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
734 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
736 ret = dmaengine_slave_config(ctlr->dma_tx, &slave_config);
740 slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
741 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
743 ret = dmaengine_slave_config(ctlr->dma_rx, &slave_config);
747 /* all went well, so set can_dma */
748 ctlr->can_dma = bcm2835_spi_can_dma;
749 /* need to do TX AND RX DMA, so we need dummy buffers */
750 ctlr->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
755 dev_err(dev, "issue configuring dma: %d - not using DMA mode\n",
758 bcm2835_dma_release(ctlr);
763 static int bcm2835_spi_transfer_one_poll(struct spi_controller *ctlr,
764 struct spi_device *spi,
765 struct spi_transfer *tfr,
768 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
769 unsigned long timeout;
771 /* update usage statistics */
772 bs->count_transfer_polling++;
774 /* enable HW block without interrupts */
775 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
777 /* fill in the fifo before timeout calculations
778 * if we are interrupted here, then the data is
779 * getting transferred by the HW while we are interrupted
781 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
783 /* set the timeout to at least 2 jiffies */
784 timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;
786 /* loop until finished the transfer */
788 /* fill in tx fifo with remaining data */
791 /* read from fifo as much as possible */
794 /* if there is still data pending to read
795 * then check the timeout
797 if (bs->rx_len && time_after(jiffies, timeout)) {
798 dev_dbg_ratelimited(&spi->dev,
799 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
801 bs->tx_len, bs->rx_len);
802 /* fall back to interrupt mode */
804 /* update usage statistics */
805 bs->count_transfer_irq_after_polling++;
807 return bcm2835_spi_transfer_one_irq(ctlr, spi,
812 /* Transfer complete - reset SPI HW */
813 bcm2835_spi_reset_hw(ctlr);
814 /* and return without waiting for completion */
818 static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
819 struct spi_device *spi,
820 struct spi_transfer *tfr)
822 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
823 unsigned long spi_hz, clk_hz, cdiv, spi_used_hz;
824 unsigned long hz_per_byte, byte_limit;
825 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
828 spi_hz = tfr->speed_hz;
829 clk_hz = clk_get_rate(bs->clk);
831 if (spi_hz >= clk_hz / 2) {
832 cdiv = 2; /* clk_hz/2 is the fastest we can go */
834 /* CDIV must be a multiple of two */
835 cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
839 cdiv = 0; /* 0 is the slowest we can go */
841 cdiv = 0; /* 0 is the slowest we can go */
843 spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
844 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
846 /* handle all the 3-wire mode */
847 if (spi->mode & SPI_3WIRE && tfr->rx_buf &&
848 tfr->rx_buf != ctlr->dummy_rx)
849 cs |= BCM2835_SPI_CS_REN;
851 cs &= ~BCM2835_SPI_CS_REN;
854 * The driver always uses software-controlled GPIO Chip Select.
855 * Set the hardware-controlled native Chip Select to an invalid
856 * value to prevent it from interfering.
858 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
860 /* set transmit buffers and length */
861 bs->tx_buf = tfr->tx_buf;
862 bs->rx_buf = tfr->rx_buf;
863 bs->tx_len = tfr->len;
864 bs->rx_len = tfr->len;
866 /* Calculate the estimated time in us the transfer runs. Note that
867 * there is 1 idle clocks cycles after each byte getting transferred
868 * so we have 9 cycles/byte. This is used to find the number of Hz
869 * per byte per polling limit. E.g., we can transfer 1 byte in 30 us
870 * per 300,000 Hz of bus clock.
872 hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
873 byte_limit = hz_per_byte ? spi_used_hz / hz_per_byte : 1;
875 /* run in polling mode for short transfers */
876 if (tfr->len < byte_limit)
877 return bcm2835_spi_transfer_one_poll(ctlr, spi, tfr, cs);
879 /* run in dma mode if conditions are right
880 * Note that unlike poll or interrupt mode DMA mode does not have
881 * this 1 idle clock cycle pattern but runs the spi clock without gaps
883 if (ctlr->can_dma && bcm2835_spi_can_dma(ctlr, spi, tfr))
884 return bcm2835_spi_transfer_one_dma(ctlr, spi, tfr, cs);
886 /* run in interrupt-mode */
887 return bcm2835_spi_transfer_one_irq(ctlr, spi, tfr, cs, true);
890 static int bcm2835_spi_prepare_message(struct spi_controller *ctlr,
891 struct spi_message *msg)
893 struct spi_device *spi = msg->spi;
894 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
895 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
900 * DMA transfers are limited to 16 bit (0 to 65535 bytes) by
901 * the SPI HW due to DLEN. Split up transfers (32-bit FIFO
902 * aligned) if the limit is exceeded.
904 ret = spi_split_transfers_maxsize(ctlr, msg, 65532,
905 GFP_KERNEL | GFP_DMA);
910 cs &= ~(BCM2835_SPI_CS_CPOL | BCM2835_SPI_CS_CPHA);
912 if (spi->mode & SPI_CPOL)
913 cs |= BCM2835_SPI_CS_CPOL;
914 if (spi->mode & SPI_CPHA)
915 cs |= BCM2835_SPI_CS_CPHA;
917 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
922 static void bcm2835_spi_handle_err(struct spi_controller *ctlr,
923 struct spi_message *msg)
925 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
927 /* if an error occurred and we have an active dma, then terminate */
928 if (cmpxchg(&bs->dma_pending, true, false)) {
929 dmaengine_terminate_sync(ctlr->dma_tx);
930 dmaengine_terminate_sync(ctlr->dma_rx);
931 bcm2835_spi_undo_prologue(bs);
934 bcm2835_spi_reset_hw(ctlr);
937 static int chip_match_name(struct gpio_chip *chip, void *data)
939 return !strcmp(chip->label, data);
942 static int bcm2835_spi_setup(struct spi_device *spi)
945 struct gpio_chip *chip;
947 * sanity checking the native-chipselects
949 if (spi->mode & SPI_NO_CS)
951 if (gpio_is_valid(spi->cs_gpio))
953 if (spi->chip_select > 1) {
954 /* error in the case of native CS requested with CS > 1
955 * officially there is a CS2, but it is not documented
956 * which GPIO is connected with that...
959 "setup: only two native chip-selects are supported\n");
962 /* now translate native cs to GPIO */
964 /* get the gpio chip for the base */
965 chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
969 /* and calculate the real CS */
970 spi->cs_gpio = chip->base + 8 - spi->chip_select;
972 /* and set up the "mode" and level */
973 dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
974 spi->chip_select, spi->cs_gpio);
976 /* set up GPIO as output and pull to the correct level */
977 err = gpio_direction_output(spi->cs_gpio,
978 (spi->mode & SPI_CS_HIGH) ? 0 : 1);
981 "could not set CS%i gpio %i as output: %i",
982 spi->chip_select, spi->cs_gpio, err);
989 static int bcm2835_spi_probe(struct platform_device *pdev)
991 struct spi_controller *ctlr;
992 struct bcm2835_spi *bs;
993 struct resource *res;
996 ctlr = spi_alloc_master(&pdev->dev, sizeof(*bs));
1000 platform_set_drvdata(pdev, ctlr);
1002 ctlr->mode_bits = BCM2835_SPI_MODE_BITS;
1003 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1004 ctlr->num_chipselect = 3;
1005 ctlr->setup = bcm2835_spi_setup;
1006 ctlr->transfer_one = bcm2835_spi_transfer_one;
1007 ctlr->handle_err = bcm2835_spi_handle_err;
1008 ctlr->prepare_message = bcm2835_spi_prepare_message;
1009 ctlr->dev.of_node = pdev->dev.of_node;
1011 bs = spi_controller_get_devdata(ctlr);
1013 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1014 bs->regs = devm_ioremap_resource(&pdev->dev, res);
1015 if (IS_ERR(bs->regs)) {
1016 err = PTR_ERR(bs->regs);
1017 goto out_controller_put;
1020 bs->clk = devm_clk_get(&pdev->dev, NULL);
1021 if (IS_ERR(bs->clk)) {
1022 err = PTR_ERR(bs->clk);
1023 dev_err(&pdev->dev, "could not get clk: %d\n", err);
1024 goto out_controller_put;
1027 bs->irq = platform_get_irq(pdev, 0);
1029 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
1030 err = bs->irq ? bs->irq : -ENODEV;
1031 goto out_controller_put;
1034 clk_prepare_enable(bs->clk);
1036 bcm2835_dma_init(ctlr, &pdev->dev);
1038 /* initialise the hardware with the default polarities */
1039 bcm2835_wr(bs, BCM2835_SPI_CS,
1040 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
1042 err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
1043 dev_name(&pdev->dev), ctlr);
1045 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
1046 goto out_clk_disable;
1049 err = devm_spi_register_controller(&pdev->dev, ctlr);
1051 dev_err(&pdev->dev, "could not register SPI controller: %d\n",
1053 goto out_clk_disable;
1056 bcm2835_debugfs_create(bs, dev_name(&pdev->dev));
1061 clk_disable_unprepare(bs->clk);
1063 spi_controller_put(ctlr);
1067 static int bcm2835_spi_remove(struct platform_device *pdev)
1069 struct spi_controller *ctlr = platform_get_drvdata(pdev);
1070 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
1072 bcm2835_debugfs_remove(bs);
1074 /* Clear FIFOs, and disable the HW block */
1075 bcm2835_wr(bs, BCM2835_SPI_CS,
1076 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
1078 clk_disable_unprepare(bs->clk);
1080 bcm2835_dma_release(ctlr);
1085 static const struct of_device_id bcm2835_spi_match[] = {
1086 { .compatible = "brcm,bcm2835-spi", },
1089 MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
1091 static struct platform_driver bcm2835_spi_driver = {
1094 .of_match_table = bcm2835_spi_match,
1096 .probe = bcm2835_spi_probe,
1097 .remove = bcm2835_spi_remove,
1099 module_platform_driver(bcm2835_spi_driver);
1101 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
1102 MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
1103 MODULE_LICENSE("GPL");