1 // SPDX-License-Identifier: GPL-2.0+
3 * spi driver for rockchip
5 * (C) Copyright 2015 Google, Inc
7 * (C) Copyright 2008-2013 Rockchip Electronics
8 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
14 #include <dt-structs.h>
17 #include <linux/errno.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/periph.h>
21 #include <dm/pinctrl.h>
24 /* Change to 1 to output registers at the start of each transaction */
25 #define DEBUG_RK_SPI 0
27 struct rockchip_spi_platdata {
28 #if CONFIG_IS_ENABLED(OF_PLATDATA)
29 struct dtd_rockchip_rk3288_spi of_plat;
31 s32 frequency; /* Default clock frequency, -1 for none */
33 uint deactivate_delay_us; /* Delay to wait after deactivate */
34 uint activate_delay_us; /* Delay to wait after activate */
37 struct rockchip_spi_priv {
38 struct rockchip_spi *regs;
40 unsigned int max_freq;
42 ulong last_transaction_us; /* Time of last transaction end */
43 unsigned int speed_hz;
44 unsigned int last_speed_hz;
48 #define SPI_FIFO_DEPTH 32
50 static void rkspi_dump_regs(struct rockchip_spi *regs)
52 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
53 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
54 debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
55 debug("ser: \t\t0x%08x\n", readl(®s->ser));
56 debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
57 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
58 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
59 debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
60 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
61 debug("sr: \t\t0x%08x\n", readl(®s->sr));
62 debug("imr: \t\t0x%08x\n", readl(®s->imr));
63 debug("isr: \t\t0x%08x\n", readl(®s->isr));
64 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
65 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
66 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
69 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
71 writel(enable ? 1 : 0, ®s->enr);
74 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
77 * We should try not to exceed the speed requested by the caller:
78 * when selecting a divider, we need to make sure we round up.
80 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
82 /* The baudrate register (BAUDR) is defined as a 32bit register where
83 * the upper 16bit are reserved and having 'Fsclk_out' in the lower
84 * 16bits with 'Fsclk_out' defined as follows:
86 * Fsclk_out = Fspi_clk/ SCKDV
87 * Where SCKDV is any even value between 2 and 65534.
89 if (clk_div > 0xfffe) {
91 debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
92 __func__, speed, priv->input_rate / clk_div);
95 /* Round up to the next even 16bit number */
96 clk_div = (clk_div + 1) & 0xfffe;
98 debug("spi speed %u, div %u\n", speed, clk_div);
100 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
101 priv->last_speed_hz = speed;
104 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
108 start = get_timer(0);
109 while (readl(®s->sr) & SR_BUSY) {
110 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
111 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
119 static void spi_cs_activate(struct udevice *dev, uint cs)
121 struct udevice *bus = dev->parent;
122 struct rockchip_spi_platdata *plat = bus->platdata;
123 struct rockchip_spi_priv *priv = dev_get_priv(bus);
124 struct rockchip_spi *regs = priv->regs;
126 /* If it's too soon to do another transaction, wait */
127 if (plat->deactivate_delay_us && priv->last_transaction_us) {
128 ulong delay_us; /* The delay completed so far */
129 delay_us = timer_get_us() - priv->last_transaction_us;
130 if (delay_us < plat->deactivate_delay_us) {
131 ulong additional_delay_us =
132 plat->deactivate_delay_us - delay_us;
133 debug("%s: delaying by %ld us\n",
134 __func__, additional_delay_us);
135 udelay(additional_delay_us);
139 debug("activate cs%u\n", cs);
140 writel(1 << cs, ®s->ser);
141 if (plat->activate_delay_us)
142 udelay(plat->activate_delay_us);
145 static void spi_cs_deactivate(struct udevice *dev, uint cs)
147 struct udevice *bus = dev->parent;
148 struct rockchip_spi_platdata *plat = bus->platdata;
149 struct rockchip_spi_priv *priv = dev_get_priv(bus);
150 struct rockchip_spi *regs = priv->regs;
152 debug("deactivate cs%u\n", cs);
153 writel(0, ®s->ser);
155 /* Remember time of this transaction so we can honour the bus delay */
156 if (plat->deactivate_delay_us)
157 priv->last_transaction_us = timer_get_us();
160 #if CONFIG_IS_ENABLED(OF_PLATDATA)
161 static int conv_of_platdata(struct udevice *dev)
163 struct rockchip_spi_platdata *plat = dev->platdata;
164 struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
165 struct rockchip_spi_priv *priv = dev_get_priv(dev);
168 plat->base = dtplat->reg[0];
169 plat->frequency = 20000000;
170 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
179 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
181 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
182 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
183 struct rockchip_spi_priv *priv = dev_get_priv(bus);
186 plat->base = dev_read_addr(bus);
188 ret = clk_get_by_index(bus, 0, &priv->clk);
190 debug("%s: Could not get clock for %s: %d\n", __func__,
196 dev_read_u32_default(bus, "spi-max-frequency", 50000000);
197 plat->deactivate_delay_us =
198 dev_read_u32_default(bus, "spi-deactivate-delay", 0);
199 plat->activate_delay_us =
200 dev_read_u32_default(bus, "spi-activate-delay", 0);
202 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
203 __func__, (uint)plat->base, plat->frequency,
204 plat->deactivate_delay_us);
210 static int rockchip_spi_calc_modclk(ulong max_freq)
213 * While this is not strictly correct for the RK3368, as the
214 * GPLL will be 576MHz, things will still work, as the
215 * clk_set_rate(...) implementation in our clock-driver will
216 * chose the next closest rate not exceeding what we request
217 * based on the output of this function.
221 const unsigned long gpll_hz = 594000000UL;
224 * We need to find an input clock that provides at least twice
225 * the maximum frequency and can be generated from the assumed
226 * speed of GPLL (594MHz) using an integer divider.
228 * To give us more achievable bitrates at higher speeds (these
229 * are generated by dividing by an even 16-bit integer from
230 * this frequency), we try to have an input frequency of at
231 * least 4x our max_freq.
234 div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
235 return gpll_hz / div;
238 static int rockchip_spi_probe(struct udevice *bus)
240 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
241 struct rockchip_spi_priv *priv = dev_get_priv(bus);
244 debug("%s: probe\n", __func__);
245 #if CONFIG_IS_ENABLED(OF_PLATDATA)
246 ret = conv_of_platdata(bus);
250 priv->regs = (struct rockchip_spi *)plat->base;
252 priv->last_transaction_us = timer_get_us();
253 priv->max_freq = plat->frequency;
255 /* Clamp the value from the DTS against any hardware limits */
256 if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
257 priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
259 /* Find a module-input clock that fits with the max_freq setting */
260 ret = clk_set_rate(&priv->clk,
261 rockchip_spi_calc_modclk(priv->max_freq));
263 debug("%s: Failed to set clock: %d\n", __func__, ret);
266 priv->input_rate = ret;
267 debug("%s: rate = %u\n", __func__, priv->input_rate);
272 static int rockchip_spi_claim_bus(struct udevice *dev)
274 struct udevice *bus = dev->parent;
275 struct rockchip_spi_priv *priv = dev_get_priv(bus);
276 struct rockchip_spi *regs = priv->regs;
279 /* Disable the SPI hardware */
280 rkspi_enable_chip(regs, false);
282 if (priv->speed_hz != priv->last_speed_hz)
283 rkspi_set_clk(priv, priv->speed_hz);
286 ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
288 /* Data Frame Size */
289 ctrlr0 |= DFS_8BIT << DFS_SHIFT;
291 /* set SPI mode 0..3 */
292 if (priv->mode & SPI_CPOL)
293 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
294 if (priv->mode & SPI_CPHA)
295 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
297 /* Chip Select Mode */
298 ctrlr0 |= CSM_KEEP << CSM_SHIFT;
300 /* SSN to Sclk_out delay */
301 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
303 /* Serial Endian Mode */
304 ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
307 ctrlr0 |= FBM_MSB << FBM_SHIFT;
309 /* Byte and Halfword Transform */
310 ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT;
312 /* Rxd Sample Delay */
313 ctrlr0 |= 0 << RXDSD_SHIFT;
316 ctrlr0 |= FRF_SPI << FRF_SHIFT;
319 ctrlr0 |= TMOD_TR << TMOD_SHIFT;
321 writel(ctrlr0, ®s->ctrlr0);
326 static int rockchip_spi_release_bus(struct udevice *dev)
328 struct udevice *bus = dev->parent;
329 struct rockchip_spi_priv *priv = dev_get_priv(bus);
331 rkspi_enable_chip(priv->regs, false);
336 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
337 const void *dout, void *din, unsigned long flags)
339 struct udevice *bus = dev->parent;
340 struct rockchip_spi_priv *priv = dev_get_priv(bus);
341 struct rockchip_spi *regs = priv->regs;
342 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
343 int len = bitlen >> 3;
344 const u8 *out = dout;
349 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
352 rkspi_dump_regs(regs);
354 /* Assert CS before transfer */
355 if (flags & SPI_XFER_BEGIN)
356 spi_cs_activate(dev, slave_plat->cs);
359 int todo = min(len, 0x10000);
361 rkspi_enable_chip(regs, false);
362 writel(todo - 1, ®s->ctrlr1);
363 rkspi_enable_chip(regs, true);
367 while (toread || towrite) {
368 u32 status = readl(®s->sr);
370 if (towrite && !(status & SR_TF_FULL)) {
371 writel(out ? *out++ : 0, regs->txdr);
374 if (toread && !(status & SR_RF_EMPT)) {
375 u32 byte = readl(regs->rxdr);
384 * In case that there's a transmit-component, we need to wait
385 * until the control goes idle before we can disable the SPI
386 * control logic (as this will implictly flush the FIFOs).
389 ret = rkspi_wait_till_not_busy(regs);
397 /* Deassert CS after transfer */
398 if (flags & SPI_XFER_END)
399 spi_cs_deactivate(dev, slave_plat->cs);
401 rkspi_enable_chip(regs, false);
406 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
408 struct rockchip_spi_priv *priv = dev_get_priv(bus);
410 /* Clamp to the maximum frequency specified in the DTS */
411 if (speed > priv->max_freq)
412 speed = priv->max_freq;
414 priv->speed_hz = speed;
419 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
421 struct rockchip_spi_priv *priv = dev_get_priv(bus);
428 static const struct dm_spi_ops rockchip_spi_ops = {
429 .claim_bus = rockchip_spi_claim_bus,
430 .release_bus = rockchip_spi_release_bus,
431 .xfer = rockchip_spi_xfer,
432 .set_speed = rockchip_spi_set_speed,
433 .set_mode = rockchip_spi_set_mode,
435 * cs_info is not needed, since we require all chip selects to be
436 * in the device tree explicitly
440 static const struct udevice_id rockchip_spi_ids[] = {
441 { .compatible = "rockchip,rk3288-spi" },
442 { .compatible = "rockchip,rk3368-spi" },
443 { .compatible = "rockchip,rk3399-spi" },
447 U_BOOT_DRIVER(rockchip_spi) = {
448 #if CONFIG_IS_ENABLED(OF_PLATDATA)
449 .name = "rockchip_rk3288_spi",
451 .name = "rockchip_spi",
454 .of_match = rockchip_spi_ids,
455 .ops = &rockchip_spi_ops,
456 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
457 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
458 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
459 .probe = rockchip_spi_probe,