1 // SPDX-License-Identifier: GPL-2.0+
3 * spi driver for rockchip
5 * (C) 2019 Theobroma Systems Design und Consulting GmbH
7 * (C) Copyright 2015 Google, Inc
9 * (C) Copyright 2008-2013 Rockchip Electronics
10 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
16 #include <dt-structs.h>
20 #include <linux/errno.h>
22 #include <asm/arch-rockchip/clock.h>
23 #include <asm/arch-rockchip/periph.h>
24 #include <dm/pinctrl.h>
27 /* Change to 1 to output registers at the start of each transaction */
28 #define DEBUG_RK_SPI 0
30 struct rockchip_spi_params {
31 /* RXFIFO overruns and TXFIFO underruns stop the master clock */
32 bool master_manages_fifo;
35 struct rockchip_spi_platdata {
36 #if CONFIG_IS_ENABLED(OF_PLATDATA)
37 struct dtd_rockchip_rk3288_spi of_plat;
39 s32 frequency; /* Default clock frequency, -1 for none */
41 uint deactivate_delay_us; /* Delay to wait after deactivate */
42 uint activate_delay_us; /* Delay to wait after activate */
45 struct rockchip_spi_priv {
46 struct rockchip_spi *regs;
48 unsigned int max_freq;
50 ulong last_transaction_us; /* Time of last transaction end */
51 unsigned int speed_hz;
52 unsigned int last_speed_hz;
56 #define SPI_FIFO_DEPTH 32
58 static void rkspi_dump_regs(struct rockchip_spi *regs)
60 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
61 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
62 debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
63 debug("ser: \t\t0x%08x\n", readl(®s->ser));
64 debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
65 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
66 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
67 debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
68 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
69 debug("sr: \t\t0x%08x\n", readl(®s->sr));
70 debug("imr: \t\t0x%08x\n", readl(®s->imr));
71 debug("isr: \t\t0x%08x\n", readl(®s->isr));
72 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
73 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
74 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
77 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
79 writel(enable ? 1 : 0, ®s->enr);
82 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
85 * We should try not to exceed the speed requested by the caller:
86 * when selecting a divider, we need to make sure we round up.
88 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
90 /* The baudrate register (BAUDR) is defined as a 32bit register where
91 * the upper 16bit are reserved and having 'Fsclk_out' in the lower
92 * 16bits with 'Fsclk_out' defined as follows:
94 * Fsclk_out = Fspi_clk/ SCKDV
95 * Where SCKDV is any even value between 2 and 65534.
97 if (clk_div > 0xfffe) {
99 debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
100 __func__, speed, priv->input_rate / clk_div);
103 /* Round up to the next even 16bit number */
104 clk_div = (clk_div + 1) & 0xfffe;
106 debug("spi speed %u, div %u\n", speed, clk_div);
108 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
109 priv->last_speed_hz = speed;
112 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
116 start = get_timer(0);
117 while (readl(®s->sr) & SR_BUSY) {
118 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
119 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
127 static void spi_cs_activate(struct udevice *dev, uint cs)
129 struct udevice *bus = dev->parent;
130 struct rockchip_spi_platdata *plat = bus->platdata;
131 struct rockchip_spi_priv *priv = dev_get_priv(bus);
132 struct rockchip_spi *regs = priv->regs;
134 /* If it's too soon to do another transaction, wait */
135 if (plat->deactivate_delay_us && priv->last_transaction_us) {
136 ulong delay_us; /* The delay completed so far */
137 delay_us = timer_get_us() - priv->last_transaction_us;
138 if (delay_us < plat->deactivate_delay_us) {
139 ulong additional_delay_us =
140 plat->deactivate_delay_us - delay_us;
141 debug("%s: delaying by %ld us\n",
142 __func__, additional_delay_us);
143 udelay(additional_delay_us);
147 debug("activate cs%u\n", cs);
148 writel(1 << cs, ®s->ser);
149 if (plat->activate_delay_us)
150 udelay(plat->activate_delay_us);
153 static void spi_cs_deactivate(struct udevice *dev, uint cs)
155 struct udevice *bus = dev->parent;
156 struct rockchip_spi_platdata *plat = bus->platdata;
157 struct rockchip_spi_priv *priv = dev_get_priv(bus);
158 struct rockchip_spi *regs = priv->regs;
160 debug("deactivate cs%u\n", cs);
161 writel(0, ®s->ser);
163 /* Remember time of this transaction so we can honour the bus delay */
164 if (plat->deactivate_delay_us)
165 priv->last_transaction_us = timer_get_us();
168 #if CONFIG_IS_ENABLED(OF_PLATDATA)
169 static int conv_of_platdata(struct udevice *dev)
171 struct rockchip_spi_platdata *plat = dev->platdata;
172 struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
173 struct rockchip_spi_priv *priv = dev_get_priv(dev);
176 plat->base = dtplat->reg[0];
177 plat->frequency = 20000000;
178 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
187 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
189 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
190 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
191 struct rockchip_spi_priv *priv = dev_get_priv(bus);
194 plat->base = dev_read_addr(bus);
196 ret = clk_get_by_index(bus, 0, &priv->clk);
198 debug("%s: Could not get clock for %s: %d\n", __func__,
204 dev_read_u32_default(bus, "spi-max-frequency", 50000000);
205 plat->deactivate_delay_us =
206 dev_read_u32_default(bus, "spi-deactivate-delay", 0);
207 plat->activate_delay_us =
208 dev_read_u32_default(bus, "spi-activate-delay", 0);
210 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
211 __func__, (uint)plat->base, plat->frequency,
212 plat->deactivate_delay_us);
218 static int rockchip_spi_calc_modclk(ulong max_freq)
221 * While this is not strictly correct for the RK3368, as the
222 * GPLL will be 576MHz, things will still work, as the
223 * clk_set_rate(...) implementation in our clock-driver will
224 * chose the next closest rate not exceeding what we request
225 * based on the output of this function.
229 const unsigned long gpll_hz = 594000000UL;
232 * We need to find an input clock that provides at least twice
233 * the maximum frequency and can be generated from the assumed
234 * speed of GPLL (594MHz) using an integer divider.
236 * To give us more achievable bitrates at higher speeds (these
237 * are generated by dividing by an even 16-bit integer from
238 * this frequency), we try to have an input frequency of at
239 * least 4x our max_freq.
242 div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
243 return gpll_hz / div;
246 static int rockchip_spi_probe(struct udevice *bus)
248 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
249 struct rockchip_spi_priv *priv = dev_get_priv(bus);
252 debug("%s: probe\n", __func__);
253 #if CONFIG_IS_ENABLED(OF_PLATDATA)
254 ret = conv_of_platdata(bus);
258 priv->regs = (struct rockchip_spi *)plat->base;
260 priv->last_transaction_us = timer_get_us();
261 priv->max_freq = plat->frequency;
263 /* Clamp the value from the DTS against any hardware limits */
264 if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
265 priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
267 /* Find a module-input clock that fits with the max_freq setting */
268 ret = clk_set_rate(&priv->clk,
269 rockchip_spi_calc_modclk(priv->max_freq));
271 debug("%s: Failed to set clock: %d\n", __func__, ret);
274 priv->input_rate = ret;
275 debug("%s: rate = %u\n", __func__, priv->input_rate);
280 static int rockchip_spi_claim_bus(struct udevice *dev)
282 struct udevice *bus = dev->parent;
283 struct rockchip_spi_priv *priv = dev_get_priv(bus);
284 struct rockchip_spi *regs = priv->regs;
287 /* Disable the SPI hardware */
288 rkspi_enable_chip(regs, false);
290 if (priv->speed_hz != priv->last_speed_hz)
291 rkspi_set_clk(priv, priv->speed_hz);
294 ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
296 /* Data Frame Size */
297 ctrlr0 |= DFS_8BIT << DFS_SHIFT;
299 /* set SPI mode 0..3 */
300 if (priv->mode & SPI_CPOL)
301 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
302 if (priv->mode & SPI_CPHA)
303 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
305 /* Chip Select Mode */
306 ctrlr0 |= CSM_KEEP << CSM_SHIFT;
308 /* SSN to Sclk_out delay */
309 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
311 /* Serial Endian Mode */
312 ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
315 ctrlr0 |= FBM_MSB << FBM_SHIFT;
317 /* Byte and Halfword Transform */
318 ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT;
320 /* Rxd Sample Delay */
321 ctrlr0 |= 0 << RXDSD_SHIFT;
324 ctrlr0 |= FRF_SPI << FRF_SHIFT;
327 ctrlr0 |= TMOD_TR << TMOD_SHIFT;
329 writel(ctrlr0, ®s->ctrlr0);
334 static int rockchip_spi_release_bus(struct udevice *dev)
336 struct udevice *bus = dev->parent;
337 struct rockchip_spi_priv *priv = dev_get_priv(bus);
339 rkspi_enable_chip(priv->regs, false);
344 static inline int rockchip_spi_16bit_reader(struct udevice *dev,
347 struct udevice *bus = dev->parent;
348 const struct rockchip_spi_params * const data =
349 (void *)dev_get_driver_data(bus);
350 struct rockchip_spi_priv *priv = dev_get_priv(bus);
351 struct rockchip_spi *regs = priv->regs;
352 const u32 saved_ctrlr0 = readl(®s->ctrlr0);
354 u32 statistics_rxlevels[33] = { };
356 u32 frames = *len / 2;
357 u8 *in = (u8 *)(*din);
358 u32 max_chunk_size = SPI_FIFO_DEPTH;
364 * If we know that the hardware will manage RXFIFO overruns
365 * (i.e. stop the SPI clock until there's space in the FIFO),
366 * we the allow largest possible chunk size that can be
367 * represented in CTRLR1.
369 if (data && data->master_manages_fifo)
370 max_chunk_size = 0x10000;
372 // rockchip_spi_configure(dev, mode, size)
373 rkspi_enable_chip(regs, false);
374 clrsetbits_le32(®s->ctrlr0,
375 TMOD_MASK << TMOD_SHIFT,
376 TMOD_RO << TMOD_SHIFT);
377 /* 16bit data frame size */
378 clrsetbits_le32(®s->ctrlr0, DFS_MASK, DFS_16BIT);
380 /* Update caller's context */
381 const u32 bytes_to_process = 2 * frames;
382 *din += bytes_to_process;
383 *len -= bytes_to_process;
385 /* Process our frames */
387 u32 chunk_size = min(frames, max_chunk_size);
389 frames -= chunk_size;
391 writew(chunk_size - 1, ®s->ctrlr1);
392 rkspi_enable_chip(regs, true);
395 u32 rx_level = readw(®s->rxflr);
397 statistics_rxlevels[rx_level]++;
399 chunk_size -= rx_level;
401 u16 val = readw(regs->rxdr);
405 } while (chunk_size);
407 rkspi_enable_chip(regs, false);
411 debug("%s: observed rx_level during processing:\n", __func__);
412 for (int i = 0; i <= 32; ++i)
413 if (statistics_rxlevels[i])
414 debug("\t%2d: %d\n", i, statistics_rxlevels[i]);
416 /* Restore the original transfer setup and return error-free. */
417 writel(saved_ctrlr0, ®s->ctrlr0);
421 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
422 const void *dout, void *din, unsigned long flags)
424 struct udevice *bus = dev->parent;
425 struct rockchip_spi_priv *priv = dev_get_priv(bus);
426 struct rockchip_spi *regs = priv->regs;
427 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
428 int len = bitlen >> 3;
429 const u8 *out = dout;
434 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
437 rkspi_dump_regs(regs);
439 /* Assert CS before transfer */
440 if (flags & SPI_XFER_BEGIN)
441 spi_cs_activate(dev, slave_plat->cs);
444 * To ensure fast loading of firmware images (e.g. full U-Boot
445 * stage, ATF, Linux kernel) from SPI flash, we optimise the
446 * case of read-only transfers by using the full 16bits of each
450 ret = rockchip_spi_16bit_reader(dev, &in, &len);
452 /* This is the original 8bit reader/writer code */
454 int todo = min(len, 0x10000);
456 rkspi_enable_chip(regs, false);
457 writel(todo - 1, ®s->ctrlr1);
458 rkspi_enable_chip(regs, true);
462 while (toread || towrite) {
463 u32 status = readl(®s->sr);
465 if (towrite && !(status & SR_TF_FULL)) {
466 writel(out ? *out++ : 0, regs->txdr);
469 if (toread && !(status & SR_RF_EMPT)) {
470 u32 byte = readl(regs->rxdr);
479 * In case that there's a transmit-component, we need to wait
480 * until the control goes idle before we can disable the SPI
481 * control logic (as this will implictly flush the FIFOs).
484 ret = rkspi_wait_till_not_busy(regs);
492 /* Deassert CS after transfer */
493 if (flags & SPI_XFER_END)
494 spi_cs_deactivate(dev, slave_plat->cs);
496 rkspi_enable_chip(regs, false);
501 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
503 struct rockchip_spi_priv *priv = dev_get_priv(bus);
505 /* Clamp to the maximum frequency specified in the DTS */
506 if (speed > priv->max_freq)
507 speed = priv->max_freq;
509 priv->speed_hz = speed;
514 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
516 struct rockchip_spi_priv *priv = dev_get_priv(bus);
523 static const struct dm_spi_ops rockchip_spi_ops = {
524 .claim_bus = rockchip_spi_claim_bus,
525 .release_bus = rockchip_spi_release_bus,
526 .xfer = rockchip_spi_xfer,
527 .set_speed = rockchip_spi_set_speed,
528 .set_mode = rockchip_spi_set_mode,
530 * cs_info is not needed, since we require all chip selects to be
531 * in the device tree explicitly
535 const struct rockchip_spi_params rk3399_spi_params = {
536 .master_manages_fifo = true,
539 static const struct udevice_id rockchip_spi_ids[] = {
540 { .compatible = "rockchip,rk3288-spi" },
541 { .compatible = "rockchip,rk3368-spi",
542 .data = (ulong)&rk3399_spi_params },
543 { .compatible = "rockchip,rk3399-spi",
544 .data = (ulong)&rk3399_spi_params },
548 U_BOOT_DRIVER(rockchip_spi) = {
549 #if CONFIG_IS_ENABLED(OF_PLATDATA)
550 .name = "rockchip_rk3288_spi",
552 .name = "rockchip_spi",
555 .of_match = rockchip_spi_ids,
556 .ops = &rockchip_spi_ops,
557 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
558 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
559 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
560 .probe = rockchip_spi_probe,