1 // SPDX-License-Identifier: GPL-2.0+
3 * spi driver for rockchip
5 * (C) 2019 Theobroma Systems Design und Consulting GmbH
7 * (C) Copyright 2015 Google, Inc
9 * (C) Copyright 2008-2013 Rockchip Electronics
10 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
16 #include <dt-structs.h>
19 #include <linux/errno.h>
21 #include <asm/arch-rockchip/clock.h>
22 #include <asm/arch-rockchip/periph.h>
23 #include <dm/pinctrl.h>
26 /* Change to 1 to output registers at the start of each transaction */
27 #define DEBUG_RK_SPI 0
29 struct rockchip_spi_params {
30 /* RXFIFO overruns and TXFIFO underruns stop the master clock */
31 bool master_manages_fifo;
34 struct rockchip_spi_platdata {
35 #if CONFIG_IS_ENABLED(OF_PLATDATA)
36 struct dtd_rockchip_rk3288_spi of_plat;
38 s32 frequency; /* Default clock frequency, -1 for none */
40 uint deactivate_delay_us; /* Delay to wait after deactivate */
41 uint activate_delay_us; /* Delay to wait after activate */
44 struct rockchip_spi_priv {
45 struct rockchip_spi *regs;
47 unsigned int max_freq;
49 ulong last_transaction_us; /* Time of last transaction end */
50 unsigned int speed_hz;
51 unsigned int last_speed_hz;
55 #define SPI_FIFO_DEPTH 32
57 static void rkspi_dump_regs(struct rockchip_spi *regs)
59 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
60 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
61 debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
62 debug("ser: \t\t0x%08x\n", readl(®s->ser));
63 debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
64 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
65 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
66 debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
67 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
68 debug("sr: \t\t0x%08x\n", readl(®s->sr));
69 debug("imr: \t\t0x%08x\n", readl(®s->imr));
70 debug("isr: \t\t0x%08x\n", readl(®s->isr));
71 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
72 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
73 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
76 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
78 writel(enable ? 1 : 0, ®s->enr);
81 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
84 * We should try not to exceed the speed requested by the caller:
85 * when selecting a divider, we need to make sure we round up.
87 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
89 /* The baudrate register (BAUDR) is defined as a 32bit register where
90 * the upper 16bit are reserved and having 'Fsclk_out' in the lower
91 * 16bits with 'Fsclk_out' defined as follows:
93 * Fsclk_out = Fspi_clk/ SCKDV
94 * Where SCKDV is any even value between 2 and 65534.
96 if (clk_div > 0xfffe) {
98 debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
99 __func__, speed, priv->input_rate / clk_div);
102 /* Round up to the next even 16bit number */
103 clk_div = (clk_div + 1) & 0xfffe;
105 debug("spi speed %u, div %u\n", speed, clk_div);
107 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
108 priv->last_speed_hz = speed;
111 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
115 start = get_timer(0);
116 while (readl(®s->sr) & SR_BUSY) {
117 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
118 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
126 static void spi_cs_activate(struct udevice *dev, uint cs)
128 struct udevice *bus = dev->parent;
129 struct rockchip_spi_platdata *plat = bus->platdata;
130 struct rockchip_spi_priv *priv = dev_get_priv(bus);
131 struct rockchip_spi *regs = priv->regs;
133 /* If it's too soon to do another transaction, wait */
134 if (plat->deactivate_delay_us && priv->last_transaction_us) {
135 ulong delay_us; /* The delay completed so far */
136 delay_us = timer_get_us() - priv->last_transaction_us;
137 if (delay_us < plat->deactivate_delay_us) {
138 ulong additional_delay_us =
139 plat->deactivate_delay_us - delay_us;
140 debug("%s: delaying by %ld us\n",
141 __func__, additional_delay_us);
142 udelay(additional_delay_us);
146 debug("activate cs%u\n", cs);
147 writel(1 << cs, ®s->ser);
148 if (plat->activate_delay_us)
149 udelay(plat->activate_delay_us);
152 static void spi_cs_deactivate(struct udevice *dev, uint cs)
154 struct udevice *bus = dev->parent;
155 struct rockchip_spi_platdata *plat = bus->platdata;
156 struct rockchip_spi_priv *priv = dev_get_priv(bus);
157 struct rockchip_spi *regs = priv->regs;
159 debug("deactivate cs%u\n", cs);
160 writel(0, ®s->ser);
162 /* Remember time of this transaction so we can honour the bus delay */
163 if (plat->deactivate_delay_us)
164 priv->last_transaction_us = timer_get_us();
167 #if CONFIG_IS_ENABLED(OF_PLATDATA)
168 static int conv_of_platdata(struct udevice *dev)
170 struct rockchip_spi_platdata *plat = dev->platdata;
171 struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
172 struct rockchip_spi_priv *priv = dev_get_priv(dev);
175 plat->base = dtplat->reg[0];
176 plat->frequency = 20000000;
177 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
186 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
188 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
189 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
190 struct rockchip_spi_priv *priv = dev_get_priv(bus);
193 plat->base = dev_read_addr(bus);
195 ret = clk_get_by_index(bus, 0, &priv->clk);
197 debug("%s: Could not get clock for %s: %d\n", __func__,
203 dev_read_u32_default(bus, "spi-max-frequency", 50000000);
204 plat->deactivate_delay_us =
205 dev_read_u32_default(bus, "spi-deactivate-delay", 0);
206 plat->activate_delay_us =
207 dev_read_u32_default(bus, "spi-activate-delay", 0);
209 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
210 __func__, (uint)plat->base, plat->frequency,
211 plat->deactivate_delay_us);
217 static int rockchip_spi_calc_modclk(ulong max_freq)
220 * While this is not strictly correct for the RK3368, as the
221 * GPLL will be 576MHz, things will still work, as the
222 * clk_set_rate(...) implementation in our clock-driver will
223 * chose the next closest rate not exceeding what we request
224 * based on the output of this function.
228 const unsigned long gpll_hz = 594000000UL;
231 * We need to find an input clock that provides at least twice
232 * the maximum frequency and can be generated from the assumed
233 * speed of GPLL (594MHz) using an integer divider.
235 * To give us more achievable bitrates at higher speeds (these
236 * are generated by dividing by an even 16-bit integer from
237 * this frequency), we try to have an input frequency of at
238 * least 4x our max_freq.
241 div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
242 return gpll_hz / div;
245 static int rockchip_spi_probe(struct udevice *bus)
247 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
248 struct rockchip_spi_priv *priv = dev_get_priv(bus);
251 debug("%s: probe\n", __func__);
252 #if CONFIG_IS_ENABLED(OF_PLATDATA)
253 ret = conv_of_platdata(bus);
257 priv->regs = (struct rockchip_spi *)plat->base;
259 priv->last_transaction_us = timer_get_us();
260 priv->max_freq = plat->frequency;
262 /* Clamp the value from the DTS against any hardware limits */
263 if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
264 priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
266 /* Find a module-input clock that fits with the max_freq setting */
267 ret = clk_set_rate(&priv->clk,
268 rockchip_spi_calc_modclk(priv->max_freq));
270 debug("%s: Failed to set clock: %d\n", __func__, ret);
273 priv->input_rate = ret;
274 debug("%s: rate = %u\n", __func__, priv->input_rate);
279 static int rockchip_spi_claim_bus(struct udevice *dev)
281 struct udevice *bus = dev->parent;
282 struct rockchip_spi_priv *priv = dev_get_priv(bus);
283 struct rockchip_spi *regs = priv->regs;
286 /* Disable the SPI hardware */
287 rkspi_enable_chip(regs, false);
289 if (priv->speed_hz != priv->last_speed_hz)
290 rkspi_set_clk(priv, priv->speed_hz);
293 ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
295 /* Data Frame Size */
296 ctrlr0 |= DFS_8BIT << DFS_SHIFT;
298 /* set SPI mode 0..3 */
299 if (priv->mode & SPI_CPOL)
300 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
301 if (priv->mode & SPI_CPHA)
302 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
304 /* Chip Select Mode */
305 ctrlr0 |= CSM_KEEP << CSM_SHIFT;
307 /* SSN to Sclk_out delay */
308 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
310 /* Serial Endian Mode */
311 ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
314 ctrlr0 |= FBM_MSB << FBM_SHIFT;
316 /* Byte and Halfword Transform */
317 ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT;
319 /* Rxd Sample Delay */
320 ctrlr0 |= 0 << RXDSD_SHIFT;
323 ctrlr0 |= FRF_SPI << FRF_SHIFT;
326 ctrlr0 |= TMOD_TR << TMOD_SHIFT;
328 writel(ctrlr0, ®s->ctrlr0);
333 static int rockchip_spi_release_bus(struct udevice *dev)
335 struct udevice *bus = dev->parent;
336 struct rockchip_spi_priv *priv = dev_get_priv(bus);
338 rkspi_enable_chip(priv->regs, false);
343 static inline int rockchip_spi_16bit_reader(struct udevice *dev,
346 struct udevice *bus = dev->parent;
347 const struct rockchip_spi_params * const data =
348 (void *)dev_get_driver_data(bus);
349 struct rockchip_spi_priv *priv = dev_get_priv(bus);
350 struct rockchip_spi *regs = priv->regs;
351 const u32 saved_ctrlr0 = readl(®s->ctrlr0);
353 u32 statistics_rxlevels[33] = { };
355 u32 frames = *len / 2;
356 u8 *in = (u8 *)(*din);
357 u32 max_chunk_size = SPI_FIFO_DEPTH;
363 * If we know that the hardware will manage RXFIFO overruns
364 * (i.e. stop the SPI clock until there's space in the FIFO),
365 * we the allow largest possible chunk size that can be
366 * represented in CTRLR1.
368 if (data && data->master_manages_fifo)
369 max_chunk_size = 0x10000;
371 // rockchip_spi_configure(dev, mode, size)
372 rkspi_enable_chip(regs, false);
373 clrsetbits_le32(®s->ctrlr0,
374 TMOD_MASK << TMOD_SHIFT,
375 TMOD_RO << TMOD_SHIFT);
376 /* 16bit data frame size */
377 clrsetbits_le32(®s->ctrlr0, DFS_MASK, DFS_16BIT);
379 /* Update caller's context */
380 const u32 bytes_to_process = 2 * frames;
381 *din += bytes_to_process;
382 *len -= bytes_to_process;
384 /* Process our frames */
386 u32 chunk_size = min(frames, max_chunk_size);
388 frames -= chunk_size;
390 writew(chunk_size - 1, ®s->ctrlr1);
391 rkspi_enable_chip(regs, true);
394 u32 rx_level = readw(®s->rxflr);
396 statistics_rxlevels[rx_level]++;
398 chunk_size -= rx_level;
400 u16 val = readw(regs->rxdr);
404 } while (chunk_size);
406 rkspi_enable_chip(regs, false);
410 debug("%s: observed rx_level during processing:\n", __func__);
411 for (int i = 0; i <= 32; ++i)
412 if (statistics_rxlevels[i])
413 debug("\t%2d: %d\n", i, statistics_rxlevels[i]);
415 /* Restore the original transfer setup and return error-free. */
416 writel(saved_ctrlr0, ®s->ctrlr0);
420 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
421 const void *dout, void *din, unsigned long flags)
423 struct udevice *bus = dev->parent;
424 struct rockchip_spi_priv *priv = dev_get_priv(bus);
425 struct rockchip_spi *regs = priv->regs;
426 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
427 int len = bitlen >> 3;
428 const u8 *out = dout;
433 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
436 rkspi_dump_regs(regs);
438 /* Assert CS before transfer */
439 if (flags & SPI_XFER_BEGIN)
440 spi_cs_activate(dev, slave_plat->cs);
443 * To ensure fast loading of firmware images (e.g. full U-Boot
444 * stage, ATF, Linux kernel) from SPI flash, we optimise the
445 * case of read-only transfers by using the full 16bits of each
449 ret = rockchip_spi_16bit_reader(dev, &in, &len);
451 /* This is the original 8bit reader/writer code */
453 int todo = min(len, 0x10000);
455 rkspi_enable_chip(regs, false);
456 writel(todo - 1, ®s->ctrlr1);
457 rkspi_enable_chip(regs, true);
461 while (toread || towrite) {
462 u32 status = readl(®s->sr);
464 if (towrite && !(status & SR_TF_FULL)) {
465 writel(out ? *out++ : 0, regs->txdr);
468 if (toread && !(status & SR_RF_EMPT)) {
469 u32 byte = readl(regs->rxdr);
478 * In case that there's a transmit-component, we need to wait
479 * until the control goes idle before we can disable the SPI
480 * control logic (as this will implictly flush the FIFOs).
483 ret = rkspi_wait_till_not_busy(regs);
491 /* Deassert CS after transfer */
492 if (flags & SPI_XFER_END)
493 spi_cs_deactivate(dev, slave_plat->cs);
495 rkspi_enable_chip(regs, false);
500 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
502 struct rockchip_spi_priv *priv = dev_get_priv(bus);
504 /* Clamp to the maximum frequency specified in the DTS */
505 if (speed > priv->max_freq)
506 speed = priv->max_freq;
508 priv->speed_hz = speed;
513 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
515 struct rockchip_spi_priv *priv = dev_get_priv(bus);
522 static const struct dm_spi_ops rockchip_spi_ops = {
523 .claim_bus = rockchip_spi_claim_bus,
524 .release_bus = rockchip_spi_release_bus,
525 .xfer = rockchip_spi_xfer,
526 .set_speed = rockchip_spi_set_speed,
527 .set_mode = rockchip_spi_set_mode,
529 * cs_info is not needed, since we require all chip selects to be
530 * in the device tree explicitly
534 const struct rockchip_spi_params rk3399_spi_params = {
535 .master_manages_fifo = true,
538 static const struct udevice_id rockchip_spi_ids[] = {
539 { .compatible = "rockchip,rk3288-spi" },
540 { .compatible = "rockchip,rk3368-spi",
541 .data = (ulong)&rk3399_spi_params },
542 { .compatible = "rockchip,rk3399-spi",
543 .data = (ulong)&rk3399_spi_params },
547 U_BOOT_DRIVER(rockchip_spi) = {
548 #if CONFIG_IS_ENABLED(OF_PLATDATA)
549 .name = "rockchip_rk3288_spi",
551 .name = "rockchip_spi",
554 .of_match = rockchip_spi_ids,
555 .ops = &rockchip_spi_ops,
556 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
557 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
558 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
559 .probe = rockchip_spi_probe,