2 * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
4 * Driver for McSPI controller on OMAP3. Based on davinci_spi.c
5 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7 * Copyright (C) 2007 Atmel Corporation
9 * Parts taken from linux/drivers/spi/omap2_mcspi.c
10 * Copyright (C) 2005, 2006 Nokia Corporation
12 * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
14 * SPDX-License-Identifier: GPL-2.0+
21 #include "omap3_spi.h"
23 #define SPI_WAIT_TIMEOUT 10
25 static void spi_reset(struct omap3_spi_slave *ds)
29 writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &ds->regs->sysconfig);
31 tmp = readl(&ds->regs->sysstatus);
32 } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
34 writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
35 OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
36 OMAP3_MCSPI_SYSCONFIG_SMARTIDLE,
37 &ds->regs->sysconfig);
39 writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &ds->regs->wakeupenable);
42 static void omap3_spi_write_chconf(struct omap3_spi_slave *ds, int val)
44 writel(val, &ds->regs->channel[ds->slave.cs].chconf);
45 /* Flash post writes to make immediate effect */
46 readl(&ds->regs->channel[ds->slave.cs].chconf);
49 static void omap3_spi_set_enable(struct omap3_spi_slave *ds, int enable)
51 writel(enable, &ds->regs->channel[ds->slave.cs].chctrl);
52 /* Flash post writes to make immediate effect */
53 readl(&ds->regs->channel[ds->slave.cs].chctrl);
61 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
62 unsigned int max_hz, unsigned int mode)
64 struct omap3_spi_slave *ds;
68 * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
69 * with different number of chip selects (CS, channels):
70 * McSPI1 has 4 CS (bus 0, cs 0 - 3)
71 * McSPI2 has 2 CS (bus 1, cs 0 - 1)
72 * McSPI3 has 2 CS (bus 2, cs 0 - 1)
73 * McSPI4 has 1 CS (bus 3, cs 0)
78 regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
80 #ifdef OMAP3_MCSPI2_BASE
82 regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
85 #ifdef OMAP3_MCSPI3_BASE
87 regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
90 #ifdef OMAP3_MCSPI4_BASE
92 regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
96 printf("SPI error: unsupported bus %i. \
97 Supported busses 0 - 3\n", bus);
101 if (((bus == 0) && (cs > 3)) ||
102 ((bus == 1) && (cs > 1)) ||
103 ((bus == 2) && (cs > 1)) ||
104 ((bus == 3) && (cs > 0))) {
105 printf("SPI error: unsupported chip select %i \
106 on bus %i\n", cs, bus);
110 if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
111 printf("SPI error: unsupported frequency %i Hz. \
112 Max frequency is 48 Mhz\n", max_hz);
116 if (mode > SPI_MODE_3) {
117 printf("SPI error: unsupported SPI mode %i\n", mode);
121 ds = spi_alloc_slave(struct omap3_spi_slave, bus, cs);
123 printf("SPI error: malloc of SPI structure failed\n");
134 void spi_free_slave(struct spi_slave *slave)
136 struct omap3_spi_slave *ds = to_omap3_spi(slave);
141 int spi_claim_bus(struct spi_slave *slave)
143 struct omap3_spi_slave *ds = to_omap3_spi(slave);
144 unsigned int conf, div = 0;
146 /* McSPI global module configuration */
149 * setup when switching from (reset default) slave mode
150 * to single-channel master mode
153 conf = readl(&ds->regs->modulctrl);
154 conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
155 conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
156 writel(conf, &ds->regs->modulctrl);
158 /* McSPI individual channel configuration */
160 /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
162 while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
168 conf = readl(&ds->regs->channel[ds->slave.cs].chconf);
170 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
171 * REVISIT: this controller could support SPI_3WIRE mode.
173 #ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED
175 * Some boards have D0 wired as MOSI / D1 as MISO instead of
176 * The normal D0 as MISO / D1 as MOSI.
178 conf &= ~OMAP3_MCSPI_CHCONF_DPE0;
179 conf |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
181 conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
182 conf |= OMAP3_MCSPI_CHCONF_DPE0;
186 conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
187 conf |= (ds->slave.wordlen - 1) << 7;
189 /* set chipselect polarity; manage with FORCE */
190 if (!(ds->mode & SPI_CS_HIGH))
191 conf |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
193 conf &= ~OMAP3_MCSPI_CHCONF_EPOL;
195 /* set clock divisor */
196 conf &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
199 /* set SPI mode 0..3 */
200 if (ds->mode & SPI_CPOL)
201 conf |= OMAP3_MCSPI_CHCONF_POL;
203 conf &= ~OMAP3_MCSPI_CHCONF_POL;
204 if (ds->mode & SPI_CPHA)
205 conf |= OMAP3_MCSPI_CHCONF_PHA;
207 conf &= ~OMAP3_MCSPI_CHCONF_PHA;
209 /* Transmit & receive mode */
210 conf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
212 omap3_spi_write_chconf(ds,conf);
217 void spi_release_bus(struct spi_slave *slave)
219 struct omap3_spi_slave *ds = to_omap3_spi(slave);
221 /* Reset the SPI hardware */
225 int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp,
228 struct omap3_spi_slave *ds = to_omap3_spi(slave);
231 int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
233 /* Enable the channel */
234 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
236 chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
237 chconf |= (ds->slave.wordlen - 1) << 7;
238 chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
239 chconf |= OMAP3_MCSPI_CHCONF_FORCE;
240 omap3_spi_write_chconf(ds,chconf);
242 for (i = 0; i < len; i++) {
243 /* wait till TX register is empty (TXS == 1) */
244 start = get_timer(0);
245 while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
246 OMAP3_MCSPI_CHSTAT_TXS)) {
247 if (get_timer(start) > SPI_WAIT_TIMEOUT) {
248 printf("SPI TXS timed out, status=0x%08x\n",
249 readl(&ds->regs->channel[ds->slave.cs].chstat));
254 unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx;
255 if (ds->slave.wordlen > 16)
256 writel(((u32 *)txp)[i], tx);
257 else if (ds->slave.wordlen > 8)
258 writel(((u16 *)txp)[i], tx);
260 writel(((u8 *)txp)[i], tx);
263 /* wait to finish of transfer */
264 while ((readl(&ds->regs->channel[ds->slave.cs].chstat) &
265 (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
266 (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS));
268 /* Disable the channel otherwise the next immediate RX will get affected */
269 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
271 if (flags & SPI_XFER_END) {
273 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
274 omap3_spi_write_chconf(ds,chconf);
279 int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp,
282 struct omap3_spi_slave *ds = to_omap3_spi(slave);
285 int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
287 /* Enable the channel */
288 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
290 chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
291 chconf |= (ds->slave.wordlen - 1) << 7;
292 chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
293 chconf |= OMAP3_MCSPI_CHCONF_FORCE;
294 omap3_spi_write_chconf(ds,chconf);
296 writel(0, &ds->regs->channel[ds->slave.cs].tx);
298 for (i = 0; i < len; i++) {
299 start = get_timer(0);
300 /* Wait till RX register contains data (RXS == 1) */
301 while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
302 OMAP3_MCSPI_CHSTAT_RXS)) {
303 if (get_timer(start) > SPI_WAIT_TIMEOUT) {
304 printf("SPI RXS timed out, status=0x%08x\n",
305 readl(&ds->regs->channel[ds->slave.cs].chstat));
310 /* Disable the channel to prevent furher receiving */
312 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
315 unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx;
316 if (ds->slave.wordlen > 16)
317 ((u32 *)rxp)[i] = readl(rx);
318 else if (ds->slave.wordlen > 8)
319 ((u16 *)rxp)[i] = (u16)readl(rx);
321 ((u8 *)rxp)[i] = (u8)readl(rx);
324 if (flags & SPI_XFER_END) {
325 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
326 omap3_spi_write_chconf(ds,chconf);
332 /*McSPI Transmit Receive Mode*/
333 int omap3_spi_txrx(struct spi_slave *slave, unsigned int len,
334 const void *txp, void *rxp, unsigned long flags)
336 struct omap3_spi_slave *ds = to_omap3_spi(slave);
338 int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
341 /*Enable SPI channel*/
342 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
344 /*set TRANSMIT-RECEIVE Mode*/
345 chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
346 chconf |= (ds->slave.wordlen - 1) << 7;
347 chconf |= OMAP3_MCSPI_CHCONF_FORCE;
348 omap3_spi_write_chconf(ds,chconf);
350 /*Shift in and out 1 byte at time*/
351 for (i=0; i < len; i++){
352 /* Write: wait for TX empty (TXS == 1)*/
353 start = get_timer(0);
354 while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
355 OMAP3_MCSPI_CHSTAT_TXS)) {
356 if (get_timer(start) > SPI_WAIT_TIMEOUT) {
357 printf("SPI TXS timed out, status=0x%08x\n",
358 readl(&ds->regs->channel[ds->slave.cs].chstat));
363 unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx;
364 if (ds->slave.wordlen > 16)
365 writel(((u32 *)txp)[i], tx);
366 else if (ds->slave.wordlen > 8)
367 writel(((u16 *)txp)[i], tx);
369 writel(((u8 *)txp)[i], tx);
371 /*Read: wait for RX containing data (RXS == 1)*/
372 start = get_timer(0);
373 while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
374 OMAP3_MCSPI_CHSTAT_RXS)) {
375 if (get_timer(start) > SPI_WAIT_TIMEOUT) {
376 printf("SPI RXS timed out, status=0x%08x\n",
377 readl(&ds->regs->channel[ds->slave.cs].chstat));
382 unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx;
383 if (ds->slave.wordlen > 16)
384 ((u32 *)rxp)[i] = readl(rx);
385 else if (ds->slave.wordlen > 8)
386 ((u16 *)rxp)[i] = (u16)readl(rx);
388 ((u8 *)rxp)[i] = (u8)readl(rx);
390 /* Disable the channel */
391 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
393 /*if transfer must be terminated disable the channel*/
394 if (flags & SPI_XFER_END) {
395 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
396 omap3_spi_write_chconf(ds,chconf);
402 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
403 const void *dout, void *din, unsigned long flags)
405 struct omap3_spi_slave *ds = to_omap3_spi(slave);
409 if (ds->slave.wordlen < 4 || ds->slave.wordlen > 32) {
410 printf("omap3_spi: invalid wordlen %d\n", ds->slave.wordlen);
414 if (bitlen % ds->slave.wordlen)
417 len = bitlen / ds->slave.wordlen;
419 if (bitlen == 0) { /* only change CS */
420 int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
422 if (flags & SPI_XFER_BEGIN) {
423 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
424 chconf |= OMAP3_MCSPI_CHCONF_FORCE;
425 omap3_spi_write_chconf(ds,chconf);
427 if (flags & SPI_XFER_END) {
428 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
429 omap3_spi_write_chconf(ds,chconf);
430 omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
434 if (dout != NULL && din != NULL)
435 ret = omap3_spi_txrx(slave, len, dout, din, flags);
436 else if (dout != NULL)
437 ret = omap3_spi_write(slave, len, dout, flags);
438 else if (din != NULL)
439 ret = omap3_spi_read(slave, len, din, flags);
444 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
449 void spi_cs_activate(struct spi_slave *slave)
453 void spi_cs_deactivate(struct spi_slave *slave)