1 // SPDX-License-Identifier: GPL-2.0+
3 * NXP FlexSPI(FSPI) controller driver.
5 * Copyright (c) 2019 Michael Walle <michael@walle.cc>
6 * Copyright (c) 2019 NXP
8 * This driver was originally ported from the linux kernel v5.4-rc3, which had
11 * FlexSPI is a flexsible SPI host controller which supports two SPI
12 * channels and up to 4 external devices. Each channel supports
13 * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
16 * FlexSPI controller is driven by the LUT(Look-up Table) registers
17 * LUT registers are a look-up-table for sequences of instructions.
18 * A valid sequence consists of four LUT registers.
19 * Maximum 32 LUT sequences can be programmed simultaneously.
21 * LUTs are being created at run-time based on the commands passed
22 * from the spi-mem framework, thus using single LUT index.
24 * Software triggered Flash read/write access by IP Bus.
26 * Memory mapped read access by AHB Bus.
28 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
31 * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
32 * Boris Brezillon <bbrezillon@kernel.org>
33 * Frieder Schrempf <frieder.schrempf@kontron.de>
43 #include <linux/bitops.h>
44 #include <linux/kernel.h>
45 #include <linux/sizes.h>
46 #include <linux/iopoll.h>
47 #include <linux/bug.h>
48 #include <linux/err.h>
51 * The driver only uses one single LUT entry, that is updated on
52 * each call of exec_op(). Index 0 is preset at boot with a basic
53 * read operation, so let's use the last entry (31).
57 /* Registers used by the driver */
58 #define FSPI_MCR0 0x00
59 #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
60 #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
61 #define FSPI_MCR0_LEARN_EN BIT(15)
62 #define FSPI_MCR0_SCRFRUN_EN BIT(14)
63 #define FSPI_MCR0_OCTCOMB_EN BIT(13)
64 #define FSPI_MCR0_DOZE_EN BIT(12)
65 #define FSPI_MCR0_HSEN BIT(11)
66 #define FSPI_MCR0_SERCLKDIV BIT(8)
67 #define FSPI_MCR0_ATDF_EN BIT(7)
68 #define FSPI_MCR0_ARDF_EN BIT(6)
69 #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
70 #define FSPI_MCR0_END_CFG(x) ((x) << 2)
71 #define FSPI_MCR0_MDIS BIT(1)
72 #define FSPI_MCR0_SWRST BIT(0)
74 #define FSPI_MCR1 0x04
75 #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
76 #define FSPI_MCR1_AHB_TIMEOUT(x) (x)
78 #define FSPI_MCR2 0x08
79 #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
80 #define FSPI_MCR2_SAMEDEVICEEN BIT(15)
81 #define FSPI_MCR2_CLRLRPHS BIT(14)
82 #define FSPI_MCR2_ABRDATSZ BIT(8)
83 #define FSPI_MCR2_ABRLEARN BIT(7)
84 #define FSPI_MCR2_ABR_READ BIT(6)
85 #define FSPI_MCR2_ABRWRITE BIT(5)
86 #define FSPI_MCR2_ABRDUMMY BIT(4)
87 #define FSPI_MCR2_ABR_MODE BIT(3)
88 #define FSPI_MCR2_ABRCADDR BIT(2)
89 #define FSPI_MCR2_ABRRADDR BIT(1)
90 #define FSPI_MCR2_ABR_CMD BIT(0)
92 #define FSPI_AHBCR 0x0c
93 #define FSPI_AHBCR_RDADDROPT BIT(6)
94 #define FSPI_AHBCR_PREF_EN BIT(5)
95 #define FSPI_AHBCR_BUFF_EN BIT(4)
96 #define FSPI_AHBCR_CACH_EN BIT(3)
97 #define FSPI_AHBCR_CLRTXBUF BIT(2)
98 #define FSPI_AHBCR_CLRRXBUF BIT(1)
99 #define FSPI_AHBCR_PAR_EN BIT(0)
101 #define FSPI_INTEN 0x10
102 #define FSPI_INTEN_SCLKSBWR BIT(9)
103 #define FSPI_INTEN_SCLKSBRD BIT(8)
104 #define FSPI_INTEN_DATALRNFL BIT(7)
105 #define FSPI_INTEN_IPTXWE BIT(6)
106 #define FSPI_INTEN_IPRXWA BIT(5)
107 #define FSPI_INTEN_AHBCMDERR BIT(4)
108 #define FSPI_INTEN_IPCMDERR BIT(3)
109 #define FSPI_INTEN_AHBCMDGE BIT(2)
110 #define FSPI_INTEN_IPCMDGE BIT(1)
111 #define FSPI_INTEN_IPCMDDONE BIT(0)
113 #define FSPI_INTR 0x14
114 #define FSPI_INTR_SCLKSBWR BIT(9)
115 #define FSPI_INTR_SCLKSBRD BIT(8)
116 #define FSPI_INTR_DATALRNFL BIT(7)
117 #define FSPI_INTR_IPTXWE BIT(6)
118 #define FSPI_INTR_IPRXWA BIT(5)
119 #define FSPI_INTR_AHBCMDERR BIT(4)
120 #define FSPI_INTR_IPCMDERR BIT(3)
121 #define FSPI_INTR_AHBCMDGE BIT(2)
122 #define FSPI_INTR_IPCMDGE BIT(1)
123 #define FSPI_INTR_IPCMDDONE BIT(0)
125 #define FSPI_LUTKEY 0x18
126 #define FSPI_LUTKEY_VALUE 0x5AF05AF0
128 #define FSPI_LCKCR 0x1C
130 #define FSPI_LCKER_LOCK 0x1
131 #define FSPI_LCKER_UNLOCK 0x2
133 #define FSPI_BUFXCR_INVALID_MSTRID 0xE
134 #define FSPI_AHBRX_BUF0CR0 0x20
135 #define FSPI_AHBRX_BUF1CR0 0x24
136 #define FSPI_AHBRX_BUF2CR0 0x28
137 #define FSPI_AHBRX_BUF3CR0 0x2C
138 #define FSPI_AHBRX_BUF4CR0 0x30
139 #define FSPI_AHBRX_BUF5CR0 0x34
140 #define FSPI_AHBRX_BUF6CR0 0x38
141 #define FSPI_AHBRX_BUF7CR0 0x3C
142 #define FSPI_AHBRXBUF0CR7_PREF BIT(31)
144 #define FSPI_AHBRX_BUF0CR1 0x40
145 #define FSPI_AHBRX_BUF1CR1 0x44
146 #define FSPI_AHBRX_BUF2CR1 0x48
147 #define FSPI_AHBRX_BUF3CR1 0x4C
148 #define FSPI_AHBRX_BUF4CR1 0x50
149 #define FSPI_AHBRX_BUF5CR1 0x54
150 #define FSPI_AHBRX_BUF6CR1 0x58
151 #define FSPI_AHBRX_BUF7CR1 0x5C
153 #define FSPI_FLSHA1CR0 0x60
154 #define FSPI_FLSHA2CR0 0x64
155 #define FSPI_FLSHB1CR0 0x68
156 #define FSPI_FLSHB2CR0 0x6C
157 #define FSPI_FLSHXCR0_SZ_KB 10
158 #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
160 #define FSPI_FLSHA1CR1 0x70
161 #define FSPI_FLSHA2CR1 0x74
162 #define FSPI_FLSHB1CR1 0x78
163 #define FSPI_FLSHB2CR1 0x7C
164 #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
165 #define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
166 #define FSPI_FLSHXCR1_WA BIT(10)
167 #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
168 #define FSPI_FLSHXCR1_TCSS(x) (x)
170 #define FSPI_FLSHA1CR2 0x80
171 #define FSPI_FLSHA2CR2 0x84
172 #define FSPI_FLSHB1CR2 0x88
173 #define FSPI_FLSHB2CR2 0x8C
174 #define FSPI_FLSHXCR2_CLRINSP BIT(24)
175 #define FSPI_FLSHXCR2_AWRWAIT BIT(16)
176 #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
177 #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
178 #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
179 #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
181 #define FSPI_IPCR0 0xA0
183 #define FSPI_IPCR1 0xA4
184 #define FSPI_IPCR1_IPAREN BIT(31)
185 #define FSPI_IPCR1_SEQNUM_SHIFT 24
186 #define FSPI_IPCR1_SEQID_SHIFT 16
187 #define FSPI_IPCR1_IDATSZ(x) (x)
189 #define FSPI_IPCMD 0xB0
190 #define FSPI_IPCMD_TRG BIT(0)
192 #define FSPI_DLPR 0xB4
194 #define FSPI_IPRXFCR 0xB8
195 #define FSPI_IPRXFCR_CLR BIT(0)
196 #define FSPI_IPRXFCR_DMA_EN BIT(1)
197 #define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
199 #define FSPI_IPTXFCR 0xBC
200 #define FSPI_IPTXFCR_CLR BIT(0)
201 #define FSPI_IPTXFCR_DMA_EN BIT(1)
202 #define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
204 #define FSPI_DLLACR 0xC0
205 #define FSPI_DLLACR_OVRDEN BIT(8)
207 #define FSPI_DLLBCR 0xC4
208 #define FSPI_DLLBCR_OVRDEN BIT(8)
210 #define FSPI_STS0 0xE0
211 #define FSPI_STS0_DLPHB(x) ((x) << 8)
212 #define FSPI_STS0_DLPHA(x) ((x) << 4)
213 #define FSPI_STS0_CMD_SRC(x) ((x) << 2)
214 #define FSPI_STS0_ARB_IDLE BIT(1)
215 #define FSPI_STS0_SEQ_IDLE BIT(0)
217 #define FSPI_STS1 0xE4
218 #define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
219 #define FSPI_STS1_IP_ERRID(x) ((x) << 16)
220 #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
221 #define FSPI_STS1_AHB_ERRID(x) (x)
223 #define FSPI_AHBSPNST 0xEC
224 #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
225 #define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
226 #define FSPI_AHBSPNST_ACTIVE BIT(0)
228 #define FSPI_IPRXFSTS 0xF0
229 #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
230 #define FSPI_IPRXFSTS_FILL(x) (x)
232 #define FSPI_IPTXFSTS 0xF4
233 #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
234 #define FSPI_IPTXFSTS_FILL(x) (x)
236 #define FSPI_RFDR 0x100
237 #define FSPI_TFDR 0x180
239 #define FSPI_LUT_BASE 0x200
240 #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
241 #define FSPI_LUT_REG(idx) \
242 (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
244 /* register map end */
246 /* Instruction set for the LUT register. */
247 #define LUT_STOP 0x00
249 #define LUT_ADDR 0x02
250 #define LUT_CADDR_SDR 0x03
251 #define LUT_MODE 0x04
252 #define LUT_MODE2 0x05
253 #define LUT_MODE4 0x06
254 #define LUT_MODE8 0x07
255 #define LUT_NXP_WRITE 0x08
256 #define LUT_NXP_READ 0x09
257 #define LUT_LEARN_SDR 0x0A
258 #define LUT_DATSZ_SDR 0x0B
259 #define LUT_DUMMY 0x0C
260 #define LUT_DUMMY_RWDS_SDR 0x0D
261 #define LUT_JMP_ON_CS 0x1F
262 #define LUT_CMD_DDR 0x21
263 #define LUT_ADDR_DDR 0x22
264 #define LUT_CADDR_DDR 0x23
265 #define LUT_MODE_DDR 0x24
266 #define LUT_MODE2_DDR 0x25
267 #define LUT_MODE4_DDR 0x26
268 #define LUT_MODE8_DDR 0x27
269 #define LUT_WRITE_DDR 0x28
270 #define LUT_READ_DDR 0x29
271 #define LUT_LEARN_DDR 0x2A
272 #define LUT_DATSZ_DDR 0x2B
273 #define LUT_DUMMY_DDR 0x2C
274 #define LUT_DUMMY_RWDS_DDR 0x2D
277 * Calculate number of required PAD bits for LUT register.
279 * The pad stands for the number of IO lines [0:7].
280 * For example, the octal read needs eight IO lines,
281 * so you should use LUT_PAD(8). This macro
282 * returns 3 i.e. use eight (2^3) IP lines for read.
284 #define LUT_PAD(x) (fls(x) - 1)
287 * Macro for constructing the LUT entries with the following
290 * ---------------------------------------------------
291 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
292 * ---------------------------------------------------
295 #define INSTR_SHIFT 10
296 #define OPRND_SHIFT 16
298 /* Macros for constructing the LUT register. */
299 #define LUT_DEF(idx, ins, pad, opr) \
300 ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
301 (opr)) << (((idx) % 2) * OPRND_SHIFT))
303 #define POLL_TOUT 5000
304 #define NXP_FSPI_MAX_CHIPSELECT 4
306 struct nxp_fspi_devtype_data {
309 unsigned int ahb_buf_size;
314 static const struct nxp_fspi_devtype_data lx2160a_data = {
315 .rxfifo = SZ_512, /* (64 * 64 bits) */
316 .txfifo = SZ_1K, /* (128 * 64 bits) */
317 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
319 .little_endian = true, /* little-endian */
324 void __iomem *iobase;
325 void __iomem *ahb_addr;
328 struct clk clk, clk_en;
329 const struct nxp_fspi_devtype_data *devtype_data;
333 * R/W functions for big- or little-endian registers:
334 * The FSPI controller's endianness is independent of
335 * the CPU core's endianness. So far, although the CPU
336 * core is little-endian the FSPI controller can use
337 * big-endian or little-endian.
339 static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
341 if (f->devtype_data->little_endian)
347 static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
349 if (f->devtype_data->little_endian)
350 return in_le32(addr);
352 return in_be32(addr);
355 static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
368 static bool nxp_fspi_supports_op(struct spi_slave *slave,
369 const struct spi_mem_op *op)
375 bus = slave->dev->parent;
376 f = dev_get_priv(bus);
378 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
381 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
383 if (op->dummy.nbytes)
384 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
387 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
393 * The number of address bytes should be equal to or less than 4 bytes.
395 if (op->addr.nbytes > 4)
399 * If requested address value is greater than controller assigned
400 * memory mapped space, return error as it didn't fit in the range
401 * of assigned address space.
403 if (op->addr.val >= f->memmap_phy_size)
406 /* Max 64 dummy clock cycles supported */
407 if (op->dummy.buswidth &&
408 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
411 /* Max data length, check controller limits and alignment */
412 if (op->data.dir == SPI_MEM_DATA_IN &&
413 (op->data.nbytes > f->devtype_data->ahb_buf_size ||
414 (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
415 !IS_ALIGNED(op->data.nbytes, 8))))
418 if (op->data.dir == SPI_MEM_DATA_OUT &&
419 op->data.nbytes > f->devtype_data->txfifo)
425 /* Instead of busy looping invoke readl_poll_sleep_timeout functionality. */
426 static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
427 u32 mask, u32 delay_us,
428 u32 timeout_us, bool c)
432 if (!f->devtype_data->little_endian)
433 mask = (u32)cpu_to_be32(mask);
436 return readl_poll_sleep_timeout(base, reg, (reg & mask),
437 delay_us, timeout_us);
439 return readl_poll_sleep_timeout(base, reg, !(reg & mask),
440 delay_us, timeout_us);
444 * If the slave device content being changed by Write/Erase, need to
445 * invalidate the AHB buffer. This can be achieved by doing the reset
446 * of controller after setting MCR0[SWRESET] bit.
448 static inline void nxp_fspi_invalid(struct nxp_fspi *f)
453 reg = fspi_readl(f, f->iobase + FSPI_MCR0);
454 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
456 /* w1c register, wait unit clear */
457 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
458 FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
462 static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
463 const struct spi_mem_op *op)
465 void __iomem *base = f->iobase;
470 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
474 if (op->addr.nbytes) {
475 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
476 LUT_PAD(op->addr.buswidth),
477 op->addr.nbytes * 8);
481 /* dummy bytes, if needed */
482 if (op->dummy.nbytes) {
483 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
485 * Due to FlexSPI controller limitation number of PAD for dummy
486 * buswidth needs to be programmed as equal to data buswidth.
488 LUT_PAD(op->data.buswidth),
489 op->dummy.nbytes * 8 /
494 /* read/write data bytes */
495 if (op->data.nbytes) {
496 lutval[lutidx / 2] |= LUT_DEF(lutidx,
497 op->data.dir == SPI_MEM_DATA_IN ?
498 LUT_NXP_READ : LUT_NXP_WRITE,
499 LUT_PAD(op->data.buswidth),
504 /* stop condition. */
505 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
508 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
509 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
512 for (i = 0; i < ARRAY_SIZE(lutval); i++)
513 fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
515 dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
516 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
519 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
520 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
523 #if CONFIG_IS_ENABLED(CONFIG_CLK)
524 static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
528 ret = clk_enable(&f->clk_en);
532 ret = clk_enable(&f->clk);
534 clk_disable(&f->clk_en);
541 static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
543 clk_disable(&f->clk);
544 clk_disable(&f->clk_en);
549 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
550 * register and start base address of the slave device.
553 * -------- <-- FLSHB2CR0
556 * B2 start address --> -------- <-- FLSHB1CR0
559 * B1 start address --> -------- <-- FLSHA2CR0
562 * A2 start address --> -------- <-- FLSHA1CR0
565 * A1 start address --> -------- (Lower address)
568 * Start base address defines the starting address range for given CS and
569 * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
571 * But, different targets are having different combinations of number of CS,
572 * some targets only have single CS or two CS covering controller's full
573 * memory mapped space area.
574 * Thus, implementation is being done as independent of the size and number
575 * of the connected slave device.
576 * Assign controller memory mapped space size as the size to the connected
578 * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
579 * chip-select Flash configuration register.
581 * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
582 * memory mapped size of the controller.
583 * Value for rest of the CS FLSHxxCR0 register would be zero.
586 static void nxp_fspi_select_mem(struct nxp_fspi *f, int chip_select)
590 /* Reset FLSHxxCR0 registers */
591 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
592 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
593 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
594 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
596 /* Assign controller memory mapped space as size, KBytes, of flash. */
597 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
599 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
602 dev_dbg(f->dev, "Slave device [CS:%x] selected\n", chip_select);
605 static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
607 u32 len = op->data.nbytes;
609 /* Read out the data directly from the AHB buffer. */
610 memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len);
613 static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
614 const struct spi_mem_op *op)
616 void __iomem *base = f->iobase;
618 u8 *buf = (u8 *)op->data.buf.out;
620 /* clear the TX FIFO. */
621 fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
624 * Default value of water mark level is 8 bytes, hence in single
625 * write request controller can write max 8 bytes of data.
628 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
629 /* Wait for TXFIFO empty */
630 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
635 fspi_writel(f, *(u32 *)(buf + i), base + FSPI_TFDR);
636 fspi_writel(f, *(u32 *)(buf + i + 4), base + FSPI_TFDR + 4);
637 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
640 if (i < op->data.nbytes) {
643 /* Wait for TXFIFO empty */
644 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
649 for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) {
650 memcpy(&data, buf + i + j, 4);
651 fspi_writel(f, data, base + FSPI_TFDR + j);
653 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
657 static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
658 const struct spi_mem_op *op)
660 void __iomem *base = f->iobase;
662 int len = op->data.nbytes;
663 u8 *buf = (u8 *)op->data.buf.in;
666 * Default value of water mark level is 8 bytes, hence in single
667 * read request controller can read max 8 bytes of data.
669 for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
670 /* Wait for RXFIFO available */
671 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
676 *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
677 *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
678 /* move the FIFO pointer */
679 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
686 buf = op->data.buf.in + i;
687 /* Wait for RXFIFO available */
688 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
693 len = op->data.nbytes - i;
694 for (j = 0; j < op->data.nbytes - i; j += 4) {
695 tmp = fspi_readl(f, base + FSPI_RFDR + j);
697 memcpy(buf + j, &tmp, size);
702 /* invalid the RXFIFO */
703 fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
704 /* move the FIFO pointer */
705 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
708 static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
710 void __iomem *base = f->iobase;
715 reg = fspi_readl(f, base + FSPI_IPRXFCR);
716 /* invalid RXFIFO first */
717 reg &= ~FSPI_IPRXFCR_DMA_EN;
718 reg = reg | FSPI_IPRXFCR_CLR;
719 fspi_writel(f, reg, base + FSPI_IPRXFCR);
721 fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
723 * Always start the sequence at the same index since we update
724 * the LUT at each exec_op() call. And also specify the DATA
725 * length, since it's has not been specified in the LUT.
727 fspi_writel(f, op->data.nbytes |
728 (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
729 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
732 /* Trigger the LUT now. */
733 fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
735 /* Wait for the completion. */
736 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
737 FSPI_STS0_ARB_IDLE, 1, 1000 * 1000, true);
739 /* Invoke IP data read, if request is of data read. */
740 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
741 nxp_fspi_read_rxfifo(f, op);
746 static int nxp_fspi_exec_op(struct spi_slave *slave,
747 const struct spi_mem_op *op)
753 bus = slave->dev->parent;
754 f = dev_get_priv(bus);
756 /* Wait for controller being ready. */
757 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
758 FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
761 nxp_fspi_prepare_lut(f, op);
763 * If we have large chunks of data, we read them through the AHB bus
764 * by accessing the mapped memory. In all other cases we use
765 * IP commands to access the flash.
767 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
768 op->data.dir == SPI_MEM_DATA_IN) {
769 nxp_fspi_read_ahb(f, op);
771 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
772 nxp_fspi_fill_txfifo(f, op);
774 err = nxp_fspi_do_op(f, op);
777 /* Invalidate the data in the AHB buffer. */
783 static int nxp_fspi_adjust_op_size(struct spi_slave *slave,
784 struct spi_mem_op *op)
789 bus = slave->dev->parent;
790 f = dev_get_priv(bus);
792 if (op->data.dir == SPI_MEM_DATA_OUT) {
793 if (op->data.nbytes > f->devtype_data->txfifo)
794 op->data.nbytes = f->devtype_data->txfifo;
796 if (op->data.nbytes > f->devtype_data->ahb_buf_size)
797 op->data.nbytes = f->devtype_data->ahb_buf_size;
798 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
799 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
805 static int nxp_fspi_default_setup(struct nxp_fspi *f)
807 void __iomem *base = f->iobase;
811 #if CONFIG_IS_ENABLED(CONFIG_CLK)
812 /* disable and unprepare clock to avoid glitch pass to controller */
813 nxp_fspi_clk_disable_unprep(f);
815 /* the default frequency, we will change it later if necessary. */
816 ret = clk_set_rate(&f->clk, 20000000);
820 ret = nxp_fspi_clk_prep_enable(f);
825 /* Reset the module */
826 /* w1c register, wait unit clear */
827 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
828 FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
831 /* Disable the module */
832 fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
834 /* Reset the DLL register to default value */
835 fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
836 fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
839 fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF),
843 * Disable same device enable bit and configure all slave devices
846 reg = fspi_readl(f, f->iobase + FSPI_MCR2);
847 reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
848 fspi_writel(f, reg, base + FSPI_MCR2);
850 /* AHB configuration for access buffer 0~7. */
851 for (i = 0; i < 7; i++)
852 fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
855 * Set ADATSZ with the maximum AHB buffer size to improve the read
858 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
859 FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0);
861 /* prefetch and no start address alignment limitation */
862 fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
865 /* AHB Read - Set lut sequence ID for all CS. */
866 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
867 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
868 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
869 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
874 static int nxp_fspi_probe(struct udevice *bus)
876 struct nxp_fspi *f = dev_get_priv(bus);
879 (struct nxp_fspi_devtype_data *)dev_get_driver_data(bus);
880 nxp_fspi_default_setup(f);
885 static int nxp_fspi_claim_bus(struct udevice *dev)
889 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
892 f = dev_get_priv(bus);
894 nxp_fspi_select_mem(f, slave_plat->cs);
899 static int nxp_fspi_set_speed(struct udevice *bus, uint speed)
901 #if CONFIG_IS_ENABLED(CONFIG_CLK)
902 struct nxp_fspi *f = dev_get_priv(bus);
905 nxp_fspi_clk_disable_unprep(f);
907 ret = clk_set_rate(&f->clk, speed);
911 ret = nxp_fspi_clk_prep_enable(f);
918 static int nxp_fspi_set_mode(struct udevice *bus, uint mode)
924 static int nxp_fspi_ofdata_to_platdata(struct udevice *bus)
926 struct nxp_fspi *f = dev_get_priv(bus);
927 #if CONFIG_IS_ENABLED(CONFIG_CLK)
932 fdt_addr_t iobase_size;
938 iobase = devfdt_get_addr_size_name(bus, "fspi_base", &iobase_size);
939 if (iobase == FDT_ADDR_T_NONE) {
940 dev_err(bus, "fspi_base regs missing\n");
943 f->iobase = map_physmem(iobase, iobase_size, MAP_NOCACHE);
945 ahb_addr = devfdt_get_addr_size_name(bus, "fspi_mmap", &ahb_size);
946 if (ahb_addr == FDT_ADDR_T_NONE) {
947 dev_err(bus, "fspi_mmap regs missing\n");
950 f->ahb_addr = map_physmem(ahb_addr, ahb_size, MAP_NOCACHE);
951 f->memmap_phy_size = ahb_size;
953 #if CONFIG_IS_ENABLED(CONFIG_CLK)
954 ret = clk_get_by_name(bus, "fspi_en", &f->clk_en);
956 dev_err(bus, "failed to get fspi_en clock\n");
960 ret = clk_get_by_name(bus, "fspi", &f->clk);
962 dev_err(bus, "failed to get fspi clock\n");
967 dev_dbg(bus, "iobase=<0x%llx>, ahb_addr=<0x%llx>\n", iobase, ahb_addr);
972 static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
973 .adjust_op_size = nxp_fspi_adjust_op_size,
974 .supports_op = nxp_fspi_supports_op,
975 .exec_op = nxp_fspi_exec_op,
978 static const struct dm_spi_ops nxp_fspi_ops = {
979 .claim_bus = nxp_fspi_claim_bus,
980 .set_speed = nxp_fspi_set_speed,
981 .set_mode = nxp_fspi_set_mode,
982 .mem_ops = &nxp_fspi_mem_ops,
985 static const struct udevice_id nxp_fspi_ids[] = {
986 { .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
990 U_BOOT_DRIVER(nxp_fspi) = {
993 .of_match = nxp_fspi_ids,
994 .ops = &nxp_fspi_ops,
995 .ofdata_to_platdata = nxp_fspi_ofdata_to_platdata,
996 .priv_auto_alloc_size = sizeof(struct nxp_fspi),
997 .probe = nxp_fspi_probe,