2 * Freescale i.MX28 SPI driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * NOTE: This driver only supports the SPI-controller chipselects,
23 * GPIO driven chipselects are not supported.
29 #include <asm/errno.h>
31 #include <asm/arch/clock.h>
32 #include <asm/arch/imx-regs.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/arch/dma.h>
36 #define MXS_SPI_MAX_TIMEOUT 1000000
37 #define MXS_SPI_PORT_OFFSET 0x2000
38 #define MXS_SSP_CHIPSELECT_MASK 0x00300000
39 #define MXS_SSP_CHIPSELECT_SHIFT 20
41 #define MXSSSP_SMALL_TRANSFER 512
44 * CONFIG_MXS_SPI_DMA_ENABLE: Experimental mixed PIO/DMA support for MXS SPI
45 * host. Use with utmost caution!
47 * Enabling this is not yet recommended since this
48 * still doesn't support transfers to/from unaligned
49 * addresses. Therefore this driver will not work
50 * for example with saving environment. This is
51 * caused by DMA alignment constraints on MXS.
54 struct mxs_spi_slave {
55 struct spi_slave slave;
58 struct mxs_ssp_regs *regs;
61 static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
63 return container_of(slave, struct mxs_spi_slave, slave);
70 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
72 /* MXS SPI: 4 ports and 3 chip selects maximum */
73 if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
79 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
80 unsigned int max_hz, unsigned int mode)
82 struct mxs_spi_slave *mxs_slave;
83 struct mxs_ssp_regs *ssp_regs;
86 if (!spi_cs_is_valid(bus, cs)) {
87 printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
91 mxs_slave = calloc(sizeof(struct mxs_spi_slave), 1);
95 if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
98 mxs_slave->slave.bus = bus;
99 mxs_slave->slave.cs = cs;
100 mxs_slave->max_khz = max_hz / 1000;
101 mxs_slave->mode = mode;
102 mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
103 ssp_regs = mxs_slave->regs;
105 reg = readl(&ssp_regs->hw_ssp_ctrl0);
106 reg &= ~(MXS_SSP_CHIPSELECT_MASK);
107 reg |= cs << MXS_SSP_CHIPSELECT_SHIFT;
109 writel(reg, &ssp_regs->hw_ssp_ctrl0);
110 return &mxs_slave->slave;
117 void spi_free_slave(struct spi_slave *slave)
119 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
123 int spi_claim_bus(struct spi_slave *slave)
125 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
126 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
129 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
131 writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
133 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
134 reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
135 reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
136 writel(reg, &ssp_regs->hw_ssp_ctrl1);
138 writel(0, &ssp_regs->hw_ssp_cmd0);
140 mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
145 void spi_release_bus(struct spi_slave *slave)
149 static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
151 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
152 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
155 static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
157 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
158 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
161 static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
162 char *data, int length, int write, unsigned long flags)
164 struct mxs_ssp_regs *ssp_regs = slave->regs;
166 if (flags & SPI_XFER_BEGIN)
167 mxs_spi_start_xfer(ssp_regs);
170 /* We transfer 1 byte */
171 #if defined(CONFIG_MX23)
172 writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
173 writel(1, &ssp_regs->hw_ssp_ctrl0_set);
174 #elif defined(CONFIG_MX28)
175 writel(1, &ssp_regs->hw_ssp_xfer_size);
178 if ((flags & SPI_XFER_END) && !length)
179 mxs_spi_end_xfer(ssp_regs);
182 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
184 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
186 writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
188 if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
189 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
190 printf("MXS SPI: Timeout waiting for start\n");
195 writel(*data++, &ssp_regs->hw_ssp_data);
197 writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
200 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
201 SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
202 printf("MXS SPI: Timeout waiting for data\n");
206 *data = readl(&ssp_regs->hw_ssp_data);
210 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
211 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
212 printf("MXS SPI: Timeout waiting for finish\n");
220 static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
221 char *data, int length, int write, unsigned long flags)
223 const int xfer_max_sz = 0xff00;
224 const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
225 struct mxs_ssp_regs *ssp_regs = slave->regs;
226 struct mxs_dma_desc *dp;
228 uint32_t cache_data_count;
229 const uint32_t dstart = (uint32_t)data;
234 #if defined(CONFIG_MX23)
235 const int mxs_spi_pio_words = 1;
236 #elif defined(CONFIG_MX28)
237 const int mxs_spi_pio_words = 4;
240 ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
242 memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
244 ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
245 ctrl0 |= SSP_CTRL0_DATA_XFER;
247 if (flags & SPI_XFER_BEGIN)
248 ctrl0 |= SSP_CTRL0_LOCK_CS;
250 ctrl0 |= SSP_CTRL0_READ;
252 if (length % ARCH_DMA_MINALIGN)
253 cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
255 cache_data_count = length;
257 /* Flush data to DRAM so DMA can pick them up */
259 flush_dcache_range(dstart, dstart + cache_data_count);
261 /* Invalidate the area, so no writeback into the RAM races with DMA */
262 invalidate_dcache_range(dstart, dstart + cache_data_count);
264 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
268 dp->address = (dma_addr_t)dp;
269 dp->cmd.address = (dma_addr_t)data;
272 * This is correct, even though it does indeed look insane.
273 * I hereby have to, wholeheartedly, thank Freescale Inc.,
274 * for always inventing insane hardware and keeping me busy
278 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
280 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
283 * The DMA controller can transfer large chunks (64kB) at
284 * time by setting the transfer length to 0. Setting tl to
285 * 0x10000 will overflow below and make .data contain 0.
286 * Otherwise, 0xff00 is the transfer maximum.
288 if (length >= 0x10000)
291 tl = min(length, xfer_max_sz);
294 ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
295 (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
296 MXS_DMA_DESC_HALT_ON_TERMINATE |
297 MXS_DMA_DESC_TERMINATE_FLUSH;
303 dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
305 if (flags & SPI_XFER_END) {
306 ctrl0 &= ~SSP_CTRL0_LOCK_CS;
307 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
312 * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
313 * case of MX28, write only CTRL0 in case of MX23 due
314 * to the difference in register layout. It is utterly
315 * essential that the XFER_SIZE register is written on
316 * a per-descriptor basis with the same size as is the
319 dp->cmd.pio_words[0] = ctrl0;
321 dp->cmd.pio_words[1] = 0;
322 dp->cmd.pio_words[2] = 0;
323 dp->cmd.pio_words[3] = tl;
326 mxs_dma_desc_append(dmach, dp);
331 if (mxs_dma_go(dmach))
334 /* The data arrived into DRAM, invalidate cache over them */
336 invalidate_dcache_range(dstart, dstart + cache_data_count);
341 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
342 const void *dout, void *din, unsigned long flags)
344 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
345 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
346 int len = bitlen / 8;
351 #ifdef CONFIG_MXS_SPI_DMA_ENABLE
358 if (flags & SPI_XFER_END) {
359 din = (void *)&dummy;
365 /* Half-duplex only */
381 * Check for alignment, if the buffer is aligned, do DMA transfer,
382 * PIO otherwise. This is a temporary workaround until proper bounce
383 * buffer is in place.
386 if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
388 if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
392 if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
393 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
394 return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
396 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
397 return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);