1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX28 SPI driver
5 * Copyright (C) 2019 DENX Software Engineering
6 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
8 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
9 * on behalf of DENX Software Engineering GmbH
11 * NOTE: This driver only supports the SPI-controller chipselects,
12 * GPIO driven chipselects are not supported.
19 #include <linux/errno.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/imx-regs.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/mach-imx/dma.h>
26 #define MXS_SPI_MAX_TIMEOUT 1000000
27 #define MXS_SPI_PORT_OFFSET 0x2000
28 #define MXS_SSP_CHIPSELECT_MASK 0x00300000
29 #define MXS_SSP_CHIPSELECT_SHIFT 20
31 #define MXSSSP_SMALL_TRANSFER 512
33 static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
35 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
36 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
39 static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
41 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
42 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
45 #if !CONFIG_IS_ENABLED(DM_SPI)
46 struct mxs_spi_slave {
47 struct spi_slave slave;
50 struct mxs_ssp_regs *regs;
53 static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
55 return container_of(slave, struct mxs_spi_slave, slave);
60 struct mxs_spi_platdata {
61 s32 frequency; /* Default clock frequency, -1 for none */
62 fdt_addr_t base; /* SPI IP block base address */
63 int num_cs; /* Number of CSes supported */
64 int dma_id; /* ID of the DMA channel */
65 int clk_id; /* ID of the SSP clock */
69 struct mxs_ssp_regs *regs;
70 unsigned int dma_channel;
71 unsigned int max_freq;
77 #if !CONFIG_IS_ENABLED(DM_SPI)
78 static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
79 char *data, int length, int write, unsigned long flags)
81 struct mxs_ssp_regs *ssp_regs = slave->regs;
83 static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
84 char *data, int length, int write,
87 struct mxs_ssp_regs *ssp_regs = priv->regs;
90 if (flags & SPI_XFER_BEGIN)
91 mxs_spi_start_xfer(ssp_regs);
94 /* We transfer 1 byte */
95 #if defined(CONFIG_MX23)
96 writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
97 writel(1, &ssp_regs->hw_ssp_ctrl0_set);
98 #elif defined(CONFIG_MX28)
99 writel(1, &ssp_regs->hw_ssp_xfer_size);
102 if ((flags & SPI_XFER_END) && !length)
103 mxs_spi_end_xfer(ssp_regs);
106 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
108 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
110 writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
112 if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
113 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
114 printf("MXS SPI: Timeout waiting for start\n");
119 writel(*data++, &ssp_regs->hw_ssp_data);
121 writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
124 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
125 SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
126 printf("MXS SPI: Timeout waiting for data\n");
130 *data = readl(&ssp_regs->hw_ssp_data);
134 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
135 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
136 printf("MXS SPI: Timeout waiting for finish\n");
144 #if !CONFIG_IS_ENABLED(DM_SPI)
145 static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
146 char *data, int length, int write, unsigned long flags)
148 struct mxs_ssp_regs *ssp_regs = slave->regs;
150 static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv,
151 char *data, int length, int write,
153 { struct mxs_ssp_regs *ssp_regs = priv->regs;
155 const int xfer_max_sz = 0xff00;
156 const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
157 struct mxs_dma_desc *dp;
159 uint32_t cache_data_count;
160 const uint32_t dstart = (uint32_t)data;
165 #if defined(CONFIG_MX23)
166 const int mxs_spi_pio_words = 1;
167 #elif defined(CONFIG_MX28)
168 const int mxs_spi_pio_words = 4;
171 ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
173 memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
175 ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
176 ctrl0 |= SSP_CTRL0_DATA_XFER;
178 if (flags & SPI_XFER_BEGIN)
179 ctrl0 |= SSP_CTRL0_LOCK_CS;
181 ctrl0 |= SSP_CTRL0_READ;
183 if (length % ARCH_DMA_MINALIGN)
184 cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
186 cache_data_count = length;
188 /* Flush data to DRAM so DMA can pick them up */
190 flush_dcache_range(dstart, dstart + cache_data_count);
192 /* Invalidate the area, so no writeback into the RAM races with DMA */
193 invalidate_dcache_range(dstart, dstart + cache_data_count);
195 #if !CONFIG_IS_ENABLED(DM_SPI)
196 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
198 dmach = priv->dma_channel;
203 dp->address = (dma_addr_t)dp;
204 dp->cmd.address = (dma_addr_t)data;
207 * This is correct, even though it does indeed look insane.
208 * I hereby have to, wholeheartedly, thank Freescale Inc.,
209 * for always inventing insane hardware and keeping me busy
213 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
215 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
218 * The DMA controller can transfer large chunks (64kB) at
219 * time by setting the transfer length to 0. Setting tl to
220 * 0x10000 will overflow below and make .data contain 0.
221 * Otherwise, 0xff00 is the transfer maximum.
223 if (length >= 0x10000)
226 tl = min(length, xfer_max_sz);
229 ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
230 (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
231 MXS_DMA_DESC_HALT_ON_TERMINATE |
232 MXS_DMA_DESC_TERMINATE_FLUSH;
238 dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
240 if (flags & SPI_XFER_END) {
241 ctrl0 &= ~SSP_CTRL0_LOCK_CS;
242 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
247 * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
248 * case of MX28, write only CTRL0 in case of MX23 due
249 * to the difference in register layout. It is utterly
250 * essential that the XFER_SIZE register is written on
251 * a per-descriptor basis with the same size as is the
254 dp->cmd.pio_words[0] = ctrl0;
256 dp->cmd.pio_words[1] = 0;
257 dp->cmd.pio_words[2] = 0;
258 dp->cmd.pio_words[3] = tl;
261 mxs_dma_desc_append(dmach, dp);
266 if (mxs_dma_go(dmach))
269 /* The data arrived into DRAM, invalidate cache over them */
271 invalidate_dcache_range(dstart, dstart + cache_data_count);
276 #if !CONFIG_IS_ENABLED(DM_SPI)
277 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
278 const void *dout, void *din, unsigned long flags)
280 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
281 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
283 int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen,
284 const void *dout, void *din, unsigned long flags)
286 struct udevice *bus = dev_get_parent(dev);
287 struct mxs_spi_priv *priv = dev_get_priv(bus);
288 struct mxs_ssp_regs *ssp_regs = priv->regs;
290 int len = bitlen / 8;
297 if (flags & SPI_XFER_END) {
298 din = (void *)&dummy;
304 /* Half-duplex only */
320 * Check for alignment, if the buffer is aligned, do DMA transfer,
321 * PIO otherwise. This is a temporary workaround until proper bounce
322 * buffer is in place.
325 if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
327 if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
331 if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
332 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
333 #if !CONFIG_IS_ENABLED(DM_SPI)
334 return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
336 return mxs_spi_xfer_pio(priv, data, len, write, flags);
339 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
340 #if !CONFIG_IS_ENABLED(DM_SPI)
341 return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
343 return mxs_spi_xfer_dma(priv, data, len, write, flags);
348 #if !CONFIG_IS_ENABLED(DM_SPI)
349 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
351 /* MXS SPI: 4 ports and 3 chip selects maximum */
352 if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
358 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
359 unsigned int max_hz, unsigned int mode)
361 struct mxs_spi_slave *mxs_slave;
363 if (!spi_cs_is_valid(bus, cs)) {
364 printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
368 mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
372 if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
375 mxs_slave->max_khz = max_hz / 1000;
376 mxs_slave->mode = mode;
377 mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
379 return &mxs_slave->slave;
386 void spi_free_slave(struct spi_slave *slave)
388 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
393 int spi_claim_bus(struct spi_slave *slave)
395 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
396 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
399 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
401 writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
402 SSP_CTRL0_BUS_WIDTH_ONE_BIT,
403 &ssp_regs->hw_ssp_ctrl0);
405 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
406 reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
407 reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
408 writel(reg, &ssp_regs->hw_ssp_ctrl1);
410 writel(0, &ssp_regs->hw_ssp_cmd0);
412 mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
417 void spi_release_bus(struct spi_slave *slave)
421 #else /* CONFIG_DM_SPI */
422 /* Base numbers of i.MX2[38] clk for ssp0 IP block */
423 #define MXS_SSP_IMX23_CLKID_SSP0 33
424 #define MXS_SSP_IMX28_CLKID_SSP0 46
426 static int mxs_spi_probe(struct udevice *bus)
428 struct mxs_spi_platdata *plat = dev_get_platdata(bus);
429 struct mxs_spi_priv *priv = dev_get_priv(bus);
432 debug("%s: probe\n", __func__);
433 priv->regs = (struct mxs_ssp_regs *)plat->base;
434 priv->max_freq = plat->frequency;
436 priv->dma_channel = plat->dma_id;
437 priv->clk_id = plat->clk_id;
439 ret = mxs_dma_init_channel(priv->dma_channel);
441 printf("%s: DMA init channel error %d\n", __func__, ret);
448 static int mxs_spi_claim_bus(struct udevice *dev)
450 struct udevice *bus = dev_get_parent(dev);
451 struct mxs_spi_priv *priv = dev_get_priv(bus);
452 struct mxs_ssp_regs *ssp_regs = priv->regs;
453 int cs = spi_chip_select(dev);
456 * i.MX28 supports up to 3 CS (SSn0, SSn1, SSn2)
457 * To set them it uses following tuple (WAIT_FOR_IRQ,WAIT_FOR_CMD),
460 * WAIT_FOR_IRQ is bit 21 of HW_SSP_CTRL0
461 * WAIT_FOR_CMD is bit 20 (#defined as MXS_SSP_CHIPSELECT_SHIFT here) of
465 * SSn2 b10 (which require setting WAIT_FOR_IRQ)
467 * However, for now i.MX28 SPI driver will support up till 2 CSes
471 /* Ungate SSP clock and set active CS */
472 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
473 BIT(MXS_SSP_CHIPSELECT_SHIFT) |
474 SSP_CTRL0_CLKGATE, (cs << MXS_SSP_CHIPSELECT_SHIFT));
479 static int mxs_spi_release_bus(struct udevice *dev)
481 struct udevice *bus = dev_get_parent(dev);
482 struct mxs_spi_priv *priv = dev_get_priv(bus);
483 struct mxs_ssp_regs *ssp_regs = priv->regs;
486 setbits_le32(&ssp_regs->hw_ssp_ctrl0, SSP_CTRL0_CLKGATE);
491 static int mxs_spi_set_speed(struct udevice *bus, uint speed)
493 struct mxs_spi_priv *priv = dev_get_priv(bus);
495 int clkid = priv->clk_id - MXS_SSP_IMX28_CLKID_SSP0;
496 #else /* CONFIG_MX23 */
497 int clkid = priv->clk_id - MXS_SSP_IMX23_CLKID_SSP0;
499 if (speed > priv->max_freq)
500 speed = priv->max_freq;
502 debug("%s speed: %u [Hz] clkid: %d\n", __func__, speed, clkid);
503 mxs_set_ssp_busclock(clkid, speed / 1000);
508 static int mxs_spi_set_mode(struct udevice *bus, uint mode)
510 struct mxs_spi_priv *priv = dev_get_priv(bus);
511 struct mxs_ssp_regs *ssp_regs = priv->regs;
515 debug("%s: mode 0x%x\n", __func__, mode);
517 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
518 reg |= (priv->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
519 reg |= (priv->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
520 writel(reg, &ssp_regs->hw_ssp_ctrl1);
522 /* Single bit SPI support */
523 writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
528 static const struct dm_spi_ops mxs_spi_ops = {
529 .claim_bus = mxs_spi_claim_bus,
530 .release_bus = mxs_spi_release_bus,
531 .xfer = mxs_spi_xfer,
532 .set_speed = mxs_spi_set_speed,
533 .set_mode = mxs_spi_set_mode,
535 * cs_info is not needed, since we require all chip selects to be
536 * in the device tree explicitly
540 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
541 static int mxs_ofdata_to_platdata(struct udevice *bus)
543 struct mxs_spi_platdata *plat = bus->platdata;
547 plat->base = dev_read_addr(bus);
549 dev_read_u32_default(bus, "spi-max-frequency", 40000000);
550 plat->num_cs = dev_read_u32_default(bus, "num-cs", 2);
552 ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
554 printf("%s: Reading 'dmas' property failed!\n", __func__);
557 plat->dma_id = prop[1];
559 ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
561 printf("%s: Reading 'clocks' property failed!\n", __func__);
564 plat->clk_id = prop[1];
566 debug("%s: base=0x%x, max-frequency=%d num-cs=%d dma_id=%d clk_id=%d\n",
567 __func__, (uint)plat->base, plat->frequency, plat->num_cs,
568 plat->dma_id, plat->clk_id);
574 static const struct udevice_id mxs_spi_ids[] = {
575 { .compatible = "fsl,imx23-spi" },
576 { .compatible = "fsl,imx28-spi" },
580 U_BOOT_DRIVER(mxs_spi) = {
583 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
584 .of_match = mxs_spi_ids,
585 .ofdata_to_platdata = mxs_ofdata_to_platdata,
587 .platdata_auto_alloc_size = sizeof(struct mxs_spi_platdata),
589 .priv_auto_alloc_size = sizeof(struct mxs_spi_priv),
590 .probe = mxs_spi_probe,