1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX28 SPI driver
5 * Copyright (C) 2019 DENX Software Engineering
6 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
8 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
9 * on behalf of DENX Software Engineering GmbH
11 * NOTE: This driver only supports the SPI-controller chipselects,
12 * GPIO driven chipselects are not supported.
19 #include <linux/errno.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/imx-regs.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/mach-imx/dma.h>
26 #define MXS_SPI_MAX_TIMEOUT 1000000
27 #define MXS_SPI_PORT_OFFSET 0x2000
28 #define MXS_SSP_CHIPSELECT_MASK 0x00300000
29 #define MXS_SSP_CHIPSELECT_SHIFT 20
31 #define MXSSSP_SMALL_TRANSFER 512
33 static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
35 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
36 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
39 static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
41 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
42 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
45 #if !CONFIG_IS_ENABLED(DM_SPI)
46 struct mxs_spi_slave {
47 struct spi_slave slave;
50 struct mxs_ssp_regs *regs;
53 static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
55 return container_of(slave, struct mxs_spi_slave, slave);
60 #include <dt-structs.h>
63 #define dtd_fsl_imx_spi dtd_fsl_imx28_spi
64 #else /* CONFIG_MX23 */
65 #define dtd_fsl_imx_spi dtd_fsl_imx23_spi
68 struct mxs_spi_platdata {
69 #if CONFIG_IS_ENABLED(OF_PLATDATA)
70 struct dtd_fsl_imx_spi dtplat;
72 s32 frequency; /* Default clock frequency, -1 for none */
73 fdt_addr_t base; /* SPI IP block base address */
74 int num_cs; /* Number of CSes supported */
75 int dma_id; /* ID of the DMA channel */
76 int clk_id; /* ID of the SSP clock */
80 struct mxs_ssp_regs *regs;
81 unsigned int dma_channel;
82 unsigned int max_freq;
88 #if !CONFIG_IS_ENABLED(DM_SPI)
89 static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
90 char *data, int length, int write, unsigned long flags)
92 struct mxs_ssp_regs *ssp_regs = slave->regs;
94 static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
95 char *data, int length, int write,
98 struct mxs_ssp_regs *ssp_regs = priv->regs;
101 if (flags & SPI_XFER_BEGIN)
102 mxs_spi_start_xfer(ssp_regs);
105 /* We transfer 1 byte */
106 #if defined(CONFIG_MX23)
107 writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
108 writel(1, &ssp_regs->hw_ssp_ctrl0_set);
109 #elif defined(CONFIG_MX28)
110 writel(1, &ssp_regs->hw_ssp_xfer_size);
113 if ((flags & SPI_XFER_END) && !length)
114 mxs_spi_end_xfer(ssp_regs);
117 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
119 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
121 writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
123 if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
124 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
125 printf("MXS SPI: Timeout waiting for start\n");
130 writel(*data++, &ssp_regs->hw_ssp_data);
132 writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
135 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
136 SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
137 printf("MXS SPI: Timeout waiting for data\n");
141 *data = readl(&ssp_regs->hw_ssp_data);
145 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
146 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
147 printf("MXS SPI: Timeout waiting for finish\n");
155 #if !CONFIG_IS_ENABLED(DM_SPI)
156 static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
157 char *data, int length, int write, unsigned long flags)
159 struct mxs_ssp_regs *ssp_regs = slave->regs;
161 static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv,
162 char *data, int length, int write,
164 { struct mxs_ssp_regs *ssp_regs = priv->regs;
166 const int xfer_max_sz = 0xff00;
167 const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
168 struct mxs_dma_desc *dp;
170 uint32_t cache_data_count;
171 const uint32_t dstart = (uint32_t)data;
176 #if defined(CONFIG_MX23)
177 const int mxs_spi_pio_words = 1;
178 #elif defined(CONFIG_MX28)
179 const int mxs_spi_pio_words = 4;
182 ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
184 memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
186 ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
187 ctrl0 |= SSP_CTRL0_DATA_XFER;
189 if (flags & SPI_XFER_BEGIN)
190 ctrl0 |= SSP_CTRL0_LOCK_CS;
192 ctrl0 |= SSP_CTRL0_READ;
194 if (length % ARCH_DMA_MINALIGN)
195 cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
197 cache_data_count = length;
199 /* Flush data to DRAM so DMA can pick them up */
201 flush_dcache_range(dstart, dstart + cache_data_count);
203 /* Invalidate the area, so no writeback into the RAM races with DMA */
204 invalidate_dcache_range(dstart, dstart + cache_data_count);
206 #if !CONFIG_IS_ENABLED(DM_SPI)
207 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
209 dmach = priv->dma_channel;
214 dp->address = (dma_addr_t)dp;
215 dp->cmd.address = (dma_addr_t)data;
218 * This is correct, even though it does indeed look insane.
219 * I hereby have to, wholeheartedly, thank Freescale Inc.,
220 * for always inventing insane hardware and keeping me busy
224 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
226 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
229 * The DMA controller can transfer large chunks (64kB) at
230 * time by setting the transfer length to 0. Setting tl to
231 * 0x10000 will overflow below and make .data contain 0.
232 * Otherwise, 0xff00 is the transfer maximum.
234 if (length >= 0x10000)
237 tl = min(length, xfer_max_sz);
240 ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
241 (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
242 MXS_DMA_DESC_HALT_ON_TERMINATE |
243 MXS_DMA_DESC_TERMINATE_FLUSH;
249 dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
251 if (flags & SPI_XFER_END) {
252 ctrl0 &= ~SSP_CTRL0_LOCK_CS;
253 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
258 * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
259 * case of MX28, write only CTRL0 in case of MX23 due
260 * to the difference in register layout. It is utterly
261 * essential that the XFER_SIZE register is written on
262 * a per-descriptor basis with the same size as is the
265 dp->cmd.pio_words[0] = ctrl0;
267 dp->cmd.pio_words[1] = 0;
268 dp->cmd.pio_words[2] = 0;
269 dp->cmd.pio_words[3] = tl;
272 mxs_dma_desc_append(dmach, dp);
277 if (mxs_dma_go(dmach))
280 /* The data arrived into DRAM, invalidate cache over them */
282 invalidate_dcache_range(dstart, dstart + cache_data_count);
287 #if !CONFIG_IS_ENABLED(DM_SPI)
288 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
289 const void *dout, void *din, unsigned long flags)
291 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
292 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
294 int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen,
295 const void *dout, void *din, unsigned long flags)
297 struct udevice *bus = dev_get_parent(dev);
298 struct mxs_spi_priv *priv = dev_get_priv(bus);
299 struct mxs_ssp_regs *ssp_regs = priv->regs;
301 int len = bitlen / 8;
308 if (flags & SPI_XFER_END) {
309 din = (void *)&dummy;
315 /* Half-duplex only */
331 * Check for alignment, if the buffer is aligned, do DMA transfer,
332 * PIO otherwise. This is a temporary workaround until proper bounce
333 * buffer is in place.
336 if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
338 if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
342 if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
343 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
344 #if !CONFIG_IS_ENABLED(DM_SPI)
345 return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
347 return mxs_spi_xfer_pio(priv, data, len, write, flags);
350 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
351 #if !CONFIG_IS_ENABLED(DM_SPI)
352 return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
354 return mxs_spi_xfer_dma(priv, data, len, write, flags);
359 #if !CONFIG_IS_ENABLED(DM_SPI)
360 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
362 /* MXS SPI: 4 ports and 3 chip selects maximum */
363 if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
369 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
370 unsigned int max_hz, unsigned int mode)
372 struct mxs_spi_slave *mxs_slave;
374 if (!spi_cs_is_valid(bus, cs)) {
375 printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
379 mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
383 if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
386 mxs_slave->max_khz = max_hz / 1000;
387 mxs_slave->mode = mode;
388 mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
390 return &mxs_slave->slave;
397 void spi_free_slave(struct spi_slave *slave)
399 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
404 int spi_claim_bus(struct spi_slave *slave)
406 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
407 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
410 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
412 writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
413 SSP_CTRL0_BUS_WIDTH_ONE_BIT,
414 &ssp_regs->hw_ssp_ctrl0);
416 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
417 reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
418 reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
419 writel(reg, &ssp_regs->hw_ssp_ctrl1);
421 writel(0, &ssp_regs->hw_ssp_cmd0);
423 mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
428 void spi_release_bus(struct spi_slave *slave)
432 #else /* CONFIG_DM_SPI */
433 /* Base numbers of i.MX2[38] clk for ssp0 IP block */
434 #define MXS_SSP_IMX23_CLKID_SSP0 33
435 #define MXS_SSP_IMX28_CLKID_SSP0 46
437 static int mxs_spi_probe(struct udevice *bus)
439 struct mxs_spi_platdata *plat = dev_get_platdata(bus);
440 struct mxs_spi_priv *priv = dev_get_priv(bus);
443 debug("%s: probe\n", __func__);
445 #if CONFIG_IS_ENABLED(OF_PLATDATA)
446 struct dtd_fsl_imx_spi *dtplat = &plat->dtplat;
447 struct phandle_1_arg *p1a = &dtplat->clocks[0];
449 priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0];
450 priv->dma_channel = dtplat->dmas[1];
451 priv->clk_id = p1a->arg[0];
452 priv->max_freq = dtplat->spi_max_frequency;
453 plat->num_cs = dtplat->num_cs;
455 debug("OF_PLATDATA: regs: 0x%x max freq: %d clkid: %d\n",
456 (unsigned int)priv->regs, priv->max_freq, priv->clk_id);
458 priv->regs = (struct mxs_ssp_regs *)plat->base;
459 priv->max_freq = plat->frequency;
461 priv->dma_channel = plat->dma_id;
462 priv->clk_id = plat->clk_id;
465 mxs_reset_block(&priv->regs->hw_ssp_ctrl0_reg);
467 ret = mxs_dma_init_channel(priv->dma_channel);
469 printf("%s: DMA init channel error %d\n", __func__, ret);
476 static int mxs_spi_claim_bus(struct udevice *dev)
478 struct udevice *bus = dev_get_parent(dev);
479 struct mxs_spi_priv *priv = dev_get_priv(bus);
480 struct mxs_ssp_regs *ssp_regs = priv->regs;
481 int cs = spi_chip_select(dev);
484 * i.MX28 supports up to 3 CS (SSn0, SSn1, SSn2)
485 * To set them it uses following tuple (WAIT_FOR_IRQ,WAIT_FOR_CMD),
488 * WAIT_FOR_IRQ is bit 21 of HW_SSP_CTRL0
489 * WAIT_FOR_CMD is bit 20 (#defined as MXS_SSP_CHIPSELECT_SHIFT here) of
493 * SSn2 b10 (which require setting WAIT_FOR_IRQ)
495 * However, for now i.MX28 SPI driver will support up till 2 CSes
499 /* Ungate SSP clock and set active CS */
500 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
501 BIT(MXS_SSP_CHIPSELECT_SHIFT) |
502 SSP_CTRL0_CLKGATE, (cs << MXS_SSP_CHIPSELECT_SHIFT));
507 static int mxs_spi_release_bus(struct udevice *dev)
509 struct udevice *bus = dev_get_parent(dev);
510 struct mxs_spi_priv *priv = dev_get_priv(bus);
511 struct mxs_ssp_regs *ssp_regs = priv->regs;
514 setbits_le32(&ssp_regs->hw_ssp_ctrl0, SSP_CTRL0_CLKGATE);
519 static int mxs_spi_set_speed(struct udevice *bus, uint speed)
521 struct mxs_spi_priv *priv = dev_get_priv(bus);
523 int clkid = priv->clk_id - MXS_SSP_IMX28_CLKID_SSP0;
524 #else /* CONFIG_MX23 */
525 int clkid = priv->clk_id - MXS_SSP_IMX23_CLKID_SSP0;
527 if (speed > priv->max_freq)
528 speed = priv->max_freq;
530 debug("%s speed: %u [Hz] clkid: %d\n", __func__, speed, clkid);
531 mxs_set_ssp_busclock(clkid, speed / 1000);
536 static int mxs_spi_set_mode(struct udevice *bus, uint mode)
538 struct mxs_spi_priv *priv = dev_get_priv(bus);
539 struct mxs_ssp_regs *ssp_regs = priv->regs;
543 debug("%s: mode 0x%x\n", __func__, mode);
545 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
546 reg |= (priv->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
547 reg |= (priv->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
548 writel(reg, &ssp_regs->hw_ssp_ctrl1);
550 /* Single bit SPI support */
551 writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
556 static const struct dm_spi_ops mxs_spi_ops = {
557 .claim_bus = mxs_spi_claim_bus,
558 .release_bus = mxs_spi_release_bus,
559 .xfer = mxs_spi_xfer,
560 .set_speed = mxs_spi_set_speed,
561 .set_mode = mxs_spi_set_mode,
563 * cs_info is not needed, since we require all chip selects to be
564 * in the device tree explicitly
568 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
569 static int mxs_ofdata_to_platdata(struct udevice *bus)
571 struct mxs_spi_platdata *plat = bus->platdata;
575 plat->base = dev_read_addr(bus);
577 dev_read_u32_default(bus, "spi-max-frequency", 40000000);
578 plat->num_cs = dev_read_u32_default(bus, "num-cs", 2);
580 ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
582 printf("%s: Reading 'dmas' property failed!\n", __func__);
585 plat->dma_id = prop[1];
587 ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
589 printf("%s: Reading 'clocks' property failed!\n", __func__);
592 plat->clk_id = prop[1];
594 debug("%s: base=0x%x, max-frequency=%d num-cs=%d dma_id=%d clk_id=%d\n",
595 __func__, (uint)plat->base, plat->frequency, plat->num_cs,
596 plat->dma_id, plat->clk_id);
601 static const struct udevice_id mxs_spi_ids[] = {
602 { .compatible = "fsl,imx23-spi" },
603 { .compatible = "fsl,imx28-spi" },
608 U_BOOT_DRIVER(mxs_spi) = {
610 .name = "fsl_imx28_spi",
611 #else /* CONFIG_MX23 */
612 .name = "fsl_imx23_spi",
615 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
616 .of_match = mxs_spi_ids,
617 .ofdata_to_platdata = mxs_ofdata_to_platdata,
619 .platdata_auto_alloc_size = sizeof(struct mxs_spi_platdata),
621 .priv_auto_alloc_size = sizeof(struct mxs_spi_priv),
622 .probe = mxs_spi_probe,