1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
4 * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
11 #include <asm/mpc8xxx_spi.h>
14 SPI_EV_NE = BIT(31 - 22), /* Receiver Not Empty */
15 SPI_EV_NF = BIT(31 - 23), /* Transmitter Not Full */
19 SPI_MODE_LOOP = BIT(31 - 1), /* Loopback mode */
20 SPI_MODE_CI = BIT(31 - 2), /* Clock invert */
21 SPI_MODE_CP = BIT(31 - 3), /* Clock phase */
22 SPI_MODE_DIV16 = BIT(31 - 4), /* Divide clock source by 16 */
23 SPI_MODE_REV = BIT(31 - 5), /* Reverse mode - MSB first */
24 SPI_MODE_MS = BIT(31 - 6), /* Always master */
25 SPI_MODE_EN = BIT(31 - 7), /* Enable interface */
27 SPI_MODE_LEN_MASK = 0xf00000,
28 SPI_MODE_PM_MASK = 0xf0000,
30 SPI_COM_LST = BIT(31 - 9),
33 #define SPI_TIMEOUT 1000
35 struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
37 struct spi_slave *slave;
39 if (!spi_cs_is_valid(bus, cs))
42 slave = spi_alloc_slave_base(bus, cs);
47 * TODO: Some of the code in spi_init() should probably move
48 * here, or into spi_claim_bus() below.
54 void spi_free_slave(struct spi_slave *slave)
61 spi8xxx_t *spi = &((immap_t *)(CONFIG_SYS_IMMR))->spi;
64 * SPI pins on the MPC83xx are not muxed, so all we do is initialize
67 out_be32(&spi->mode, SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN);
68 /* Use SYSCLK / 8 (16.67MHz typ.) */
69 clrsetbits_be32(&spi->mode, 0x000f0000, BIT(16));
70 /* Clear all SPI events */
71 setbits_be32(&spi->event, 0xffffffff);
72 /* Mask all SPI interrupts */
73 clrbits_be32(&spi->mask, 0xffffffff);
74 /* LST bit doesn't do anything, so disregard */
75 out_be32(&spi->com, 0);
78 int spi_claim_bus(struct spi_slave *slave)
83 void spi_release_bus(struct spi_slave *slave)
87 int spi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, void *din,
90 spi8xxx_t *spi = &((immap_t *)(CONFIG_SYS_IMMR))->spi;
91 uint tmpdout, tmpdin, event;
92 int num_blks = DIV_ROUND_UP(bitlen, 32);
96 debug("%s: slave %u:%u dout %08X din %08X bitlen %u\n", __func__,
97 slave->bus, slave->cs, *(uint *)dout, *(uint *)din, bitlen);
99 if (flags & SPI_XFER_BEGIN)
100 spi_cs_activate(slave);
102 /* Clear all SPI events */
103 setbits_be32(&spi->event, 0xffffffff);
105 /* Handle data in 32-bit chunks */
108 char_size = (bitlen >= 32 ? 32 : bitlen);
110 /* Shift data so it's msb-justified */
111 tmpdout = *(u32 *)dout >> (32 - char_size);
113 /* The LEN field of the SPMODE register is set as follows:
117 * 4 < len <= 16 len - 1
121 clrbits_be32(&spi->mode, SPI_MODE_EN);
124 clrsetbits_be32(&spi->mode, 0x00f00000, (3 << 20));
125 } else if (bitlen <= 16) {
126 clrsetbits_be32(&spi->mode, 0x00f00000,
127 ((bitlen - 1) << 20));
129 clrbits_be32(&spi->mode, 0x00f00000);
130 /* Set up the next iteration if sending > 32 bits */
135 setbits_be32(&spi->mode, SPI_MODE_EN);
137 /* Write the data out */
138 out_be32(&spi->tx, tmpdout);
140 debug("*** %s: ... %08x written\n", __func__, tmpdout);
143 * Wait for SPI transmit to get out
144 * or time out (1 second = 1000 ms)
145 * The NE event must be read and cleared first
147 for (tm = 0; tm < SPI_TIMEOUT; ++tm) {
148 event = in_be32(&spi->event);
149 bool have_ne = event & SPI_EV_NE;
150 bool have_nf = event & SPI_EV_NF;
155 tmpdin = in_be32(&spi->rx);
156 setbits_be32(&spi->event, SPI_EV_NE);
158 *(u32 *)din = (tmpdin << (32 - char_size));
159 if (char_size == 32) {
160 /* Advance output buffer by 32 bits */
165 * Only bail when we've had both NE and NF events.
166 * This will cause timeouts on RO devices, so maybe
167 * in the future put an arbitrary delay after writing
168 * the device. Arbitrary delays suck, though...
174 if (tm >= SPI_TIMEOUT)
175 debug("*** %s: Time out during SPI transfer\n",
178 debug("*** %s: transfer ended. Value=%08x\n", __func__, tmpdin);
181 if (flags & SPI_XFER_END)
182 spi_cs_deactivate(slave);