1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2011 The Chromium OS Authors.
5 * This file is derived from the flashrom project.
11 struct ich7_spi_regs {
23 struct ich9_spi_regs {
24 uint32_t bfpr; /* 0x00 */
29 uint32_t fdata[16]; /* 0x10 */
30 uint32_t frap; /* 0x50 */
32 uint32_t _reserved1[3];
33 uint32_t pr[5]; /* 0x74 */
34 uint32_t _reserved2[2];
35 uint8_t ssfs; /* 0x90 */
37 uint16_t preop; /* 0x94 */
39 uint8_t opmenu[8]; /* 0x98 */
41 uint8_t _reserved3[12];
42 uint32_t fdoc; /* 0xb0 */
44 uint8_t _reserved4[8];
45 uint32_t afc; /* 0xc0 */
48 uint8_t _reserved5[4];
49 uint32_t fpb; /* 0xd0 */
50 uint8_t _reserved6[28];
51 uint32_t srdl; /* 0xf0 */
64 SPIS_RESERVED_MASK = 0x7ff0,
65 SSFS_RESERVED_MASK = 0x7fe2
75 SSFC_SCF_MASK = 0x070000,
76 SSFC_RESERVED = 0xf80000,
78 /* Mask for speed byte, biuts 23:16 of SSFC */
79 SSFC_SCF_33MHZ = 0x01,
86 HSFS_BERASE_MASK = 0x0018,
87 HSFS_BERASE_SHIFT = 3,
96 HSFC_FCYCLE_MASK = 0x0006,
97 HSFC_FCYCLE_SHIFT = 1,
98 HSFC_FDBC_MASK = 0x3f00,
114 #define SPI_OPCODE_WRSR 0x01
115 #define SPI_OPCODE_PAGE_PROGRAM 0x02
116 #define SPI_OPCODE_READ 0x03
117 #define SPI_OPCODE_WRDIS 0x04
118 #define SPI_OPCODE_RDSR 0x05
119 #define SPI_OPCODE_WREN 0x06
120 #define SPI_OPCODE_FAST_READ 0x0b
121 #define SPI_OPCODE_ERASE_SECT 0x20
122 #define SPI_OPCODE_READ_ID 0x9f
123 #define SPI_OPCODE_ERASE_BLOCK 0xd8
125 #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
126 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
127 #define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
128 #define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
130 #define SPI_OPMENU_0 SPI_OPCODE_WRSR
131 #define SPI_OPTYPE_0 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
133 #define SPI_OPMENU_1 SPI_OPCODE_PAGE_PROGRAM
134 #define SPI_OPTYPE_1 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
136 #define SPI_OPMENU_2 SPI_OPCODE_READ
137 #define SPI_OPTYPE_2 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
139 #define SPI_OPMENU_3 SPI_OPCODE_RDSR
140 #define SPI_OPTYPE_3 SPI_OPCODE_TYPE_READ_NO_ADDRESS
142 #define SPI_OPMENU_4 SPI_OPCODE_ERASE_SECT
143 #define SPI_OPTYPE_4 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
145 #define SPI_OPMENU_5 SPI_OPCODE_READ_ID
146 #define SPI_OPTYPE_5 SPI_OPCODE_TYPE_READ_NO_ADDRESS
148 #define SPI_OPMENU_6 SPI_OPCODE_ERASE_BLOCK
149 #define SPI_OPTYPE_6 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
151 #define SPI_OPMENU_7 SPI_OPCODE_FAST_READ
152 #define SPI_OPTYPE_7 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
154 #define SPI_OPPREFIX ((SPI_OPCODE_WREN << 8) | SPI_OPCODE_WREN)
155 #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
156 (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
157 (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
158 (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0))
159 #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
160 (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0))
161 #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
162 (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0))
164 #define ICH_BOUNDARY 0x1000
171 struct ich_spi_platdata {
172 enum ich_version ich_version; /* Controller version, 7 or 9 */
173 bool lockdown; /* lock down controller settings? */
176 struct ich_spi_priv {
179 void *base; /* Base of register set */
189 uint32_t *pr; /* only for ich9 */
190 int speed; /* pointer to speed control */
191 ulong max_speed; /* Maximum bus speed in MHz */
192 ulong cur_speed; /* Current bus speed */
193 struct spi_trans trans; /* current transaction in progress */