1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011-12 The Chromium OS Authors.
5 * This file is derived from the flashrom project.
8 #define LOG_CATEGORY UCLASS_SPI
11 #include <bootstage.h>
14 #include <dt-structs.h>
22 #include <spi_flash.h>
25 #include <asm/fast_spi.h>
27 #include <dm/uclass-internal.h>
29 #include <linux/bitops.h>
30 #include <linux/delay.h>
31 #include <linux/sizes.h>
36 #define debug_trace(fmt, args...) debug(fmt, ##args)
38 #define debug_trace(x, args...)
41 struct ich_spi_platdata {
42 #if CONFIG_IS_ENABLED(OF_PLATDATA)
43 struct dtd_intel_fast_spi dtplat;
45 enum ich_version ich_version; /* Controller version, 7 or 9 */
46 bool lockdown; /* lock down controller settings? */
47 ulong mmio_base; /* Base of MMIO registers */
48 pci_dev_t bdf; /* PCI address used by of-platdata */
49 bool hwseq; /* Use hardware sequencing (not s/w) */
52 static u8 ich_readb(struct ich_spi_priv *priv, int reg)
54 u8 value = readb(priv->base + reg);
56 debug_trace("read %2.2x from %4.4x\n", value, reg);
61 static u16 ich_readw(struct ich_spi_priv *priv, int reg)
63 u16 value = readw(priv->base + reg);
65 debug_trace("read %4.4x from %4.4x\n", value, reg);
70 static u32 ich_readl(struct ich_spi_priv *priv, int reg)
72 u32 value = readl(priv->base + reg);
74 debug_trace("read %8.8x from %4.4x\n", value, reg);
79 static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
81 writeb(value, priv->base + reg);
82 debug_trace("wrote %2.2x to %4.4x\n", value, reg);
85 static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
87 writew(value, priv->base + reg);
88 debug_trace("wrote %4.4x to %4.4x\n", value, reg);
91 static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
93 writel(value, priv->base + reg);
94 debug_trace("wrote %8.8x to %4.4x\n", value, reg);
97 static void write_reg(struct ich_spi_priv *priv, const void *value,
98 int dest_reg, uint32_t size)
100 memcpy_toio(priv->base + dest_reg, value, size);
103 static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
106 memcpy_fromio(value, priv->base + src_reg, size);
109 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
111 const uint32_t bbar_mask = 0x00ffff00;
112 uint32_t ichspi_bbar;
115 minaddr &= bbar_mask;
116 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
117 ichspi_bbar |= minaddr;
118 ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
122 /* @return 1 if the SPI flash supports the 33MHz speed */
123 static bool ich9_can_do_33mhz(struct udevice *dev)
125 struct ich_spi_priv *priv = dev_get_priv(dev);
128 if (!CONFIG_IS_ENABLED(PCI))
130 /* Observe SPI Descriptor Component Section 0 */
131 dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
133 /* Extract the Write/Erase SPI Frequency from descriptor */
134 dm_pci_read_config32(priv->pch, 0xb4, &fdod);
136 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
137 speed = (fdod >> 21) & 7;
142 static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
144 if (plat->ich_version == ICHV_7) {
145 struct ich7_spi_regs *ich7_spi = sbase;
147 setbits_le16(&ich7_spi->spis, SPIS_LOCK);
148 } else if (plat->ich_version == ICHV_9) {
149 struct ich9_spi_regs *ich9_spi = sbase;
151 setbits_le16(&ich9_spi->hsfs, HSFS_FLOCKDN);
155 static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
159 if (plat->ich_version == ICHV_7) {
160 struct ich7_spi_regs *ich7_spi = sbase;
162 lock = readw(&ich7_spi->spis) & SPIS_LOCK;
163 } else if (plat->ich_version == ICHV_9) {
164 struct ich9_spi_regs *ich9_spi = sbase;
166 lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
172 static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
176 uint8_t opmenu[ctlr->menubytes];
179 /* The lock is off, so just use index 0. */
180 ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
181 optypes = ich_readw(ctlr, ctlr->optype);
182 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
183 ich_writew(ctlr, optypes, ctlr->optype);
186 /* The lock is on. See if what we need is on the menu. */
188 uint16_t opcode_index;
190 /* Write Enable is handled as atomic prefix */
191 if (trans->opcode == SPI_OPCODE_WREN)
194 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
195 for (opcode_index = 0; opcode_index < ctlr->menubytes;
197 if (opmenu[opcode_index] == trans->opcode)
201 if (opcode_index == ctlr->menubytes) {
202 debug("ICH SPI: Opcode %x not found\n", trans->opcode);
206 optypes = ich_readw(ctlr, ctlr->optype);
207 optype = (optypes >> (opcode_index * 2)) & 0x3;
209 if (optype != trans->type) {
210 debug("ICH SPI: Transaction doesn't fit type %d\n",
219 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
220 * below is true) or 0. In case the wait was for the bit(s) to set - write
221 * those bits back, which would cause resetting them.
223 * Return the last read status value on success or -1 on failure.
225 static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
228 int timeout = 600000; /* This will result in 6s */
232 status = ich_readw(ctlr, ctlr->status);
233 if (wait_til_set ^ ((status & bitmask) == 0)) {
235 ich_writew(ctlr, status & bitmask,
242 debug("ICH SPI: SCIP timeout, read %x, expected %x, wts %x %x\n",
243 status, bitmask, wait_til_set, status & bitmask);
248 static void ich_spi_config_opcode(struct udevice *dev)
250 struct ich_spi_priv *ctlr = dev_get_priv(dev);
253 * PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down
254 * to prevent accidental or intentional writes. Before they get
255 * locked down, these registers should be initialized properly.
257 ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
258 ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
259 ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
260 ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
263 static int ich_spi_exec_op_swseq(struct spi_slave *slave,
264 const struct spi_mem_op *op)
266 struct udevice *bus = dev_get_parent(slave->dev);
267 struct ich_spi_platdata *plat = dev_get_platdata(bus);
268 struct ich_spi_priv *ctlr = dev_get_priv(bus);
270 int16_t opcode_index;
273 struct spi_trans *trans = &ctlr->trans;
274 bool lock = spi_lock_status(plat, ctlr->base);
281 if (op->data.nbytes) {
282 if (op->data.dir == SPI_MEM_DATA_IN) {
283 trans->in = op->data.buf.in;
284 trans->bytesin = op->data.nbytes;
286 trans->out = op->data.buf.out;
287 trans->bytesout = op->data.nbytes;
291 if (trans->opcode != op->cmd.opcode)
292 trans->opcode = op->cmd.opcode;
294 if (lock && trans->opcode == SPI_OPCODE_WRDIS)
297 if (trans->opcode == SPI_OPCODE_WREN) {
299 * Treat Write Enable as Atomic Pre-Op if possible
300 * in order to prevent the Management Engine from
301 * issuing a transaction between WREN and DATA.
304 ich_writew(ctlr, trans->opcode, ctlr->preop);
308 ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
312 if (plat->ich_version == ICHV_7)
313 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
315 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
317 /* Try to guess spi transaction type */
318 if (op->data.dir == SPI_MEM_DATA_OUT) {
320 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
322 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
325 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
327 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
329 /* Special erase case handling */
330 if (op->addr.nbytes && !op->data.buswidth)
331 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
333 opcode_index = spi_setup_opcode(ctlr, trans, lock);
334 if (opcode_index < 0)
337 if (op->addr.nbytes) {
338 trans->offset = op->addr.val;
342 if (ctlr->speed && ctlr->max_speed >= 33000000) {
345 byte = ich_readb(ctlr, ctlr->speed);
346 if (ctlr->cur_speed >= 33000000)
347 byte |= SSFC_SCF_33MHZ;
349 byte &= ~SSFC_SCF_33MHZ;
350 ich_writeb(ctlr, byte, ctlr->speed);
353 /* Preset control fields */
354 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
356 /* Issue atomic preop cycle if needed */
357 if (ich_readw(ctlr, ctlr->preop))
360 if (!trans->bytesout && !trans->bytesin) {
361 /* SPI addresses are 24 bit only */
363 ich_writel(ctlr, trans->offset & 0x00FFFFFF,
367 * This is a 'no data' command (like Write Enable), its
368 * bitesout size was 1, decremented to zero while executing
369 * spi_setup_opcode() above. Tell the chip to send the
372 ich_writew(ctlr, control, ctlr->control);
374 /* wait for the result */
375 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
379 if (status & SPIS_FCERR) {
380 debug("ICH SPI: Command transaction error\n");
387 while (trans->bytesout || trans->bytesin) {
388 uint32_t data_length;
390 /* SPI addresses are 24 bit only */
391 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
394 data_length = min(trans->bytesout, ctlr->databytes);
396 data_length = min(trans->bytesin, ctlr->databytes);
398 /* Program data into FDATA0 to N */
399 if (trans->bytesout) {
400 write_reg(ctlr, trans->out, ctlr->data, data_length);
401 trans->bytesout -= data_length;
404 /* Add proper control fields' values */
405 control &= ~((ctlr->databytes - 1) << 8);
407 control |= (data_length - 1) << 8;
410 ich_writew(ctlr, control, ctlr->control);
412 /* Wait for Cycle Done Status or Flash Cycle Error */
413 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
417 if (status & SPIS_FCERR) {
418 debug("ICH SPI: Data transaction error %x\n", status);
422 if (trans->bytesin) {
423 read_reg(ctlr, ctlr->data, trans->in, data_length);
424 trans->bytesin -= data_length;
428 /* Clear atomic preop now that xfer is done */
430 ich_writew(ctlr, 0, ctlr->preop);
436 * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and
437 * that the operation does not cross page boundary.
439 static uint get_xfer_len(u32 offset, int len, int page_size)
441 uint xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE);
442 uint bytes_left = ALIGN(offset, page_size) - offset;
445 xfer_len = min(xfer_len, bytes_left);
450 /* Fill FDATAn FIFO in preparation for a write transaction */
451 static void fill_xfer_fifo(struct fast_spi_regs *regs, const void *data,
454 memcpy(regs->fdata, data, len);
457 /* Drain FDATAn FIFO after a read transaction populates data */
458 static void drain_xfer_fifo(struct fast_spi_regs *regs, void *dest, uint len)
460 memcpy(dest, regs->fdata, len);
463 /* Fire up a transfer using the hardware sequencer */
464 static void start_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle,
465 uint offset, uint len)
467 /* Make sure all W1C status bits get cleared */
470 hsfsts = readl(®s->hsfsts_ctl);
471 hsfsts &= ~(HSFSTS_FCYCLE_MASK | HSFSTS_FDBC_MASK);
472 hsfsts |= HSFSTS_AEL | HSFSTS_FCERR | HSFSTS_FDONE;
474 /* Set up transaction parameters */
475 hsfsts |= hsfsts_cycle << HSFSTS_FCYCLE_SHIFT;
476 hsfsts |= ((len - 1) << HSFSTS_FDBC_SHIFT) & HSFSTS_FDBC_MASK;
477 hsfsts |= HSFSTS_FGO;
479 writel(offset, ®s->faddr);
480 writel(hsfsts, ®s->hsfsts_ctl);
483 static int wait_for_hwseq_xfer(struct fast_spi_regs *regs, uint offset)
488 start = get_timer(0);
490 hsfsts = readl(®s->hsfsts_ctl);
491 if (hsfsts & HSFSTS_FCERR) {
492 debug("SPI transaction error at offset %x HSFSTS = %08x\n",
496 if (hsfsts & HSFSTS_AEL)
499 if (hsfsts & HSFSTS_FDONE)
501 } while (get_timer(start) < SPIBAR_HWSEQ_XFER_TIMEOUT_MS);
503 debug("SPI transaction timeout at offset %x HSFSTS = %08x, timer %d\n",
504 offset, hsfsts, (uint)get_timer(start));
510 * exec_sync_hwseq_xfer() - Execute flash transfer by hardware sequencing
512 * This waits until complete or timeout
514 * @regs: SPI registers
515 * @hsfsts_cycle: Cycle type (enum hsfsts_cycle_t)
516 * @offset: Offset to access
517 * @len: Number of bytes to transfer (can be 0)
518 * @return 0 if OK, -EIO on flash-cycle error (FCERR), -EPERM on access error
519 * (AEL), -ETIMEDOUT on timeout
521 static int exec_sync_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle,
522 uint offset, uint len)
524 start_hwseq_xfer(regs, hsfsts_cycle, offset, len);
526 return wait_for_hwseq_xfer(regs, offset);
529 static int ich_spi_exec_op_hwseq(struct spi_slave *slave,
530 const struct spi_mem_op *op)
532 struct spi_flash *flash = dev_get_uclass_priv(slave->dev);
533 struct udevice *bus = dev_get_parent(slave->dev);
534 struct ich_spi_priv *priv = dev_get_priv(bus);
535 struct fast_spi_regs *regs = priv->base;
544 offset = op->addr.val;
545 len = op->data.nbytes;
547 switch (op->cmd.opcode) {
549 cycle = HSFSTS_CYCLE_RDID;
551 case SPINOR_OP_READ_FAST:
552 cycle = HSFSTS_CYCLE_READ;
555 cycle = HSFSTS_CYCLE_WRITE;
558 /* Nothing needs to be done */
561 cycle = HSFSTS_CYCLE_WR_STATUS;
564 cycle = HSFSTS_CYCLE_RD_STATUS;
567 return 0; /* ignore */
568 case SPINOR_OP_BE_4K:
569 cycle = HSFSTS_CYCLE_4K_ERASE;
570 ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0);
573 debug("Unknown cycle %x\n", op->cmd.opcode);
577 out = op->data.dir == SPI_MEM_DATA_OUT;
578 buf = out ? (u8 *)op->data.buf.out : op->data.buf.in;
579 page_size = flash->page_size ? : 256;
582 uint xfer_len = get_xfer_len(offset, len, page_size);
585 fill_xfer_fifo(regs, buf, xfer_len);
587 ret = exec_sync_hwseq_xfer(regs, cycle, offset, xfer_len);
592 drain_xfer_fifo(regs, buf, xfer_len);
602 static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
604 struct udevice *bus = dev_get_parent(slave->dev);
605 struct ich_spi_platdata *plat = dev_get_platdata(bus);
608 bootstage_start(BOOTSTAGE_ID_ACCUM_SPI, "fast_spi");
610 ret = ich_spi_exec_op_hwseq(slave, op);
612 ret = ich_spi_exec_op_swseq(slave, op);
613 bootstage_accum(BOOTSTAGE_ID_ACCUM_SPI);
619 * ich_spi_get_basics() - Get basic information about the ICH device
621 * This works without probing any devices if requested.
623 * @bus: SPI controller to use
624 * @can_probe: true if this function is allowed to probe the PCH
625 * @pchp: Returns a pointer to the pch, or NULL if not found
626 * @ich_versionp: Returns ICH version detected on success
627 * @mmio_basep: Returns the address of the SPI registers on success
628 * @return 0 if OK, -EPROTOTYPE if the PCH could not be found, -EAGAIN if
629 * the function cannot success without probing, possible another error if
630 * pch_get_spi_base() fails
632 static int ich_spi_get_basics(struct udevice *bus, bool can_probe,
633 struct udevice **pchp,
634 enum ich_version *ich_versionp, ulong *mmio_basep)
636 struct udevice *pch = NULL;
639 /* Find a PCH if there is one */
641 pch = dev_get_parent(bus);
642 if (device_get_uclass_id(pch) != UCLASS_PCH) {
643 uclass_first_device(UCLASS_PCH, &pch);
645 return log_msg_ret("uclass", -EPROTOTYPE);
649 *ich_versionp = dev_get_driver_data(bus);
650 if (*ich_versionp == ICHV_APL)
651 *mmio_basep = dm_pci_read_bar32(bus, 0);
653 ret = pch_get_spi_base(pch, mmio_basep);
662 * ich_get_mmap_bus() - Handle the get_mmap() method for a bus
664 * There are several cases to consider:
665 * 1. Using of-platdata, in which case we have the BDF and can access the
666 * registers by reading the BAR
667 * 2. Not using of-platdata, but still with a SPI controller that is on its own
668 * PCI PDF. In this case we read the BDF from the parent platdata and again get
669 * the registers by reading the BAR
670 * 3. Using a SPI controller that is a child of the PCH, in which case we try
671 * to find the registers by asking the PCH. This only works if the PCH has
672 * been probed (which it will be if the bus is probed since parents are
673 * probed before children), since the PCH may not have a PCI address until
674 * its parent (the PCI bus itself) has been probed. If you are using this
675 * method then you should make sure the SPI bus is probed.
677 * The first two cases are useful in early init. The last one is more useful
680 static int ich_get_mmap_bus(struct udevice *bus, ulong *map_basep,
681 uint *map_sizep, uint *offsetp)
684 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
685 if (device_is_on_pci_bus(bus)) {
686 struct pci_child_platdata *pplat;
688 pplat = dev_get_parent_platdata(bus);
689 spi_bdf = pplat->devfn;
691 enum ich_version ich_version;
692 struct fast_spi_regs *regs;
697 ret = ich_spi_get_basics(bus, device_active(bus), &pch,
698 &ich_version, &mmio_base);
700 return log_msg_ret("basics", ret);
701 regs = (struct fast_spi_regs *)mmio_base;
703 return fast_spi_get_bios_mmap_regs(regs, map_basep, map_sizep,
707 struct ich_spi_platdata *plat = dev_get_platdata(bus);
710 * We cannot rely on plat->bdf being set up yet since this method can
711 * be called before the device is probed. Use the of-platdata directly
714 spi_bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
717 return fast_spi_get_bios_mmap(spi_bdf, map_basep, map_sizep, offsetp);
720 static int ich_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep,
723 struct udevice *bus = dev_get_parent(dev);
725 return ich_get_mmap_bus(bus, map_basep, map_sizep, offsetp);
728 static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op)
730 unsigned int page_offset;
731 int addr = op->addr.val;
732 unsigned int byte_count = op->data.nbytes;
734 if (hweight32(ICH_BOUNDARY) == 1) {
735 page_offset = addr & (ICH_BOUNDARY - 1);
739 page_offset = do_div(aux, ICH_BOUNDARY);
742 if (op->data.dir == SPI_MEM_DATA_IN) {
743 if (slave->max_read_size) {
744 op->data.nbytes = min(ICH_BOUNDARY - page_offset,
745 slave->max_read_size);
747 } else if (slave->max_write_size) {
748 op->data.nbytes = min(ICH_BOUNDARY - page_offset,
749 slave->max_write_size);
752 op->data.nbytes = min(op->data.nbytes, byte_count);
757 static int ich_protect_lockdown(struct udevice *dev)
759 struct ich_spi_platdata *plat = dev_get_platdata(dev);
760 struct ich_spi_priv *priv = dev_get_priv(dev);
763 /* Disable the BIOS write protect so write commands are allowed */
765 ret = pch_set_spi_protect(priv->pch, false);
766 if (ret == -ENOSYS) {
769 bios_cntl = ich_readb(priv, priv->bcr);
770 bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
771 bios_cntl |= 1; /* Write Protect Disable (WPD) */
772 ich_writeb(priv, bios_cntl, priv->bcr);
774 debug("%s: Failed to disable write-protect: err=%d\n",
779 /* Lock down SPI controller settings if required */
780 if (plat->lockdown) {
781 ich_spi_config_opcode(dev);
782 spi_lock_down(plat, priv->base);
788 static int ich_init_controller(struct udevice *dev,
789 struct ich_spi_platdata *plat,
790 struct ich_spi_priv *ctlr)
792 if (spl_phase() == PHASE_TPL) {
793 struct ich_spi_platdata *plat = dev_get_platdata(dev);
796 ret = fast_spi_early_init(plat->bdf, plat->mmio_base);
801 ctlr->base = (void *)plat->mmio_base;
802 if (plat->ich_version == ICHV_7) {
803 struct ich7_spi_regs *ich7_spi = ctlr->base;
805 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
806 ctlr->menubytes = sizeof(ich7_spi->opmenu);
807 ctlr->optype = offsetof(struct ich7_spi_regs, optype);
808 ctlr->addr = offsetof(struct ich7_spi_regs, spia);
809 ctlr->data = offsetof(struct ich7_spi_regs, spid);
810 ctlr->databytes = sizeof(ich7_spi->spid);
811 ctlr->status = offsetof(struct ich7_spi_regs, spis);
812 ctlr->control = offsetof(struct ich7_spi_regs, spic);
813 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
814 ctlr->preop = offsetof(struct ich7_spi_regs, preop);
815 } else if (plat->ich_version == ICHV_9) {
816 struct ich9_spi_regs *ich9_spi = ctlr->base;
818 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
819 ctlr->menubytes = sizeof(ich9_spi->opmenu);
820 ctlr->optype = offsetof(struct ich9_spi_regs, optype);
821 ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
822 ctlr->data = offsetof(struct ich9_spi_regs, fdata);
823 ctlr->databytes = sizeof(ich9_spi->fdata);
824 ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
825 ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
826 ctlr->speed = ctlr->control + 2;
827 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
828 ctlr->preop = offsetof(struct ich9_spi_regs, preop);
829 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
830 ctlr->pr = &ich9_spi->pr[0];
831 } else if (plat->ich_version == ICHV_APL) {
833 debug("ICH SPI: Unrecognised ICH version %d\n",
838 /* Work out the maximum speed we can support */
839 ctlr->max_speed = 20000000;
840 if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
841 ctlr->max_speed = 33000000;
842 debug("ICH SPI: Version ID %d detected at %lx, speed %ld\n",
843 plat->ich_version, plat->mmio_base, ctlr->max_speed);
845 ich_set_bbar(ctlr, 0);
850 static int ich_cache_bios_region(struct udevice *dev)
858 ret = ich_get_mmap_bus(dev, &map_base, &map_size, &offset);
862 /* Don't use WRBACK since we are not supposed to write to SPI flash */
863 base = SZ_4G - map_size;
864 mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size);
865 log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size);
870 static int ich_spi_probe(struct udevice *dev)
872 struct ich_spi_platdata *plat = dev_get_platdata(dev);
873 struct ich_spi_priv *priv = dev_get_priv(dev);
876 ret = ich_init_controller(dev, plat, priv);
880 if (spl_phase() == PHASE_TPL) {
881 /* Cache the BIOS to speed things up */
882 ret = ich_cache_bios_region(dev);
886 ret = ich_protect_lockdown(dev);
890 priv->cur_speed = priv->max_speed;
895 static int ich_spi_remove(struct udevice *bus)
898 * Configure SPI controller so that the Linux MTD driver can fully
899 * access the SPI NOR chip
901 ich_spi_config_opcode(bus);
906 static int ich_spi_set_speed(struct udevice *bus, uint speed)
908 struct ich_spi_priv *priv = dev_get_priv(bus);
910 priv->cur_speed = speed;
915 static int ich_spi_set_mode(struct udevice *bus, uint mode)
917 debug("%s: mode=%d\n", __func__, mode);
922 static int ich_spi_child_pre_probe(struct udevice *dev)
924 struct udevice *bus = dev_get_parent(dev);
925 struct ich_spi_platdata *plat = dev_get_platdata(bus);
926 struct ich_spi_priv *priv = dev_get_priv(bus);
927 struct spi_slave *slave = dev_get_parent_priv(dev);
930 * Yes this controller can only write a small number of bytes at
931 * once! The limit is typically 64 bytes. For hardware sequencing a
932 * a loop is used to get around this.
935 slave->max_write_size = priv->databytes;
937 * ICH 7 SPI controller only supports array read command
938 * and byte program command for SST flash
940 if (plat->ich_version == ICHV_7)
941 slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
946 static int ich_spi_ofdata_to_platdata(struct udevice *dev)
948 struct ich_spi_platdata *plat = dev_get_platdata(dev);
951 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
952 struct ich_spi_priv *priv = dev_get_priv(dev);
954 ret = ich_spi_get_basics(dev, true, &priv->pch, &plat->ich_version,
957 return log_msg_ret("basics", ret);
958 plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");
960 * Use an int so that the property is present in of-platdata even
963 plat->hwseq = dev_read_u32_default(dev, "intel,hardware-seq", 0);
965 plat->ich_version = ICHV_APL;
966 plat->mmio_base = plat->dtplat.early_regs[0];
967 plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
968 plat->hwseq = plat->dtplat.intel_hardware_seq;
970 debug("%s: mmio_base=%lx\n", __func__, plat->mmio_base);
975 static const struct spi_controller_mem_ops ich_controller_mem_ops = {
976 .adjust_op_size = ich_spi_adjust_size,
978 .exec_op = ich_spi_exec_op,
981 static const struct dm_spi_ops ich_spi_ops = {
982 /* xfer is not supported */
983 .set_speed = ich_spi_set_speed,
984 .set_mode = ich_spi_set_mode,
985 .mem_ops = &ich_controller_mem_ops,
986 .get_mmap = ich_get_mmap,
988 * cs_info is not needed, since we require all chip selects to be
989 * in the device tree explicitly
993 static const struct udevice_id ich_spi_ids[] = {
994 { .compatible = "intel,ich7-spi", ICHV_7 },
995 { .compatible = "intel,ich9-spi", ICHV_9 },
996 { .compatible = "intel,fast-spi", ICHV_APL },
1000 U_BOOT_DRIVER(intel_fast_spi) = {
1001 .name = "intel_fast_spi",
1003 .of_match = ich_spi_ids,
1004 .ops = &ich_spi_ops,
1005 .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
1006 .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
1007 .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
1008 .child_pre_probe = ich_spi_child_pre_probe,
1009 .probe = ich_spi_probe,
1010 .remove = ich_spi_remove,
1011 .flags = DM_FLAG_OS_PREPARE,