2 * Copyright (c) 2011-12 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
6 * This file is derived from the flashrom project.
20 #define SPI_OPCODE_WREN 0x06
21 #define SPI_OPCODE_FAST_READ 0x0b
24 #define debug_trace(fmt, args...) debug(fmt, ##args)
26 #define debug_trace(x, args...)
29 struct ich_spi_platdata {
30 pci_dev_t dev; /* PCI device number */
31 int ich_version; /* Controller version, 7 or 9 */
32 bool use_sbase; /* Use SBASE instead of RCB */
40 void *base; /* Base of register set */
50 uint32_t *pr; /* only for ich9 */
51 int speed; /* pointer to speed control */
52 ulong max_speed; /* Maximum bus speed in MHz */
53 ulong cur_speed; /* Current bus speed */
54 struct spi_trans trans; /* current transaction in progress */
57 static u8 ich_readb(struct ich_spi_priv *priv, int reg)
59 u8 value = readb(priv->base + reg);
61 debug_trace("read %2.2x from %4.4x\n", value, reg);
66 static u16 ich_readw(struct ich_spi_priv *priv, int reg)
68 u16 value = readw(priv->base + reg);
70 debug_trace("read %4.4x from %4.4x\n", value, reg);
75 static u32 ich_readl(struct ich_spi_priv *priv, int reg)
77 u32 value = readl(priv->base + reg);
79 debug_trace("read %8.8x from %4.4x\n", value, reg);
84 static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
86 writeb(value, priv->base + reg);
87 debug_trace("wrote %2.2x to %4.4x\n", value, reg);
90 static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
92 writew(value, priv->base + reg);
93 debug_trace("wrote %4.4x to %4.4x\n", value, reg);
96 static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
98 writel(value, priv->base + reg);
99 debug_trace("wrote %8.8x to %4.4x\n", value, reg);
102 static void write_reg(struct ich_spi_priv *priv, const void *value,
103 int dest_reg, uint32_t size)
105 memcpy_toio(priv->base + dest_reg, value, size);
108 static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
111 memcpy_fromio(value, priv->base + src_reg, size);
114 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
116 const uint32_t bbar_mask = 0x00ffff00;
117 uint32_t ichspi_bbar;
119 minaddr &= bbar_mask;
120 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
121 ichspi_bbar |= minaddr;
122 ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
126 * Check if this device ID matches one of supported Intel PCH devices.
128 * Return the ICH version if there is a match, or zero otherwise.
130 static int get_ich_version(uint16_t device_id)
132 if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
133 device_id == PCI_DEVICE_ID_INTEL_ITC_LPC ||
134 device_id == PCI_DEVICE_ID_INTEL_QRK_ILB)
137 if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
138 device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
139 (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
140 device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
141 device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC ||
142 device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC ||
143 device_id == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LPC)
149 /* @return 1 if the SPI flash supports the 33MHz speed */
150 static int ich9_can_do_33mhz(pci_dev_t dev)
154 /* Observe SPI Descriptor Component Section 0 */
155 pci_write_config_dword(dev, 0xb0, 0x1000);
157 /* Extract the Write/Erase SPI Frequency from descriptor */
158 pci_read_config_dword(dev, 0xb4, &fdod);
160 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
161 speed = (fdod >> 21) & 7;
166 static int ich_find_spi_controller(struct ich_spi_platdata *ich)
168 int last_bus = pci_last_busno();
171 if (last_bus == -1) {
172 debug("No PCI busses?\n");
176 for (bus = 0; bus <= last_bus; bus++) {
177 uint16_t vendor_id, device_id;
181 dev = PCI_BDF(bus, 31, 0);
182 pci_read_config_dword(dev, 0, &ids);
184 device_id = ids >> 16;
186 if (vendor_id == PCI_VENDOR_ID_INTEL) {
188 ich->ich_version = get_ich_version(device_id);
189 if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
190 ich->use_sbase = true;
191 return ich->ich_version == 0 ? -ENODEV : 0;
195 debug("ICH SPI: No ICH found.\n");
199 static int ich_init_controller(struct ich_spi_platdata *plat,
200 struct ich_spi_priv *ctlr)
202 uint8_t *rcrb; /* Root Complex Register Block */
203 uint32_t rcba; /* Root Complex Base Address */
207 pci_read_config_dword(plat->dev, 0xf0, &rcba);
208 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
209 rcrb = (uint8_t *)(rcba & 0xffffc000);
211 /* SBASE is similar */
212 pci_read_config_dword(plat->dev, 0x54, &sbase_addr);
213 sbase = (uint8_t *)(sbase_addr & 0xfffffe00);
215 if (plat->ich_version == 7) {
216 struct ich7_spi_regs *ich7_spi;
218 ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
219 ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK;
220 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
221 ctlr->menubytes = sizeof(ich7_spi->opmenu);
222 ctlr->optype = offsetof(struct ich7_spi_regs, optype);
223 ctlr->addr = offsetof(struct ich7_spi_regs, spia);
224 ctlr->data = offsetof(struct ich7_spi_regs, spid);
225 ctlr->databytes = sizeof(ich7_spi->spid);
226 ctlr->status = offsetof(struct ich7_spi_regs, spis);
227 ctlr->control = offsetof(struct ich7_spi_regs, spic);
228 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
229 ctlr->preop = offsetof(struct ich7_spi_regs, preop);
230 ctlr->base = ich7_spi;
231 } else if (plat->ich_version == 9) {
232 struct ich9_spi_regs *ich9_spi;
235 ich9_spi = (struct ich9_spi_regs *)sbase;
237 ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
238 ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
239 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
240 ctlr->menubytes = sizeof(ich9_spi->opmenu);
241 ctlr->optype = offsetof(struct ich9_spi_regs, optype);
242 ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
243 ctlr->data = offsetof(struct ich9_spi_regs, fdata);
244 ctlr->databytes = sizeof(ich9_spi->fdata);
245 ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
246 ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
247 ctlr->speed = ctlr->control + 2;
248 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
249 ctlr->preop = offsetof(struct ich9_spi_regs, preop);
250 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
251 ctlr->pr = &ich9_spi->pr[0];
252 ctlr->base = ich9_spi;
254 debug("ICH SPI: Unrecognised ICH version %d\n",
259 /* Work out the maximum speed we can support */
260 ctlr->max_speed = 20000000;
261 if (plat->ich_version == 9 && ich9_can_do_33mhz(plat->dev))
262 ctlr->max_speed = 33000000;
263 debug("ICH SPI: Version %d detected at %p, speed %ld\n",
264 plat->ich_version, ctlr->base, ctlr->max_speed);
266 ich_set_bbar(ctlr, 0);
271 static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
274 trans->bytesout -= bytes;
277 static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
280 trans->bytesin -= bytes;
283 static void spi_setup_type(struct spi_trans *trans, int data_bytes)
287 /* Try to guess spi type from read/write sizes. */
288 if (trans->bytesin == 0) {
289 if (trans->bytesout + data_bytes > 4)
291 * If bytesin = 0 and bytesout > 4, we presume this is
292 * a write data operation, which is accompanied by an
295 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
297 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
301 if (trans->bytesout == 1) { /* and bytesin is > 0 */
302 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
306 if (trans->bytesout == 4) /* and bytesin is > 0 */
307 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
309 /* Fast read command is called with 5 bytes instead of 4 */
310 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
311 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
316 static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans)
319 uint8_t opmenu[ctlr->menubytes];
321 trans->opcode = trans->out[0];
322 spi_use_out(trans, 1);
323 if (!ctlr->ichspi_lock) {
324 /* The lock is off, so just use index 0. */
325 ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
326 optypes = ich_readw(ctlr, ctlr->optype);
327 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
328 ich_writew(ctlr, optypes, ctlr->optype);
331 /* The lock is on. See if what we need is on the menu. */
333 uint16_t opcode_index;
335 /* Write Enable is handled as atomic prefix */
336 if (trans->opcode == SPI_OPCODE_WREN)
339 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
340 for (opcode_index = 0; opcode_index < ctlr->menubytes;
342 if (opmenu[opcode_index] == trans->opcode)
346 if (opcode_index == ctlr->menubytes) {
347 printf("ICH SPI: Opcode %x not found\n",
352 optypes = ich_readw(ctlr, ctlr->optype);
353 optype = (optypes >> (opcode_index * 2)) & 0x3;
354 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
355 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
356 trans->bytesout >= 3) {
357 /* We guessed wrong earlier. Fix it up. */
358 trans->type = optype;
360 if (optype != trans->type) {
361 printf("ICH SPI: Transaction doesn't fit type %d\n",
369 static int spi_setup_offset(struct spi_trans *trans)
371 /* Separate the SPI address and data. */
372 switch (trans->type) {
373 case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
374 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
376 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
377 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
378 trans->offset = ((uint32_t)trans->out[0] << 16) |
379 ((uint32_t)trans->out[1] << 8) |
380 ((uint32_t)trans->out[2] << 0);
381 spi_use_out(trans, 3);
384 printf("Unrecognized SPI transaction type %#x\n", trans->type);
390 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
391 * below is true) or 0. In case the wait was for the bit(s) to set - write
392 * those bits back, which would cause resetting them.
394 * Return the last read status value on success or -1 on failure.
396 static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
399 int timeout = 600000; /* This will result in 6s */
403 status = ich_readw(ctlr, ctlr->status);
404 if (wait_til_set ^ ((status & bitmask) == 0)) {
406 ich_writew(ctlr, status & bitmask,
414 printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
419 static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
420 const void *dout, void *din, unsigned long flags)
422 struct udevice *bus = dev_get_parent(dev);
423 struct ich_spi_platdata *plat = dev_get_platdata(bus);
424 struct ich_spi_priv *ctlr = dev_get_priv(bus);
426 int16_t opcode_index;
429 int bytes = bitlen / 8;
430 struct spi_trans *trans = &ctlr->trans;
431 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
435 /* We don't support writing partial bytes */
437 debug("ICH SPI: Accessing partial bytes not supported\n");
438 return -EPROTONOSUPPORT;
441 /* An empty end transaction can be ignored */
442 if (type == SPI_XFER_END && !dout && !din)
445 if (type & SPI_XFER_BEGIN)
446 memset(trans, '\0', sizeof(*trans));
448 /* Dp we need to come back later to finish it? */
449 if (dout && type == SPI_XFER_BEGIN) {
450 if (bytes > ICH_MAX_CMD_LEN) {
451 debug("ICH SPI: Command length limit exceeded\n");
454 memcpy(trans->cmd, dout, bytes);
455 trans->cmd_len = bytes;
456 debug_trace("ICH SPI: Saved %d bytes\n", bytes);
461 * We process a 'middle' spi_xfer() call, which has no
462 * SPI_XFER_BEGIN/END, as an independent transaction as if it had
463 * an end. We therefore repeat the command. This is because ICH
464 * seems to have no support for this, or because interest (in digging
465 * out the details and creating a special case in the code) is low.
467 if (trans->cmd_len) {
468 trans->out = trans->cmd;
469 trans->bytesout = trans->cmd_len;
471 debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len);
474 trans->bytesout = dout ? bytes : 0;
478 trans->bytesin = din ? bytes : 0;
480 /* There has to always at least be an opcode. */
481 if (!trans->bytesout) {
482 debug("ICH SPI: No opcode for transfer\n");
486 ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
490 if (plat->ich_version == 7)
491 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
493 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
495 spi_setup_type(trans, using_cmd ? bytes : 0);
496 opcode_index = spi_setup_opcode(ctlr, trans);
497 if (opcode_index < 0)
499 with_address = spi_setup_offset(trans);
500 if (with_address < 0)
503 if (trans->opcode == SPI_OPCODE_WREN) {
505 * Treat Write Enable as Atomic Pre-Op if possible
506 * in order to prevent the Management Engine from
507 * issuing a transaction between WREN and DATA.
509 if (!ctlr->ichspi_lock)
510 ich_writew(ctlr, trans->opcode, ctlr->preop);
514 if (ctlr->speed && ctlr->max_speed >= 33000000) {
517 byte = ich_readb(ctlr, ctlr->speed);
518 if (ctlr->cur_speed >= 33000000)
519 byte |= SSFC_SCF_33MHZ;
521 byte &= ~SSFC_SCF_33MHZ;
522 ich_writeb(ctlr, byte, ctlr->speed);
525 /* See if we have used up the command data */
526 if (using_cmd && dout && bytes) {
528 trans->bytesout = bytes;
529 debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes);
532 /* Preset control fields */
533 control = ich_readw(ctlr, ctlr->control);
534 control &= ~SSFC_RESERVED;
535 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
537 /* Issue atomic preop cycle if needed */
538 if (ich_readw(ctlr, ctlr->preop))
541 if (!trans->bytesout && !trans->bytesin) {
542 /* SPI addresses are 24 bit only */
544 ich_writel(ctlr, trans->offset & 0x00FFFFFF,
548 * This is a 'no data' command (like Write Enable), its
549 * bitesout size was 1, decremented to zero while executing
550 * spi_setup_opcode() above. Tell the chip to send the
553 ich_writew(ctlr, control, ctlr->control);
555 /* wait for the result */
556 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
560 if (status & SPIS_FCERR) {
561 debug("ICH SPI: Command transaction error\n");
569 * Check if this is a write command atempting to transfer more bytes
570 * than the controller can handle. Iterations for writes are not
571 * supported here because each SPI write command needs to be preceded
572 * and followed by other SPI commands, and this sequence is controlled
573 * by the SPI chip driver.
575 if (trans->bytesout > ctlr->databytes) {
576 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
581 * Read or write up to databytes bytes at a time until everything has
584 while (trans->bytesout || trans->bytesin) {
585 uint32_t data_length;
587 /* SPI addresses are 24 bit only */
588 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
591 data_length = min(trans->bytesout, ctlr->databytes);
593 data_length = min(trans->bytesin, ctlr->databytes);
595 /* Program data into FDATA0 to N */
596 if (trans->bytesout) {
597 write_reg(ctlr, trans->out, ctlr->data, data_length);
598 spi_use_out(trans, data_length);
600 trans->offset += data_length;
603 /* Add proper control fields' values */
604 control &= ~((ctlr->databytes - 1) << 8);
606 control |= (data_length - 1) << 8;
609 ich_writew(ctlr, control, ctlr->control);
611 /* Wait for Cycle Done Status or Flash Cycle Error. */
612 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
616 if (status & SPIS_FCERR) {
617 debug("ICH SPI: Data transaction error %x\n", status);
621 if (trans->bytesin) {
622 read_reg(ctlr, ctlr->data, trans->in, data_length);
623 spi_use_in(trans, data_length);
625 trans->offset += data_length;
629 /* Clear atomic preop now that xfer is done */
630 ich_writew(ctlr, 0, ctlr->preop);
636 * This uses the SPI controller from the Intel Cougar Point and Panther Point
637 * PCH to write-protect portions of the SPI flash until reboot. The changes
638 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's
641 int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit,
642 uint32_t length, int hint)
644 struct udevice *bus = dev->parent;
645 struct ich_spi_priv *ctlr = dev_get_priv(bus);
647 uint32_t upper_limit;
650 printf("%s: operation not supported on this chipset\n",
656 lower_limit > (0xFFFFFFFFUL - length) + 1 ||
657 hint < 0 || hint > 4) {
658 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__,
659 lower_limit, length, hint);
663 upper_limit = lower_limit + length - 1;
666 * Determine bits to write, as follows:
667 * 31 Write-protection enable (includes erase operation)
669 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff)
670 * 15 Read-protection enable
672 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000)
674 tmplong = 0x80000000 |
675 ((upper_limit & 0x01fff000) << 4) |
676 ((lower_limit & 0x01fff000) >> 12);
678 printf("%s: writing 0x%08x to %p\n", __func__, tmplong,
680 ctlr->pr[hint] = tmplong;
685 static int ich_spi_probe(struct udevice *bus)
687 struct ich_spi_platdata *plat = dev_get_platdata(bus);
688 struct ich_spi_priv *priv = dev_get_priv(bus);
692 ret = ich_init_controller(plat, priv);
696 * Disable the BIOS write protect so write commands are allowed. On
697 * v9, deassert SMM BIOS Write Protect Disable.
699 if (plat->use_sbase) {
700 bios_cntl = ich_readb(priv, priv->bcr);
701 bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
702 bios_cntl |= 1; /* Write Protect Disable (WPD) */
703 ich_writeb(priv, bios_cntl, priv->bcr);
705 pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
706 if (plat->ich_version == 9)
707 bios_cntl &= ~BIT(5);
708 pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
711 priv->cur_speed = priv->max_speed;
716 static int ich_spi_ofdata_to_platdata(struct udevice *bus)
718 struct ich_spi_platdata *plat = dev_get_platdata(bus);
721 ret = ich_find_spi_controller(plat);
728 static int ich_spi_set_speed(struct udevice *bus, uint speed)
730 struct ich_spi_priv *priv = dev_get_priv(bus);
732 priv->cur_speed = speed;
737 static int ich_spi_set_mode(struct udevice *bus, uint mode)
739 debug("%s: mode=%d\n", __func__, mode);
744 static int ich_spi_child_pre_probe(struct udevice *dev)
746 struct udevice *bus = dev_get_parent(dev);
747 struct ich_spi_platdata *plat = dev_get_platdata(bus);
748 struct ich_spi_priv *priv = dev_get_priv(bus);
749 struct spi_slave *slave = dev_get_parent_priv(dev);
752 * Yes this controller can only write a small number of bytes at
753 * once! The limit is typically 64 bytes.
755 slave->max_write_size = priv->databytes;
757 * ICH 7 SPI controller only supports array read command
758 * and byte program command for SST flash
760 if (plat->ich_version == 7) {
761 slave->mode_rx = SPI_RX_SLOW;
762 slave->mode = SPI_TX_BYTE;
768 static const struct dm_spi_ops ich_spi_ops = {
769 .xfer = ich_spi_xfer,
770 .set_speed = ich_spi_set_speed,
771 .set_mode = ich_spi_set_mode,
773 * cs_info is not needed, since we require all chip selects to be
774 * in the device tree explicitly
778 static const struct udevice_id ich_spi_ids[] = {
779 { .compatible = "intel,ich-spi" },
783 U_BOOT_DRIVER(ich_spi) = {
786 .of_match = ich_spi_ids,
788 .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
789 .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
790 .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
791 .child_pre_probe = ich_spi_child_pre_probe,
792 .probe = ich_spi_probe,