2 * Copyright (c) 2011-12 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
6 * This file is derived from the flashrom project.
22 #define debug_trace(fmt, args...) debug(fmt, ##args)
24 #define debug_trace(x, args...)
27 static u8 ich_readb(struct ich_spi_priv *priv, int reg)
29 u8 value = readb(priv->base + reg);
31 debug_trace("read %2.2x from %4.4x\n", value, reg);
36 static u16 ich_readw(struct ich_spi_priv *priv, int reg)
38 u16 value = readw(priv->base + reg);
40 debug_trace("read %4.4x from %4.4x\n", value, reg);
45 static u32 ich_readl(struct ich_spi_priv *priv, int reg)
47 u32 value = readl(priv->base + reg);
49 debug_trace("read %8.8x from %4.4x\n", value, reg);
54 static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
56 writeb(value, priv->base + reg);
57 debug_trace("wrote %2.2x to %4.4x\n", value, reg);
60 static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
62 writew(value, priv->base + reg);
63 debug_trace("wrote %4.4x to %4.4x\n", value, reg);
66 static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
68 writel(value, priv->base + reg);
69 debug_trace("wrote %8.8x to %4.4x\n", value, reg);
72 static void write_reg(struct ich_spi_priv *priv, const void *value,
73 int dest_reg, uint32_t size)
75 memcpy_toio(priv->base + dest_reg, value, size);
78 static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
81 memcpy_fromio(value, priv->base + src_reg, size);
84 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
86 const uint32_t bbar_mask = 0x00ffff00;
90 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
91 ichspi_bbar |= minaddr;
92 ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
95 /* @return 1 if the SPI flash supports the 33MHz speed */
96 static int ich9_can_do_33mhz(struct udevice *dev)
100 /* Observe SPI Descriptor Component Section 0 */
101 dm_pci_write_config32(dev->parent, 0xb0, 0x1000);
103 /* Extract the Write/Erase SPI Frequency from descriptor */
104 dm_pci_read_config32(dev->parent, 0xb4, &fdod);
106 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
107 speed = (fdod >> 21) & 7;
112 static int ich_init_controller(struct udevice *dev,
113 struct ich_spi_platdata *plat,
114 struct ich_spi_priv *ctlr)
119 /* SBASE is similar */
120 pch_get_sbase(dev->parent, &sbase_addr);
121 sbase = (void *)sbase_addr;
122 debug("%s: sbase=%p\n", __func__, sbase);
124 if (plat->ich_version == PCHV_7) {
125 struct ich7_spi_regs *ich7_spi = sbase;
127 ich7_spi = (struct ich7_spi_regs *)sbase;
128 ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK;
129 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
130 ctlr->menubytes = sizeof(ich7_spi->opmenu);
131 ctlr->optype = offsetof(struct ich7_spi_regs, optype);
132 ctlr->addr = offsetof(struct ich7_spi_regs, spia);
133 ctlr->data = offsetof(struct ich7_spi_regs, spid);
134 ctlr->databytes = sizeof(ich7_spi->spid);
135 ctlr->status = offsetof(struct ich7_spi_regs, spis);
136 ctlr->control = offsetof(struct ich7_spi_regs, spic);
137 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
138 ctlr->preop = offsetof(struct ich7_spi_regs, preop);
139 ctlr->base = ich7_spi;
140 } else if (plat->ich_version == PCHV_9) {
141 struct ich9_spi_regs *ich9_spi = sbase;
143 ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
144 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
145 ctlr->menubytes = sizeof(ich9_spi->opmenu);
146 ctlr->optype = offsetof(struct ich9_spi_regs, optype);
147 ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
148 ctlr->data = offsetof(struct ich9_spi_regs, fdata);
149 ctlr->databytes = sizeof(ich9_spi->fdata);
150 ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
151 ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
152 ctlr->speed = ctlr->control + 2;
153 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
154 ctlr->preop = offsetof(struct ich9_spi_regs, preop);
155 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
156 ctlr->pr = &ich9_spi->pr[0];
157 ctlr->base = ich9_spi;
159 debug("ICH SPI: Unrecognised ICH version %d\n",
164 /* Work out the maximum speed we can support */
165 ctlr->max_speed = 20000000;
166 if (plat->ich_version == PCHV_9 && ich9_can_do_33mhz(dev))
167 ctlr->max_speed = 33000000;
168 debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
169 plat->ich_version, ctlr->base, ctlr->max_speed);
171 ich_set_bbar(ctlr, 0);
176 static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
179 trans->bytesout -= bytes;
182 static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
185 trans->bytesin -= bytes;
188 static void spi_setup_type(struct spi_trans *trans, int data_bytes)
192 /* Try to guess spi type from read/write sizes */
193 if (trans->bytesin == 0) {
194 if (trans->bytesout + data_bytes > 4)
196 * If bytesin = 0 and bytesout > 4, we presume this is
197 * a write data operation, which is accompanied by an
200 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
202 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
206 if (trans->bytesout == 1) { /* and bytesin is > 0 */
207 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
211 if (trans->bytesout == 4) /* and bytesin is > 0 */
212 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
214 /* Fast read command is called with 5 bytes instead of 4 */
215 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
216 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
221 static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans)
224 uint8_t opmenu[ctlr->menubytes];
226 trans->opcode = trans->out[0];
227 spi_use_out(trans, 1);
228 if (!ctlr->ichspi_lock) {
229 /* The lock is off, so just use index 0. */
230 ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
231 optypes = ich_readw(ctlr, ctlr->optype);
232 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
233 ich_writew(ctlr, optypes, ctlr->optype);
236 /* The lock is on. See if what we need is on the menu. */
238 uint16_t opcode_index;
240 /* Write Enable is handled as atomic prefix */
241 if (trans->opcode == SPI_OPCODE_WREN)
244 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
245 for (opcode_index = 0; opcode_index < ctlr->menubytes;
247 if (opmenu[opcode_index] == trans->opcode)
251 if (opcode_index == ctlr->menubytes) {
252 printf("ICH SPI: Opcode %x not found\n",
257 optypes = ich_readw(ctlr, ctlr->optype);
258 optype = (optypes >> (opcode_index * 2)) & 0x3;
259 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
260 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
261 trans->bytesout >= 3) {
262 /* We guessed wrong earlier. Fix it up. */
263 trans->type = optype;
265 if (optype != trans->type) {
266 printf("ICH SPI: Transaction doesn't fit type %d\n",
274 static int spi_setup_offset(struct spi_trans *trans)
276 /* Separate the SPI address and data */
277 switch (trans->type) {
278 case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
279 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
281 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
282 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
283 trans->offset = ((uint32_t)trans->out[0] << 16) |
284 ((uint32_t)trans->out[1] << 8) |
285 ((uint32_t)trans->out[2] << 0);
286 spi_use_out(trans, 3);
289 printf("Unrecognized SPI transaction type %#x\n", trans->type);
295 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
296 * below is true) or 0. In case the wait was for the bit(s) to set - write
297 * those bits back, which would cause resetting them.
299 * Return the last read status value on success or -1 on failure.
301 static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
304 int timeout = 600000; /* This will result in 6s */
308 status = ich_readw(ctlr, ctlr->status);
309 if (wait_til_set ^ ((status & bitmask) == 0)) {
311 ich_writew(ctlr, status & bitmask,
319 printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
324 static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
325 const void *dout, void *din, unsigned long flags)
327 struct udevice *bus = dev_get_parent(dev);
328 struct ich_spi_platdata *plat = dev_get_platdata(bus);
329 struct ich_spi_priv *ctlr = dev_get_priv(bus);
331 int16_t opcode_index;
334 int bytes = bitlen / 8;
335 struct spi_trans *trans = &ctlr->trans;
336 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
340 /* We don't support writing partial bytes */
342 debug("ICH SPI: Accessing partial bytes not supported\n");
343 return -EPROTONOSUPPORT;
346 /* An empty end transaction can be ignored */
347 if (type == SPI_XFER_END && !dout && !din)
350 if (type & SPI_XFER_BEGIN)
351 memset(trans, '\0', sizeof(*trans));
353 /* Dp we need to come back later to finish it? */
354 if (dout && type == SPI_XFER_BEGIN) {
355 if (bytes > ICH_MAX_CMD_LEN) {
356 debug("ICH SPI: Command length limit exceeded\n");
359 memcpy(trans->cmd, dout, bytes);
360 trans->cmd_len = bytes;
361 debug_trace("ICH SPI: Saved %d bytes\n", bytes);
366 * We process a 'middle' spi_xfer() call, which has no
367 * SPI_XFER_BEGIN/END, as an independent transaction as if it had
368 * an end. We therefore repeat the command. This is because ICH
369 * seems to have no support for this, or because interest (in digging
370 * out the details and creating a special case in the code) is low.
372 if (trans->cmd_len) {
373 trans->out = trans->cmd;
374 trans->bytesout = trans->cmd_len;
376 debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len);
379 trans->bytesout = dout ? bytes : 0;
383 trans->bytesin = din ? bytes : 0;
385 /* There has to always at least be an opcode */
386 if (!trans->bytesout) {
387 debug("ICH SPI: No opcode for transfer\n");
391 ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
395 if (plat->ich_version == PCHV_7)
396 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
398 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
400 spi_setup_type(trans, using_cmd ? bytes : 0);
401 opcode_index = spi_setup_opcode(ctlr, trans);
402 if (opcode_index < 0)
404 with_address = spi_setup_offset(trans);
405 if (with_address < 0)
408 if (trans->opcode == SPI_OPCODE_WREN) {
410 * Treat Write Enable as Atomic Pre-Op if possible
411 * in order to prevent the Management Engine from
412 * issuing a transaction between WREN and DATA.
414 if (!ctlr->ichspi_lock)
415 ich_writew(ctlr, trans->opcode, ctlr->preop);
419 if (ctlr->speed && ctlr->max_speed >= 33000000) {
422 byte = ich_readb(ctlr, ctlr->speed);
423 if (ctlr->cur_speed >= 33000000)
424 byte |= SSFC_SCF_33MHZ;
426 byte &= ~SSFC_SCF_33MHZ;
427 ich_writeb(ctlr, byte, ctlr->speed);
430 /* See if we have used up the command data */
431 if (using_cmd && dout && bytes) {
433 trans->bytesout = bytes;
434 debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes);
437 /* Preset control fields */
438 control = ich_readw(ctlr, ctlr->control);
439 control &= ~SSFC_RESERVED;
440 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
442 /* Issue atomic preop cycle if needed */
443 if (ich_readw(ctlr, ctlr->preop))
446 if (!trans->bytesout && !trans->bytesin) {
447 /* SPI addresses are 24 bit only */
449 ich_writel(ctlr, trans->offset & 0x00FFFFFF,
453 * This is a 'no data' command (like Write Enable), its
454 * bitesout size was 1, decremented to zero while executing
455 * spi_setup_opcode() above. Tell the chip to send the
458 ich_writew(ctlr, control, ctlr->control);
460 /* wait for the result */
461 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
465 if (status & SPIS_FCERR) {
466 debug("ICH SPI: Command transaction error\n");
474 * Check if this is a write command atempting to transfer more bytes
475 * than the controller can handle. Iterations for writes are not
476 * supported here because each SPI write command needs to be preceded
477 * and followed by other SPI commands, and this sequence is controlled
478 * by the SPI chip driver.
480 if (trans->bytesout > ctlr->databytes) {
481 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
486 * Read or write up to databytes bytes at a time until everything has
489 while (trans->bytesout || trans->bytesin) {
490 uint32_t data_length;
492 /* SPI addresses are 24 bit only */
493 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
496 data_length = min(trans->bytesout, ctlr->databytes);
498 data_length = min(trans->bytesin, ctlr->databytes);
500 /* Program data into FDATA0 to N */
501 if (trans->bytesout) {
502 write_reg(ctlr, trans->out, ctlr->data, data_length);
503 spi_use_out(trans, data_length);
505 trans->offset += data_length;
508 /* Add proper control fields' values */
509 control &= ~((ctlr->databytes - 1) << 8);
511 control |= (data_length - 1) << 8;
514 ich_writew(ctlr, control, ctlr->control);
516 /* Wait for Cycle Done Status or Flash Cycle Error */
517 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
521 if (status & SPIS_FCERR) {
522 debug("ICH SPI: Data transaction error %x\n", status);
526 if (trans->bytesin) {
527 read_reg(ctlr, ctlr->data, trans->in, data_length);
528 spi_use_in(trans, data_length);
530 trans->offset += data_length;
534 /* Clear atomic preop now that xfer is done */
535 ich_writew(ctlr, 0, ctlr->preop);
541 * This uses the SPI controller from the Intel Cougar Point and Panther Point
542 * PCH to write-protect portions of the SPI flash until reboot. The changes
543 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's
546 int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit,
547 uint32_t length, int hint)
549 struct udevice *bus = dev->parent;
550 struct ich_spi_priv *ctlr = dev_get_priv(bus);
552 uint32_t upper_limit;
555 printf("%s: operation not supported on this chipset\n",
561 lower_limit > (0xFFFFFFFFUL - length) + 1 ||
562 hint < 0 || hint > 4) {
563 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__,
564 lower_limit, length, hint);
568 upper_limit = lower_limit + length - 1;
571 * Determine bits to write, as follows:
572 * 31 Write-protection enable (includes erase operation)
574 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff)
575 * 15 Read-protection enable
577 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000)
579 tmplong = 0x80000000 |
580 ((upper_limit & 0x01fff000) << 4) |
581 ((lower_limit & 0x01fff000) >> 12);
583 printf("%s: writing 0x%08x to %p\n", __func__, tmplong,
585 ctlr->pr[hint] = tmplong;
590 static int ich_spi_probe(struct udevice *dev)
592 struct ich_spi_platdata *plat = dev_get_platdata(dev);
593 struct ich_spi_priv *priv = dev_get_priv(dev);
597 /* Check the ICH version */
598 plat->ich_version = pch_get_version(dev->parent);
600 ret = ich_init_controller(dev, plat, priv);
603 /* Disable the BIOS write protect so write commands are allowed */
604 ret = pch_set_spi_protect(dev->parent, false);
605 if (ret == -ENOSYS) {
606 bios_cntl = ich_readb(priv, priv->bcr);
607 bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
608 bios_cntl |= 1; /* Write Protect Disable (WPD) */
609 ich_writeb(priv, bios_cntl, priv->bcr);
611 debug("%s: Failed to disable write-protect: err=%d\n",
616 priv->cur_speed = priv->max_speed;
621 static int ich_spi_set_speed(struct udevice *bus, uint speed)
623 struct ich_spi_priv *priv = dev_get_priv(bus);
625 priv->cur_speed = speed;
630 static int ich_spi_set_mode(struct udevice *bus, uint mode)
632 debug("%s: mode=%d\n", __func__, mode);
637 static int ich_spi_child_pre_probe(struct udevice *dev)
639 struct udevice *bus = dev_get_parent(dev);
640 struct ich_spi_platdata *plat = dev_get_platdata(bus);
641 struct ich_spi_priv *priv = dev_get_priv(bus);
642 struct spi_slave *slave = dev_get_parent_priv(dev);
645 * Yes this controller can only write a small number of bytes at
646 * once! The limit is typically 64 bytes.
648 slave->max_write_size = priv->databytes;
650 * ICH 7 SPI controller only supports array read command
651 * and byte program command for SST flash
653 if (plat->ich_version == PCHV_7) {
654 slave->mode_rx = SPI_RX_SLOW;
655 slave->mode = SPI_TX_BYTE;
661 static const struct dm_spi_ops ich_spi_ops = {
662 .xfer = ich_spi_xfer,
663 .set_speed = ich_spi_set_speed,
664 .set_mode = ich_spi_set_mode,
666 * cs_info is not needed, since we require all chip selects to be
667 * in the device tree explicitly
671 static const struct udevice_id ich_spi_ids[] = {
672 { .compatible = "intel,ich-spi" },
676 U_BOOT_DRIVER(ich_spi) = {
679 .of_match = ich_spi_ids,
681 .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
682 .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
683 .child_pre_probe = ich_spi_child_pre_probe,
684 .probe = ich_spi_probe,