1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011-12 The Chromium OS Authors.
5 * This file is derived from the flashrom project.
8 #define LOG_CATEGORY UCLASS_SPI
13 #include <dt-structs.h>
20 #include <spi_flash.h>
23 #include <asm/fast_spi.h>
26 #include <linux/sizes.h>
31 #define debug_trace(fmt, args...) debug(fmt, ##args)
33 #define debug_trace(x, args...)
36 struct ich_spi_platdata {
37 #if CONFIG_IS_ENABLED(OF_PLATDATA)
38 struct dtd_intel_fast_spi dtplat;
40 enum ich_version ich_version; /* Controller version, 7 or 9 */
41 bool lockdown; /* lock down controller settings? */
42 ulong mmio_base; /* Base of MMIO registers */
43 pci_dev_t bdf; /* PCI address used by of-platdata */
44 bool hwseq; /* Use hardware sequencing (not s/w) */
47 static u8 ich_readb(struct ich_spi_priv *priv, int reg)
49 u8 value = readb(priv->base + reg);
51 debug_trace("read %2.2x from %4.4x\n", value, reg);
56 static u16 ich_readw(struct ich_spi_priv *priv, int reg)
58 u16 value = readw(priv->base + reg);
60 debug_trace("read %4.4x from %4.4x\n", value, reg);
65 static u32 ich_readl(struct ich_spi_priv *priv, int reg)
67 u32 value = readl(priv->base + reg);
69 debug_trace("read %8.8x from %4.4x\n", value, reg);
74 static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
76 writeb(value, priv->base + reg);
77 debug_trace("wrote %2.2x to %4.4x\n", value, reg);
80 static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
82 writew(value, priv->base + reg);
83 debug_trace("wrote %4.4x to %4.4x\n", value, reg);
86 static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
88 writel(value, priv->base + reg);
89 debug_trace("wrote %8.8x to %4.4x\n", value, reg);
92 static void write_reg(struct ich_spi_priv *priv, const void *value,
93 int dest_reg, uint32_t size)
95 memcpy_toio(priv->base + dest_reg, value, size);
98 static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
101 memcpy_fromio(value, priv->base + src_reg, size);
104 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
106 const uint32_t bbar_mask = 0x00ffff00;
107 uint32_t ichspi_bbar;
110 minaddr &= bbar_mask;
111 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
112 ichspi_bbar |= minaddr;
113 ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
117 /* @return 1 if the SPI flash supports the 33MHz speed */
118 static bool ich9_can_do_33mhz(struct udevice *dev)
120 struct ich_spi_priv *priv = dev_get_priv(dev);
123 if (!CONFIG_IS_ENABLED(PCI))
125 /* Observe SPI Descriptor Component Section 0 */
126 dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
128 /* Extract the Write/Erase SPI Frequency from descriptor */
129 dm_pci_read_config32(priv->pch, 0xb4, &fdod);
131 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
132 speed = (fdod >> 21) & 7;
137 static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
139 if (plat->ich_version == ICHV_7) {
140 struct ich7_spi_regs *ich7_spi = sbase;
142 setbits_le16(&ich7_spi->spis, SPIS_LOCK);
143 } else if (plat->ich_version == ICHV_9) {
144 struct ich9_spi_regs *ich9_spi = sbase;
146 setbits_le16(&ich9_spi->hsfs, HSFS_FLOCKDN);
150 static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
154 if (plat->ich_version == ICHV_7) {
155 struct ich7_spi_regs *ich7_spi = sbase;
157 lock = readw(&ich7_spi->spis) & SPIS_LOCK;
158 } else if (plat->ich_version == ICHV_9) {
159 struct ich9_spi_regs *ich9_spi = sbase;
161 lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
167 static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
171 uint8_t opmenu[ctlr->menubytes];
174 /* The lock is off, so just use index 0. */
175 ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
176 optypes = ich_readw(ctlr, ctlr->optype);
177 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
178 ich_writew(ctlr, optypes, ctlr->optype);
181 /* The lock is on. See if what we need is on the menu. */
183 uint16_t opcode_index;
185 /* Write Enable is handled as atomic prefix */
186 if (trans->opcode == SPI_OPCODE_WREN)
189 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
190 for (opcode_index = 0; opcode_index < ctlr->menubytes;
192 if (opmenu[opcode_index] == trans->opcode)
196 if (opcode_index == ctlr->menubytes) {
197 debug("ICH SPI: Opcode %x not found\n", trans->opcode);
201 optypes = ich_readw(ctlr, ctlr->optype);
202 optype = (optypes >> (opcode_index * 2)) & 0x3;
204 if (optype != trans->type) {
205 debug("ICH SPI: Transaction doesn't fit type %d\n",
214 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
215 * below is true) or 0. In case the wait was for the bit(s) to set - write
216 * those bits back, which would cause resetting them.
218 * Return the last read status value on success or -1 on failure.
220 static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
223 int timeout = 600000; /* This will result in 6s */
227 status = ich_readw(ctlr, ctlr->status);
228 if (wait_til_set ^ ((status & bitmask) == 0)) {
230 ich_writew(ctlr, status & bitmask,
237 debug("ICH SPI: SCIP timeout, read %x, expected %x, wts %x %x\n",
238 status, bitmask, wait_til_set, status & bitmask);
243 static void ich_spi_config_opcode(struct udevice *dev)
245 struct ich_spi_priv *ctlr = dev_get_priv(dev);
248 * PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down
249 * to prevent accidental or intentional writes. Before they get
250 * locked down, these registers should be initialized properly.
252 ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
253 ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
254 ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
255 ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
258 static int ich_spi_exec_op_swseq(struct spi_slave *slave,
259 const struct spi_mem_op *op)
261 struct udevice *bus = dev_get_parent(slave->dev);
262 struct ich_spi_platdata *plat = dev_get_platdata(bus);
263 struct ich_spi_priv *ctlr = dev_get_priv(bus);
265 int16_t opcode_index;
268 struct spi_trans *trans = &ctlr->trans;
269 bool lock = spi_lock_status(plat, ctlr->base);
276 if (op->data.nbytes) {
277 if (op->data.dir == SPI_MEM_DATA_IN) {
278 trans->in = op->data.buf.in;
279 trans->bytesin = op->data.nbytes;
281 trans->out = op->data.buf.out;
282 trans->bytesout = op->data.nbytes;
286 if (trans->opcode != op->cmd.opcode)
287 trans->opcode = op->cmd.opcode;
289 if (lock && trans->opcode == SPI_OPCODE_WRDIS)
292 if (trans->opcode == SPI_OPCODE_WREN) {
294 * Treat Write Enable as Atomic Pre-Op if possible
295 * in order to prevent the Management Engine from
296 * issuing a transaction between WREN and DATA.
299 ich_writew(ctlr, trans->opcode, ctlr->preop);
303 ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
307 if (plat->ich_version == ICHV_7)
308 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
310 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
312 /* Try to guess spi transaction type */
313 if (op->data.dir == SPI_MEM_DATA_OUT) {
315 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
317 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
320 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
322 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
324 /* Special erase case handling */
325 if (op->addr.nbytes && !op->data.buswidth)
326 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
328 opcode_index = spi_setup_opcode(ctlr, trans, lock);
329 if (opcode_index < 0)
332 if (op->addr.nbytes) {
333 trans->offset = op->addr.val;
337 if (ctlr->speed && ctlr->max_speed >= 33000000) {
340 byte = ich_readb(ctlr, ctlr->speed);
341 if (ctlr->cur_speed >= 33000000)
342 byte |= SSFC_SCF_33MHZ;
344 byte &= ~SSFC_SCF_33MHZ;
345 ich_writeb(ctlr, byte, ctlr->speed);
348 /* Preset control fields */
349 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
351 /* Issue atomic preop cycle if needed */
352 if (ich_readw(ctlr, ctlr->preop))
355 if (!trans->bytesout && !trans->bytesin) {
356 /* SPI addresses are 24 bit only */
358 ich_writel(ctlr, trans->offset & 0x00FFFFFF,
362 * This is a 'no data' command (like Write Enable), its
363 * bitesout size was 1, decremented to zero while executing
364 * spi_setup_opcode() above. Tell the chip to send the
367 ich_writew(ctlr, control, ctlr->control);
369 /* wait for the result */
370 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
374 if (status & SPIS_FCERR) {
375 debug("ICH SPI: Command transaction error\n");
382 while (trans->bytesout || trans->bytesin) {
383 uint32_t data_length;
385 /* SPI addresses are 24 bit only */
386 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
389 data_length = min(trans->bytesout, ctlr->databytes);
391 data_length = min(trans->bytesin, ctlr->databytes);
393 /* Program data into FDATA0 to N */
394 if (trans->bytesout) {
395 write_reg(ctlr, trans->out, ctlr->data, data_length);
396 trans->bytesout -= data_length;
399 /* Add proper control fields' values */
400 control &= ~((ctlr->databytes - 1) << 8);
402 control |= (data_length - 1) << 8;
405 ich_writew(ctlr, control, ctlr->control);
407 /* Wait for Cycle Done Status or Flash Cycle Error */
408 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
412 if (status & SPIS_FCERR) {
413 debug("ICH SPI: Data transaction error %x\n", status);
417 if (trans->bytesin) {
418 read_reg(ctlr, ctlr->data, trans->in, data_length);
419 trans->bytesin -= data_length;
423 /* Clear atomic preop now that xfer is done */
425 ich_writew(ctlr, 0, ctlr->preop);
431 * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and
432 * that the operation does not cross page boundary.
434 static uint get_xfer_len(u32 offset, int len, int page_size)
436 uint xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE);
437 uint bytes_left = ALIGN(offset, page_size) - offset;
440 xfer_len = min(xfer_len, bytes_left);
445 /* Fill FDATAn FIFO in preparation for a write transaction */
446 static void fill_xfer_fifo(struct fast_spi_regs *regs, const void *data,
449 memcpy(regs->fdata, data, len);
452 /* Drain FDATAn FIFO after a read transaction populates data */
453 static void drain_xfer_fifo(struct fast_spi_regs *regs, void *dest, uint len)
455 memcpy(dest, regs->fdata, len);
458 /* Fire up a transfer using the hardware sequencer */
459 static void start_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle,
460 uint offset, uint len)
462 /* Make sure all W1C status bits get cleared */
465 hsfsts = readl(®s->hsfsts_ctl);
466 hsfsts &= ~(HSFSTS_FCYCLE_MASK | HSFSTS_FDBC_MASK);
467 hsfsts |= HSFSTS_AEL | HSFSTS_FCERR | HSFSTS_FDONE;
469 /* Set up transaction parameters */
470 hsfsts |= hsfsts_cycle << HSFSTS_FCYCLE_SHIFT;
471 hsfsts |= ((len - 1) << HSFSTS_FDBC_SHIFT) & HSFSTS_FDBC_MASK;
472 hsfsts |= HSFSTS_FGO;
474 writel(offset, ®s->faddr);
475 writel(hsfsts, ®s->hsfsts_ctl);
478 static int wait_for_hwseq_xfer(struct fast_spi_regs *regs, uint offset)
483 start = get_timer(0);
485 hsfsts = readl(®s->hsfsts_ctl);
486 if (hsfsts & HSFSTS_FCERR) {
487 debug("SPI transaction error at offset %x HSFSTS = %08x\n",
491 if (hsfsts & HSFSTS_AEL)
494 if (hsfsts & HSFSTS_FDONE)
496 } while (get_timer(start) < SPIBAR_HWSEQ_XFER_TIMEOUT_MS);
498 debug("SPI transaction timeout at offset %x HSFSTS = %08x, timer %d\n",
499 offset, hsfsts, (uint)get_timer(start));
505 * exec_sync_hwseq_xfer() - Execute flash transfer by hardware sequencing
507 * This waits until complete or timeout
509 * @regs: SPI registers
510 * @hsfsts_cycle: Cycle type (enum hsfsts_cycle_t)
511 * @offset: Offset to access
512 * @len: Number of bytes to transfer (can be 0)
513 * @return 0 if OK, -EIO on flash-cycle error (FCERR), -EPERM on access error
514 * (AEL), -ETIMEDOUT on timeout
516 static int exec_sync_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle,
517 uint offset, uint len)
519 start_hwseq_xfer(regs, hsfsts_cycle, offset, len);
521 return wait_for_hwseq_xfer(regs, offset);
524 static int ich_spi_exec_op_hwseq(struct spi_slave *slave,
525 const struct spi_mem_op *op)
527 struct spi_flash *flash = dev_get_uclass_priv(slave->dev);
528 struct udevice *bus = dev_get_parent(slave->dev);
529 struct ich_spi_priv *priv = dev_get_priv(bus);
530 struct fast_spi_regs *regs = priv->base;
539 offset = op->addr.val;
540 len = op->data.nbytes;
542 switch (op->cmd.opcode) {
544 cycle = HSFSTS_CYCLE_RDID;
546 case SPINOR_OP_READ_FAST:
547 cycle = HSFSTS_CYCLE_READ;
550 cycle = HSFSTS_CYCLE_WRITE;
553 /* Nothing needs to be done */
556 cycle = HSFSTS_CYCLE_WR_STATUS;
559 cycle = HSFSTS_CYCLE_RD_STATUS;
562 return 0; /* ignore */
563 case SPINOR_OP_BE_4K:
564 cycle = HSFSTS_CYCLE_4K_ERASE;
566 uint xfer_len = 0x1000;
568 ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0);
576 debug("Unknown cycle %x\n", op->cmd.opcode);
580 out = op->data.dir == SPI_MEM_DATA_OUT;
581 buf = out ? (u8 *)op->data.buf.out : op->data.buf.in;
582 page_size = flash->page_size ? : 256;
585 uint xfer_len = get_xfer_len(offset, len, page_size);
588 fill_xfer_fifo(regs, buf, xfer_len);
590 ret = exec_sync_hwseq_xfer(regs, cycle, offset, xfer_len);
595 drain_xfer_fifo(regs, buf, xfer_len);
605 static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
607 struct udevice *bus = dev_get_parent(slave->dev);
608 struct ich_spi_platdata *plat = dev_get_platdata(bus);
611 bootstage_start(BOOTSTAGE_ID_ACCUM_SPI, "fast_spi");
613 ret = ich_spi_exec_op_hwseq(slave, op);
615 ret = ich_spi_exec_op_swseq(slave, op);
616 bootstage_accum(BOOTSTAGE_ID_ACCUM_SPI);
621 static int ich_get_mmap_bus(struct udevice *bus, ulong *map_basep,
622 uint *map_sizep, uint *offsetp)
626 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
627 struct pci_child_platdata *pplat = dev_get_parent_platdata(bus);
629 spi_bdf = pplat->devfn;
631 struct ich_spi_platdata *plat = dev_get_platdata(bus);
634 * We cannot rely on plat->bdf being set up yet since this method can
635 * be called before the device is probed. Use the of-platdata directly
638 spi_bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
641 return fast_spi_get_bios_mmap(spi_bdf, map_basep, map_sizep, offsetp);
644 static int ich_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep,
647 struct udevice *bus = dev_get_parent(dev);
649 return ich_get_mmap_bus(bus, map_basep, map_sizep, offsetp);
652 static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op)
654 unsigned int page_offset;
655 int addr = op->addr.val;
656 unsigned int byte_count = op->data.nbytes;
658 if (hweight32(ICH_BOUNDARY) == 1) {
659 page_offset = addr & (ICH_BOUNDARY - 1);
663 page_offset = do_div(aux, ICH_BOUNDARY);
666 if (op->data.dir == SPI_MEM_DATA_IN) {
667 if (slave->max_read_size) {
668 op->data.nbytes = min(ICH_BOUNDARY - page_offset,
669 slave->max_read_size);
671 } else if (slave->max_write_size) {
672 op->data.nbytes = min(ICH_BOUNDARY - page_offset,
673 slave->max_write_size);
676 op->data.nbytes = min(op->data.nbytes, byte_count);
681 static int ich_protect_lockdown(struct udevice *dev)
683 struct ich_spi_platdata *plat = dev_get_platdata(dev);
684 struct ich_spi_priv *priv = dev_get_priv(dev);
687 /* Disable the BIOS write protect so write commands are allowed */
689 ret = pch_set_spi_protect(priv->pch, false);
690 if (ret == -ENOSYS) {
693 bios_cntl = ich_readb(priv, priv->bcr);
694 bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
695 bios_cntl |= 1; /* Write Protect Disable (WPD) */
696 ich_writeb(priv, bios_cntl, priv->bcr);
698 debug("%s: Failed to disable write-protect: err=%d\n",
703 /* Lock down SPI controller settings if required */
704 if (plat->lockdown) {
705 ich_spi_config_opcode(dev);
706 spi_lock_down(plat, priv->base);
712 static int ich_init_controller(struct udevice *dev,
713 struct ich_spi_platdata *plat,
714 struct ich_spi_priv *ctlr)
716 if (spl_phase() == PHASE_TPL) {
717 struct ich_spi_platdata *plat = dev_get_platdata(dev);
720 ret = fast_spi_early_init(plat->bdf, plat->mmio_base);
725 ctlr->base = (void *)plat->mmio_base;
726 if (plat->ich_version == ICHV_7) {
727 struct ich7_spi_regs *ich7_spi = ctlr->base;
729 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
730 ctlr->menubytes = sizeof(ich7_spi->opmenu);
731 ctlr->optype = offsetof(struct ich7_spi_regs, optype);
732 ctlr->addr = offsetof(struct ich7_spi_regs, spia);
733 ctlr->data = offsetof(struct ich7_spi_regs, spid);
734 ctlr->databytes = sizeof(ich7_spi->spid);
735 ctlr->status = offsetof(struct ich7_spi_regs, spis);
736 ctlr->control = offsetof(struct ich7_spi_regs, spic);
737 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
738 ctlr->preop = offsetof(struct ich7_spi_regs, preop);
739 } else if (plat->ich_version == ICHV_9) {
740 struct ich9_spi_regs *ich9_spi = ctlr->base;
742 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
743 ctlr->menubytes = sizeof(ich9_spi->opmenu);
744 ctlr->optype = offsetof(struct ich9_spi_regs, optype);
745 ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
746 ctlr->data = offsetof(struct ich9_spi_regs, fdata);
747 ctlr->databytes = sizeof(ich9_spi->fdata);
748 ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
749 ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
750 ctlr->speed = ctlr->control + 2;
751 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
752 ctlr->preop = offsetof(struct ich9_spi_regs, preop);
753 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
754 ctlr->pr = &ich9_spi->pr[0];
755 } else if (plat->ich_version == ICHV_APL) {
757 debug("ICH SPI: Unrecognised ICH version %d\n",
762 /* Work out the maximum speed we can support */
763 ctlr->max_speed = 20000000;
764 if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
765 ctlr->max_speed = 33000000;
766 debug("ICH SPI: Version ID %d detected at %lx, speed %ld\n",
767 plat->ich_version, plat->mmio_base, ctlr->max_speed);
769 ich_set_bbar(ctlr, 0);
774 static int ich_cache_bios_region(struct udevice *dev)
782 ret = ich_get_mmap_bus(dev, &map_base, &map_size, &offset);
786 /* Don't use WRBACK since we are not supposed to write to SPI flash */
787 base = SZ_4G - map_size;
788 mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size);
789 log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size);
794 static int ich_spi_probe(struct udevice *dev)
796 struct ich_spi_platdata *plat = dev_get_platdata(dev);
797 struct ich_spi_priv *priv = dev_get_priv(dev);
800 ret = ich_init_controller(dev, plat, priv);
804 if (spl_phase() == PHASE_TPL) {
805 /* Cache the BIOS to speed things up */
806 ret = ich_cache_bios_region(dev);
810 ret = ich_protect_lockdown(dev);
814 priv->cur_speed = priv->max_speed;
819 static int ich_spi_remove(struct udevice *bus)
822 * Configure SPI controller so that the Linux MTD driver can fully
823 * access the SPI NOR chip
825 ich_spi_config_opcode(bus);
830 static int ich_spi_set_speed(struct udevice *bus, uint speed)
832 struct ich_spi_priv *priv = dev_get_priv(bus);
834 priv->cur_speed = speed;
839 static int ich_spi_set_mode(struct udevice *bus, uint mode)
841 debug("%s: mode=%d\n", __func__, mode);
846 static int ich_spi_child_pre_probe(struct udevice *dev)
848 struct udevice *bus = dev_get_parent(dev);
849 struct ich_spi_platdata *plat = dev_get_platdata(bus);
850 struct ich_spi_priv *priv = dev_get_priv(bus);
851 struct spi_slave *slave = dev_get_parent_priv(dev);
854 * Yes this controller can only write a small number of bytes at
855 * once! The limit is typically 64 bytes. For hardware sequencing a
856 * a loop is used to get around this.
859 slave->max_write_size = priv->databytes;
861 * ICH 7 SPI controller only supports array read command
862 * and byte program command for SST flash
864 if (plat->ich_version == ICHV_7)
865 slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
870 static int ich_spi_ofdata_to_platdata(struct udevice *dev)
872 struct ich_spi_platdata *plat = dev_get_platdata(dev);
874 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
875 struct ich_spi_priv *priv = dev_get_priv(dev);
877 /* Find a PCH if there is one */
878 uclass_first_device(UCLASS_PCH, &priv->pch);
880 priv->pch = dev_get_parent(dev);
882 plat->ich_version = dev_get_driver_data(dev);
883 plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");
884 if (plat->ich_version == ICHV_APL) {
885 plat->mmio_base = dm_pci_read_bar32(dev, 0);
887 /* SBASE is similar */
888 pch_get_spi_base(priv->pch, &plat->mmio_base);
891 * Use an int so that the property is present in of-platdata even
894 plat->hwseq = dev_read_u32_default(dev, "intel,hardware-seq", 0);
896 plat->ich_version = ICHV_APL;
897 plat->mmio_base = plat->dtplat.early_regs[0];
898 plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
899 plat->hwseq = plat->dtplat.intel_hardware_seq;
901 debug("%s: mmio_base=%lx\n", __func__, plat->mmio_base);
906 static const struct spi_controller_mem_ops ich_controller_mem_ops = {
907 .adjust_op_size = ich_spi_adjust_size,
909 .exec_op = ich_spi_exec_op,
912 static const struct dm_spi_ops ich_spi_ops = {
913 /* xfer is not supported */
914 .set_speed = ich_spi_set_speed,
915 .set_mode = ich_spi_set_mode,
916 .mem_ops = &ich_controller_mem_ops,
917 .get_mmap = ich_get_mmap,
919 * cs_info is not needed, since we require all chip selects to be
920 * in the device tree explicitly
924 static const struct udevice_id ich_spi_ids[] = {
925 { .compatible = "intel,ich7-spi", ICHV_7 },
926 { .compatible = "intel,ich9-spi", ICHV_9 },
927 { .compatible = "intel,fast-spi", ICHV_APL },
931 U_BOOT_DRIVER(intel_fast_spi) = {
932 .name = "intel_fast_spi",
934 .of_match = ich_spi_ids,
936 .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
937 .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
938 .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
939 .child_pre_probe = ich_spi_child_pre_probe,
940 .probe = ich_spi_probe,
941 .remove = ich_spi_remove,
942 .flags = DM_FLAG_OS_PREPARE,