1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011-12 The Chromium OS Authors.
5 * This file is derived from the flashrom project.
8 #define LOG_CATEGORY UCLASS_SPI
13 #include <dt-structs.h>
20 #include <spi_flash.h>
23 #include <asm/fast_spi.h>
26 #include <linux/sizes.h>
31 #define debug_trace(fmt, args...) debug(fmt, ##args)
33 #define debug_trace(x, args...)
36 struct ich_spi_platdata {
37 #if CONFIG_IS_ENABLED(OF_PLATDATA)
38 struct dtd_intel_fast_spi dtplat;
40 enum ich_version ich_version; /* Controller version, 7 or 9 */
41 bool lockdown; /* lock down controller settings? */
42 ulong mmio_base; /* Base of MMIO registers */
43 pci_dev_t bdf; /* PCI address used by of-platdata */
44 bool hwseq; /* Use hardware sequencing (not s/w) */
47 static u8 ich_readb(struct ich_spi_priv *priv, int reg)
49 u8 value = readb(priv->base + reg);
51 debug_trace("read %2.2x from %4.4x\n", value, reg);
56 static u16 ich_readw(struct ich_spi_priv *priv, int reg)
58 u16 value = readw(priv->base + reg);
60 debug_trace("read %4.4x from %4.4x\n", value, reg);
65 static u32 ich_readl(struct ich_spi_priv *priv, int reg)
67 u32 value = readl(priv->base + reg);
69 debug_trace("read %8.8x from %4.4x\n", value, reg);
74 static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
76 writeb(value, priv->base + reg);
77 debug_trace("wrote %2.2x to %4.4x\n", value, reg);
80 static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
82 writew(value, priv->base + reg);
83 debug_trace("wrote %4.4x to %4.4x\n", value, reg);
86 static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
88 writel(value, priv->base + reg);
89 debug_trace("wrote %8.8x to %4.4x\n", value, reg);
92 static void write_reg(struct ich_spi_priv *priv, const void *value,
93 int dest_reg, uint32_t size)
95 memcpy_toio(priv->base + dest_reg, value, size);
98 static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
101 memcpy_fromio(value, priv->base + src_reg, size);
104 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
106 const uint32_t bbar_mask = 0x00ffff00;
107 uint32_t ichspi_bbar;
109 minaddr &= bbar_mask;
110 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
111 ichspi_bbar |= minaddr;
112 ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
115 /* @return 1 if the SPI flash supports the 33MHz speed */
116 static bool ich9_can_do_33mhz(struct udevice *dev)
118 struct ich_spi_priv *priv = dev_get_priv(dev);
121 if (!CONFIG_IS_ENABLED(PCI))
123 /* Observe SPI Descriptor Component Section 0 */
124 dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
126 /* Extract the Write/Erase SPI Frequency from descriptor */
127 dm_pci_read_config32(priv->pch, 0xb4, &fdod);
129 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
130 speed = (fdod >> 21) & 7;
135 static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
137 if (plat->ich_version == ICHV_7) {
138 struct ich7_spi_regs *ich7_spi = sbase;
140 setbits_le16(&ich7_spi->spis, SPIS_LOCK);
141 } else if (plat->ich_version == ICHV_9) {
142 struct ich9_spi_regs *ich9_spi = sbase;
144 setbits_le16(&ich9_spi->hsfs, HSFS_FLOCKDN);
148 static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
152 if (plat->ich_version == ICHV_7) {
153 struct ich7_spi_regs *ich7_spi = sbase;
155 lock = readw(&ich7_spi->spis) & SPIS_LOCK;
156 } else if (plat->ich_version == ICHV_9) {
157 struct ich9_spi_regs *ich9_spi = sbase;
159 lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
165 static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
169 uint8_t opmenu[ctlr->menubytes];
172 /* The lock is off, so just use index 0. */
173 ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
174 optypes = ich_readw(ctlr, ctlr->optype);
175 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
176 ich_writew(ctlr, optypes, ctlr->optype);
179 /* The lock is on. See if what we need is on the menu. */
181 uint16_t opcode_index;
183 /* Write Enable is handled as atomic prefix */
184 if (trans->opcode == SPI_OPCODE_WREN)
187 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
188 for (opcode_index = 0; opcode_index < ctlr->menubytes;
190 if (opmenu[opcode_index] == trans->opcode)
194 if (opcode_index == ctlr->menubytes) {
195 debug("ICH SPI: Opcode %x not found\n", trans->opcode);
199 optypes = ich_readw(ctlr, ctlr->optype);
200 optype = (optypes >> (opcode_index * 2)) & 0x3;
202 if (optype != trans->type) {
203 debug("ICH SPI: Transaction doesn't fit type %d\n",
212 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
213 * below is true) or 0. In case the wait was for the bit(s) to set - write
214 * those bits back, which would cause resetting them.
216 * Return the last read status value on success or -1 on failure.
218 static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
221 int timeout = 600000; /* This will result in 6s */
225 status = ich_readw(ctlr, ctlr->status);
226 if (wait_til_set ^ ((status & bitmask) == 0)) {
228 ich_writew(ctlr, status & bitmask,
235 debug("ICH SPI: SCIP timeout, read %x, expected %x, wts %x %x\n",
236 status, bitmask, wait_til_set, status & bitmask);
241 static void ich_spi_config_opcode(struct udevice *dev)
243 struct ich_spi_priv *ctlr = dev_get_priv(dev);
246 * PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down
247 * to prevent accidental or intentional writes. Before they get
248 * locked down, these registers should be initialized properly.
250 ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
251 ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
252 ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
253 ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
256 static int ich_spi_exec_op_swseq(struct spi_slave *slave,
257 const struct spi_mem_op *op)
259 struct udevice *bus = dev_get_parent(slave->dev);
260 struct ich_spi_platdata *plat = dev_get_platdata(bus);
261 struct ich_spi_priv *ctlr = dev_get_priv(bus);
263 int16_t opcode_index;
266 struct spi_trans *trans = &ctlr->trans;
267 bool lock = spi_lock_status(plat, ctlr->base);
274 if (op->data.nbytes) {
275 if (op->data.dir == SPI_MEM_DATA_IN) {
276 trans->in = op->data.buf.in;
277 trans->bytesin = op->data.nbytes;
279 trans->out = op->data.buf.out;
280 trans->bytesout = op->data.nbytes;
284 if (trans->opcode != op->cmd.opcode)
285 trans->opcode = op->cmd.opcode;
287 if (lock && trans->opcode == SPI_OPCODE_WRDIS)
290 if (trans->opcode == SPI_OPCODE_WREN) {
292 * Treat Write Enable as Atomic Pre-Op if possible
293 * in order to prevent the Management Engine from
294 * issuing a transaction between WREN and DATA.
297 ich_writew(ctlr, trans->opcode, ctlr->preop);
301 ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
305 if (plat->ich_version == ICHV_7)
306 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
308 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
310 /* Try to guess spi transaction type */
311 if (op->data.dir == SPI_MEM_DATA_OUT) {
313 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
315 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
318 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
320 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
322 /* Special erase case handling */
323 if (op->addr.nbytes && !op->data.buswidth)
324 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
326 opcode_index = spi_setup_opcode(ctlr, trans, lock);
327 if (opcode_index < 0)
330 if (op->addr.nbytes) {
331 trans->offset = op->addr.val;
335 if (ctlr->speed && ctlr->max_speed >= 33000000) {
338 byte = ich_readb(ctlr, ctlr->speed);
339 if (ctlr->cur_speed >= 33000000)
340 byte |= SSFC_SCF_33MHZ;
342 byte &= ~SSFC_SCF_33MHZ;
343 ich_writeb(ctlr, byte, ctlr->speed);
346 /* Preset control fields */
347 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
349 /* Issue atomic preop cycle if needed */
350 if (ich_readw(ctlr, ctlr->preop))
353 if (!trans->bytesout && !trans->bytesin) {
354 /* SPI addresses are 24 bit only */
356 ich_writel(ctlr, trans->offset & 0x00FFFFFF,
360 * This is a 'no data' command (like Write Enable), its
361 * bitesout size was 1, decremented to zero while executing
362 * spi_setup_opcode() above. Tell the chip to send the
365 ich_writew(ctlr, control, ctlr->control);
367 /* wait for the result */
368 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
372 if (status & SPIS_FCERR) {
373 debug("ICH SPI: Command transaction error\n");
380 while (trans->bytesout || trans->bytesin) {
381 uint32_t data_length;
383 /* SPI addresses are 24 bit only */
384 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
387 data_length = min(trans->bytesout, ctlr->databytes);
389 data_length = min(trans->bytesin, ctlr->databytes);
391 /* Program data into FDATA0 to N */
392 if (trans->bytesout) {
393 write_reg(ctlr, trans->out, ctlr->data, data_length);
394 trans->bytesout -= data_length;
397 /* Add proper control fields' values */
398 control &= ~((ctlr->databytes - 1) << 8);
400 control |= (data_length - 1) << 8;
403 ich_writew(ctlr, control, ctlr->control);
405 /* Wait for Cycle Done Status or Flash Cycle Error */
406 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
410 if (status & SPIS_FCERR) {
411 debug("ICH SPI: Data transaction error %x\n", status);
415 if (trans->bytesin) {
416 read_reg(ctlr, ctlr->data, trans->in, data_length);
417 trans->bytesin -= data_length;
421 /* Clear atomic preop now that xfer is done */
423 ich_writew(ctlr, 0, ctlr->preop);
429 * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and
430 * that the operation does not cross page boundary.
432 static uint get_xfer_len(u32 offset, int len, int page_size)
434 uint xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE);
435 uint bytes_left = ALIGN(offset, page_size) - offset;
438 xfer_len = min(xfer_len, bytes_left);
443 /* Fill FDATAn FIFO in preparation for a write transaction */
444 static void fill_xfer_fifo(struct fast_spi_regs *regs, const void *data,
447 memcpy(regs->fdata, data, len);
450 /* Drain FDATAn FIFO after a read transaction populates data */
451 static void drain_xfer_fifo(struct fast_spi_regs *regs, void *dest, uint len)
453 memcpy(dest, regs->fdata, len);
456 /* Fire up a transfer using the hardware sequencer */
457 static void start_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle,
458 uint offset, uint len)
460 /* Make sure all W1C status bits get cleared */
463 hsfsts = readl(®s->hsfsts_ctl);
464 hsfsts &= ~(HSFSTS_FCYCLE_MASK | HSFSTS_FDBC_MASK);
465 hsfsts |= HSFSTS_AEL | HSFSTS_FCERR | HSFSTS_FDONE;
467 /* Set up transaction parameters */
468 hsfsts |= hsfsts_cycle << HSFSTS_FCYCLE_SHIFT;
469 hsfsts |= ((len - 1) << HSFSTS_FDBC_SHIFT) & HSFSTS_FDBC_MASK;
470 hsfsts |= HSFSTS_FGO;
472 writel(offset, ®s->faddr);
473 writel(hsfsts, ®s->hsfsts_ctl);
476 static int wait_for_hwseq_xfer(struct fast_spi_regs *regs, uint offset)
481 start = get_timer(0);
483 hsfsts = readl(®s->hsfsts_ctl);
484 if (hsfsts & HSFSTS_FCERR) {
485 debug("SPI transaction error at offset %x HSFSTS = %08x\n",
489 if (hsfsts & HSFSTS_AEL)
492 if (hsfsts & HSFSTS_FDONE)
494 } while (get_timer(start) < SPIBAR_HWSEQ_XFER_TIMEOUT_MS);
496 debug("SPI transaction timeout at offset %x HSFSTS = %08x, timer %d\n",
497 offset, hsfsts, (uint)get_timer(start));
503 * exec_sync_hwseq_xfer() - Execute flash transfer by hardware sequencing
505 * This waits until complete or timeout
507 * @regs: SPI registers
508 * @hsfsts_cycle: Cycle type (enum hsfsts_cycle_t)
509 * @offset: Offset to access
510 * @len: Number of bytes to transfer (can be 0)
511 * @return 0 if OK, -EIO on flash-cycle error (FCERR), -EPERM on access error
512 * (AEL), -ETIMEDOUT on timeout
514 static int exec_sync_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle,
515 uint offset, uint len)
517 start_hwseq_xfer(regs, hsfsts_cycle, offset, len);
519 return wait_for_hwseq_xfer(regs, offset);
522 static int ich_spi_exec_op_hwseq(struct spi_slave *slave,
523 const struct spi_mem_op *op)
525 struct spi_flash *flash = dev_get_uclass_priv(slave->dev);
526 struct udevice *bus = dev_get_parent(slave->dev);
527 struct ich_spi_priv *priv = dev_get_priv(bus);
528 struct fast_spi_regs *regs = priv->base;
537 offset = op->addr.val;
538 len = op->data.nbytes;
540 switch (op->cmd.opcode) {
542 cycle = HSFSTS_CYCLE_RDID;
544 case SPINOR_OP_READ_FAST:
545 cycle = HSFSTS_CYCLE_READ;
548 cycle = HSFSTS_CYCLE_WRITE;
551 /* Nothing needs to be done */
554 cycle = HSFSTS_CYCLE_WR_STATUS;
557 cycle = HSFSTS_CYCLE_RD_STATUS;
560 return 0; /* ignore */
561 case SPINOR_OP_BE_4K:
562 cycle = HSFSTS_CYCLE_4K_ERASE;
564 uint xfer_len = 0x1000;
566 ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0);
574 debug("Unknown cycle %x\n", op->cmd.opcode);
578 out = op->data.dir == SPI_MEM_DATA_OUT;
579 buf = out ? (u8 *)op->data.buf.out : op->data.buf.in;
580 page_size = flash->page_size ? : 256;
583 uint xfer_len = get_xfer_len(offset, len, page_size);
586 fill_xfer_fifo(regs, buf, xfer_len);
588 ret = exec_sync_hwseq_xfer(regs, cycle, offset, xfer_len);
593 drain_xfer_fifo(regs, buf, xfer_len);
603 static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
605 struct udevice *bus = dev_get_parent(slave->dev);
606 struct ich_spi_platdata *plat = dev_get_platdata(bus);
609 bootstage_start(BOOTSTAGE_ID_ACCUM_SPI, "fast_spi");
611 ret = ich_spi_exec_op_hwseq(slave, op);
613 ret = ich_spi_exec_op_swseq(slave, op);
614 bootstage_accum(BOOTSTAGE_ID_ACCUM_SPI);
619 static int ich_get_mmap_bus(struct udevice *bus, ulong *map_basep,
620 uint *map_sizep, uint *offsetp)
624 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
625 struct pci_child_platdata *pplat = dev_get_parent_platdata(bus);
627 spi_bdf = pplat->devfn;
629 struct ich_spi_platdata *plat = dev_get_platdata(bus);
632 * We cannot rely on plat->bdf being set up yet since this method can
633 * be called before the device is probed. Use the of-platdata directly
636 spi_bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
639 return fast_spi_get_bios_mmap(spi_bdf, map_basep, map_sizep, offsetp);
642 static int ich_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep,
645 struct udevice *bus = dev_get_parent(dev);
647 return ich_get_mmap_bus(bus, map_basep, map_sizep, offsetp);
650 static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op)
652 unsigned int page_offset;
653 int addr = op->addr.val;
654 unsigned int byte_count = op->data.nbytes;
656 if (hweight32(ICH_BOUNDARY) == 1) {
657 page_offset = addr & (ICH_BOUNDARY - 1);
661 page_offset = do_div(aux, ICH_BOUNDARY);
664 if (op->data.dir == SPI_MEM_DATA_IN) {
665 if (slave->max_read_size) {
666 op->data.nbytes = min(ICH_BOUNDARY - page_offset,
667 slave->max_read_size);
669 } else if (slave->max_write_size) {
670 op->data.nbytes = min(ICH_BOUNDARY - page_offset,
671 slave->max_write_size);
674 op->data.nbytes = min(op->data.nbytes, byte_count);
679 static int ich_protect_lockdown(struct udevice *dev)
681 struct ich_spi_platdata *plat = dev_get_platdata(dev);
682 struct ich_spi_priv *priv = dev_get_priv(dev);
685 /* Disable the BIOS write protect so write commands are allowed */
687 ret = pch_set_spi_protect(priv->pch, false);
688 if (ret == -ENOSYS) {
691 bios_cntl = ich_readb(priv, priv->bcr);
692 bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
693 bios_cntl |= 1; /* Write Protect Disable (WPD) */
694 ich_writeb(priv, bios_cntl, priv->bcr);
696 debug("%s: Failed to disable write-protect: err=%d\n",
701 /* Lock down SPI controller settings if required */
702 if (plat->lockdown) {
703 ich_spi_config_opcode(dev);
704 spi_lock_down(plat, priv->base);
710 static int ich_init_controller(struct udevice *dev,
711 struct ich_spi_platdata *plat,
712 struct ich_spi_priv *ctlr)
714 if (spl_phase() == PHASE_TPL) {
715 struct ich_spi_platdata *plat = dev_get_platdata(dev);
718 ret = fast_spi_early_init(plat->bdf, plat->mmio_base);
723 ctlr->base = (void *)plat->mmio_base;
724 if (plat->ich_version == ICHV_7) {
725 struct ich7_spi_regs *ich7_spi = ctlr->base;
727 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
728 ctlr->menubytes = sizeof(ich7_spi->opmenu);
729 ctlr->optype = offsetof(struct ich7_spi_regs, optype);
730 ctlr->addr = offsetof(struct ich7_spi_regs, spia);
731 ctlr->data = offsetof(struct ich7_spi_regs, spid);
732 ctlr->databytes = sizeof(ich7_spi->spid);
733 ctlr->status = offsetof(struct ich7_spi_regs, spis);
734 ctlr->control = offsetof(struct ich7_spi_regs, spic);
735 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
736 ctlr->preop = offsetof(struct ich7_spi_regs, preop);
737 } else if (plat->ich_version == ICHV_9) {
738 struct ich9_spi_regs *ich9_spi = ctlr->base;
740 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
741 ctlr->menubytes = sizeof(ich9_spi->opmenu);
742 ctlr->optype = offsetof(struct ich9_spi_regs, optype);
743 ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
744 ctlr->data = offsetof(struct ich9_spi_regs, fdata);
745 ctlr->databytes = sizeof(ich9_spi->fdata);
746 ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
747 ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
748 ctlr->speed = ctlr->control + 2;
749 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
750 ctlr->preop = offsetof(struct ich9_spi_regs, preop);
751 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
752 ctlr->pr = &ich9_spi->pr[0];
754 debug("ICH SPI: Unrecognised ICH version %d\n",
759 /* Work out the maximum speed we can support */
760 ctlr->max_speed = 20000000;
761 if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
762 ctlr->max_speed = 33000000;
763 debug("ICH SPI: Version ID %d detected at %lx, speed %ld\n",
764 plat->ich_version, plat->mmio_base, ctlr->max_speed);
766 ich_set_bbar(ctlr, 0);
771 static int ich_cache_bios_region(struct udevice *dev)
779 ret = ich_get_mmap_bus(dev, &map_base, &map_size, &offset);
783 /* Don't use WRBACK since we are not supposed to write to SPI flash */
784 base = SZ_4G - map_size;
785 mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size);
786 log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size);
791 static int ich_spi_probe(struct udevice *dev)
793 struct ich_spi_platdata *plat = dev_get_platdata(dev);
794 struct ich_spi_priv *priv = dev_get_priv(dev);
797 ret = ich_init_controller(dev, plat, priv);
801 if (spl_phase() == PHASE_TPL) {
802 /* Cache the BIOS to speed things up */
803 ret = ich_cache_bios_region(dev);
807 ret = ich_protect_lockdown(dev);
811 priv->cur_speed = priv->max_speed;
816 static int ich_spi_remove(struct udevice *bus)
819 * Configure SPI controller so that the Linux MTD driver can fully
820 * access the SPI NOR chip
822 ich_spi_config_opcode(bus);
827 static int ich_spi_set_speed(struct udevice *bus, uint speed)
829 struct ich_spi_priv *priv = dev_get_priv(bus);
831 priv->cur_speed = speed;
836 static int ich_spi_set_mode(struct udevice *bus, uint mode)
838 debug("%s: mode=%d\n", __func__, mode);
843 static int ich_spi_child_pre_probe(struct udevice *dev)
845 struct udevice *bus = dev_get_parent(dev);
846 struct ich_spi_platdata *plat = dev_get_platdata(bus);
847 struct ich_spi_priv *priv = dev_get_priv(bus);
848 struct spi_slave *slave = dev_get_parent_priv(dev);
851 * Yes this controller can only write a small number of bytes at
852 * once! The limit is typically 64 bytes. For hardware sequencing a
853 * a loop is used to get around this.
856 slave->max_write_size = priv->databytes;
858 * ICH 7 SPI controller only supports array read command
859 * and byte program command for SST flash
861 if (plat->ich_version == ICHV_7)
862 slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
867 static int ich_spi_ofdata_to_platdata(struct udevice *dev)
869 struct ich_spi_platdata *plat = dev_get_platdata(dev);
871 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
872 struct ich_spi_priv *priv = dev_get_priv(dev);
874 /* Find a PCH if there is one */
875 uclass_first_device(UCLASS_PCH, &priv->pch);
877 priv->pch = dev_get_parent(dev);
879 plat->ich_version = dev_get_driver_data(dev);
880 plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");
881 pch_get_spi_base(priv->pch, &plat->mmio_base);
883 * Use an int so that the property is present in of-platdata even
886 plat->hwseq = dev_read_u32_default(dev, "intel,hardware-seq", 0);
888 plat->ich_version = ICHV_APL;
889 plat->mmio_base = plat->dtplat.early_regs[0];
890 plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
891 plat->hwseq = plat->dtplat.intel_hardware_seq;
893 debug("%s: mmio_base=%lx\n", __func__, plat->mmio_base);
898 static const struct spi_controller_mem_ops ich_controller_mem_ops = {
899 .adjust_op_size = ich_spi_adjust_size,
901 .exec_op = ich_spi_exec_op,
904 static const struct dm_spi_ops ich_spi_ops = {
905 /* xfer is not supported */
906 .set_speed = ich_spi_set_speed,
907 .set_mode = ich_spi_set_mode,
908 .mem_ops = &ich_controller_mem_ops,
909 .get_mmap = ich_get_mmap,
911 * cs_info is not needed, since we require all chip selects to be
912 * in the device tree explicitly
916 static const struct udevice_id ich_spi_ids[] = {
917 { .compatible = "intel,ich7-spi", ICHV_7 },
918 { .compatible = "intel,ich9-spi", ICHV_9 },
922 U_BOOT_DRIVER(intel_fast_spi) = {
923 .name = "intel_fast_spi",
925 .of_match = ich_spi_ids,
927 .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
928 .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
929 .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
930 .child_pre_probe = ich_spi_child_pre_probe,
931 .probe = ich_spi_probe,
932 .remove = ich_spi_remove,
933 .flags = DM_FLAG_OS_PREPARE,