2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Freescale Quad Serial Peripheral Interface (QSPI) driver
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/sizes.h>
16 #define RX_BUFFER_SIZE 0x80
18 #define TX_BUFFER_SIZE 0x200
20 #define TX_BUFFER_SIZE 0x40
23 #define OFFSET_BITS_MASK 0x00ffffff
25 #define FLASH_STATUS_WEL 0x02
29 #define SEQID_FAST_READ 2
32 #define SEQID_CHIP_ERASE 5
36 #ifdef CONFIG_SPI_FLASH_BAR
39 #define SEQID_RDEAR 11
40 #define SEQID_WREAR 12
44 #define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */
45 #define QSPI_CMD_RDSR 0x05 /* Read status register */
46 #define QSPI_CMD_WREN 0x06 /* Write enable */
47 #define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */
48 #define QSPI_CMD_BE_4K 0x20 /* 4K erase */
49 #define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */
50 #define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */
51 #define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */
53 /* Used for Micron, winbond and Macronix flashes */
54 #define QSPI_CMD_WREAR 0xc5 /* EAR register write */
55 #define QSPI_CMD_RDEAR 0xc8 /* EAR reigster read */
57 /* Used for Spansion flashes only. */
58 #define QSPI_CMD_BRRD 0x16 /* Bank register read */
59 #define QSPI_CMD_BRWR 0x17 /* Bank register write */
61 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
62 #define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
63 #define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */
64 #define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
66 #ifdef CONFIG_SYS_FSL_QSPI_LE
67 #define qspi_read32 in_le32
68 #define qspi_write32 out_le32
69 #elif defined(CONFIG_SYS_FSL_QSPI_BE)
70 #define qspi_read32 in_be32
71 #define qspi_write32 out_be32
74 static unsigned long spi_bases[] = {
81 static unsigned long amba_bases[] = {
89 struct spi_slave slave;
90 unsigned long reg_base;
91 unsigned long amba_base;
96 /* QSPI support swapping the flash read/write data
97 * in hardware for LS102xA, but not for VF610 */
98 static inline u32 qspi_endian_xchg(u32 data)
107 static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
109 return container_of(slave, struct fsl_qspi, slave);
112 static void qspi_set_lut(struct fsl_qspi *qspi)
114 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
118 qspi_write32(®s->lutkey, LUT_KEY_VALUE);
119 qspi_write32(®s->lckcr, QSPI_LCKCR_UNLOCK);
122 lut_base = SEQID_WREN * 4;
123 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
124 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
125 qspi_write32(®s->lut[lut_base + 1], 0);
126 qspi_write32(®s->lut[lut_base + 2], 0);
127 qspi_write32(®s->lut[lut_base + 3], 0);
130 lut_base = SEQID_FAST_READ * 4;
131 #ifdef CONFIG_SPI_FLASH_BAR
132 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) |
133 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
134 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
136 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
137 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) |
138 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
139 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
141 qspi_write32(®s->lut[lut_base],
142 OPRND0(QSPI_CMD_FAST_READ_4B) |
143 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
144 OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
147 qspi_write32(®s->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) |
148 INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
150 qspi_write32(®s->lut[lut_base + 2], 0);
151 qspi_write32(®s->lut[lut_base + 3], 0);
154 lut_base = SEQID_RDSR * 4;
155 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
156 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
157 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
158 qspi_write32(®s->lut[lut_base + 1], 0);
159 qspi_write32(®s->lut[lut_base + 2], 0);
160 qspi_write32(®s->lut[lut_base + 3], 0);
163 lut_base = SEQID_SE * 4;
164 #ifdef CONFIG_SPI_FLASH_BAR
165 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE) |
166 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
167 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
169 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
170 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE) |
171 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
172 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
174 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE_4B) |
175 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
176 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
178 qspi_write32(®s->lut[lut_base + 1], 0);
179 qspi_write32(®s->lut[lut_base + 2], 0);
180 qspi_write32(®s->lut[lut_base + 3], 0);
182 /* Erase the whole chip */
183 lut_base = SEQID_CHIP_ERASE * 4;
184 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_CHIP_ERASE) |
185 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
186 qspi_write32(®s->lut[lut_base + 1], 0);
187 qspi_write32(®s->lut[lut_base + 2], 0);
188 qspi_write32(®s->lut[lut_base + 3], 0);
191 lut_base = SEQID_PP * 4;
192 #ifdef CONFIG_SPI_FLASH_BAR
193 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP) |
194 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
195 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
197 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
198 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP) |
199 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
200 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
202 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP_4B) |
203 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
204 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
208 * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
209 * So, Use IDATSZ in IPCR to determine the size and here set 0.
211 qspi_write32(®s->lut[lut_base + 1], OPRND0(0) |
212 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
214 qspi_write32(®s->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) |
215 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
217 qspi_write32(®s->lut[lut_base + 2], 0);
218 qspi_write32(®s->lut[lut_base + 3], 0);
221 lut_base = SEQID_RDID * 4;
222 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
223 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
224 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
225 qspi_write32(®s->lut[lut_base + 1], 0);
226 qspi_write32(®s->lut[lut_base + 2], 0);
227 qspi_write32(®s->lut[lut_base + 3], 0);
229 /* SUB SECTOR 4K ERASE */
230 lut_base = SEQID_BE_4K * 4;
231 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
232 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
233 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
235 #ifdef CONFIG_SPI_FLASH_BAR
237 * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
238 * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
241 lut_base = SEQID_BRRD * 4;
242 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
243 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
244 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
246 lut_base = SEQID_BRWR * 4;
247 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
248 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
249 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
251 lut_base = SEQID_RDEAR * 4;
252 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
253 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
254 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
256 lut_base = SEQID_WREAR * 4;
257 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
258 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
259 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
262 qspi_write32(®s->lutkey, LUT_KEY_VALUE);
263 qspi_write32(®s->lckcr, QSPI_LCKCR_LOCK);
271 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
272 unsigned int max_hz, unsigned int mode)
274 struct fsl_qspi *qspi;
275 struct fsl_qspi_regs *regs;
276 u32 reg_val, smpr_val;
277 u32 total_size, seq_id;
279 if (bus >= ARRAY_SIZE(spi_bases))
282 if (cs >= FSL_QSPI_FLASH_NUM)
285 qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
289 qspi->reg_base = spi_bases[bus];
291 * According cs, use different amba_base to choose the
292 * corresponding flash devices.
294 * If not, only one flash device is used even if passing
295 * different cs using `sf probe`
297 qspi->amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
299 qspi->slave.max_write_size = TX_BUFFER_SIZE;
301 regs = (struct fsl_qspi_regs *)qspi->reg_base;
302 qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
304 smpr_val = qspi_read32(®s->smpr);
305 qspi_write32(®s->smpr, smpr_val & ~(QSPI_SMPR_FSDLY_MASK |
306 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK));
307 qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK);
309 total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
311 * Any read access to non-implemented addresses will provide
314 * In case single die flash devices, TOP_ADDR_MEMA2 and
315 * TOP_ADDR_MEMB2 should be initialized/programmed to
316 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
317 * setting the size of these devices to 0. This would ensure
318 * that the complete memory map is assigned to only one flash device.
320 qspi_write32(®s->sfa1ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
321 qspi_write32(®s->sfa2ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
322 qspi_write32(®s->sfb1ad, total_size | amba_bases[bus]);
323 qspi_write32(®s->sfb2ad, total_size | amba_bases[bus]);
327 smpr_val = qspi_read32(®s->smpr);
328 smpr_val &= ~QSPI_SMPR_DDRSMP_MASK;
329 qspi_write32(®s->smpr, smpr_val);
330 qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK);
333 reg_val = qspi_read32(®s->bfgencr);
334 reg_val &= ~QSPI_BFGENCR_SEQID_MASK;
335 reg_val |= (seq_id << QSPI_BFGENCR_SEQID_SHIFT);
336 reg_val &= ~QSPI_BFGENCR_PAR_EN_MASK;
337 qspi_write32(®s->bfgencr, reg_val);
342 void spi_free_slave(struct spi_slave *slave)
344 struct fsl_qspi *qspi = to_qspi_spi(slave);
349 int spi_claim_bus(struct spi_slave *slave)
354 #ifdef CONFIG_SPI_FLASH_BAR
355 /* Bank register read/write, EAR register read/write */
356 static void qspi_op_rdbank(struct fsl_qspi *qspi, u8 *rxbuf, u32 len)
358 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
359 u32 reg, mcr_reg, data, seqid;
361 mcr_reg = qspi_read32(®s->mcr);
362 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
363 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
364 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
366 qspi_write32(®s->sfar, qspi->amba_base);
368 if (qspi->cur_seqid == QSPI_CMD_BRRD)
373 qspi_write32(®s->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
375 /* Wait previous command complete */
376 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
380 reg = qspi_read32(®s->rbsr);
381 if (reg & QSPI_RBSR_RDBFL_MASK) {
382 data = qspi_read32(®s->rbdr[0]);
383 data = qspi_endian_xchg(data);
384 memcpy(rxbuf, &data, len);
385 qspi_write32(®s->mcr, qspi_read32(®s->mcr) |
386 QSPI_MCR_CLR_RXF_MASK);
391 qspi_write32(®s->mcr, mcr_reg);
395 static void qspi_op_rdid(struct fsl_qspi *qspi, u32 *rxbuf, u32 len)
397 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
398 u32 mcr_reg, rbsr_reg, data;
401 mcr_reg = qspi_read32(®s->mcr);
402 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
403 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
404 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
406 qspi_write32(®s->sfar, qspi->amba_base);
408 qspi_write32(®s->ipcr, (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
409 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
414 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
415 rbsr_reg = qspi_read32(®s->rbsr);
416 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
417 data = qspi_read32(®s->rbdr[i]);
418 data = qspi_endian_xchg(data);
419 memcpy(rxbuf, &data, 4);
426 qspi_write32(®s->mcr, mcr_reg);
429 static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf, u32 len)
431 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
436 mcr_reg = qspi_read32(®s->mcr);
437 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
438 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
439 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
441 to_or_from = qspi->sf_addr + qspi->amba_base;
444 qspi_write32(®s->sfar, to_or_from);
446 size = (len > RX_BUFFER_SIZE) ?
447 RX_BUFFER_SIZE : len;
449 qspi_write32(®s->ipcr,
450 (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) | size);
451 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
458 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
459 data = qspi_read32(®s->rbdr[i]);
460 data = qspi_endian_xchg(data);
461 memcpy(rxbuf, &data, 4);
466 qspi_write32(®s->mcr, qspi_read32(®s->mcr) |
467 QSPI_MCR_CLR_RXF_MASK);
470 qspi_write32(®s->mcr, mcr_reg);
473 static void qspi_op_write(struct fsl_qspi *qspi, u8 *txbuf, u32 len)
475 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
476 u32 mcr_reg, data, reg, status_reg, seqid;
477 int i, size, tx_size;
480 mcr_reg = qspi_read32(®s->mcr);
481 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
482 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
483 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
486 while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
487 qspi_write32(®s->ipcr,
488 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
489 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
492 qspi_write32(®s->ipcr,
493 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
494 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
497 reg = qspi_read32(®s->rbsr);
498 if (reg & QSPI_RBSR_RDBFL_MASK) {
499 status_reg = qspi_read32(®s->rbdr[0]);
500 status_reg = qspi_endian_xchg(status_reg);
502 qspi_write32(®s->mcr,
503 qspi_read32(®s->mcr) | QSPI_MCR_CLR_RXF_MASK);
506 /* Default is page programming */
508 #ifdef CONFIG_SPI_FLASH_BAR
509 if (qspi->cur_seqid == QSPI_CMD_BRWR)
511 else if (qspi->cur_seqid == QSPI_CMD_WREAR)
515 to_or_from = qspi->sf_addr + qspi->amba_base;
517 qspi_write32(®s->sfar, to_or_from);
519 tx_size = (len > TX_BUFFER_SIZE) ?
520 TX_BUFFER_SIZE : len;
523 for (i = 0; i < size; i++) {
524 memcpy(&data, txbuf, 4);
525 data = qspi_endian_xchg(data);
526 qspi_write32(®s->tbdr, data);
533 memcpy(&data, txbuf, size);
534 data = qspi_endian_xchg(data);
535 qspi_write32(®s->tbdr, data);
538 qspi_write32(®s->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
539 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
542 qspi_write32(®s->mcr, mcr_reg);
545 static void qspi_op_rdsr(struct fsl_qspi *qspi, u32 *rxbuf)
547 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
548 u32 mcr_reg, reg, data;
550 mcr_reg = qspi_read32(®s->mcr);
551 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
552 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
553 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
555 qspi_write32(®s->sfar, qspi->amba_base);
557 qspi_write32(®s->ipcr,
558 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
559 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
563 reg = qspi_read32(®s->rbsr);
564 if (reg & QSPI_RBSR_RDBFL_MASK) {
565 data = qspi_read32(®s->rbdr[0]);
566 data = qspi_endian_xchg(data);
567 memcpy(rxbuf, &data, 4);
568 qspi_write32(®s->mcr, qspi_read32(®s->mcr) |
569 QSPI_MCR_CLR_RXF_MASK);
574 qspi_write32(®s->mcr, mcr_reg);
577 static void qspi_op_erase(struct fsl_qspi *qspi)
579 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
583 mcr_reg = qspi_read32(®s->mcr);
584 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
585 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
586 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
588 to_or_from = qspi->sf_addr + qspi->amba_base;
589 qspi_write32(®s->sfar, to_or_from);
591 qspi_write32(®s->ipcr,
592 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
593 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
596 if (qspi->cur_seqid == QSPI_CMD_SE) {
597 qspi_write32(®s->ipcr,
598 (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
599 } else if (qspi->cur_seqid == QSPI_CMD_BE_4K) {
600 qspi_write32(®s->ipcr,
601 (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
603 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
606 qspi_write32(®s->mcr, mcr_reg);
609 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
610 const void *dout, void *din, unsigned long flags)
612 struct fsl_qspi *qspi = to_qspi_spi(slave);
613 u32 bytes = DIV_ROUND_UP(bitlen, 8);
614 static u32 wr_sfaddr;
618 if (flags & SPI_XFER_BEGIN) {
619 qspi->cur_seqid = *(u8 *)dout;
620 memcpy(&txbuf, dout, 4);
623 if (flags == SPI_XFER_END) {
624 qspi->sf_addr = wr_sfaddr;
625 qspi_op_write(qspi, (u8 *)dout, bytes);
629 if (qspi->cur_seqid == QSPI_CMD_FAST_READ) {
630 qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
631 } else if ((qspi->cur_seqid == QSPI_CMD_SE) ||
632 (qspi->cur_seqid == QSPI_CMD_BE_4K)) {
633 qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
635 } else if (qspi->cur_seqid == QSPI_CMD_PP)
636 wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
637 #ifdef CONFIG_SPI_FLASH_BAR
638 else if ((qspi->cur_seqid == QSPI_CMD_BRWR) ||
639 (qspi->cur_seqid == QSPI_CMD_WREAR)) {
646 if (qspi->cur_seqid == QSPI_CMD_FAST_READ)
647 qspi_op_read(qspi, din, bytes);
648 else if (qspi->cur_seqid == QSPI_CMD_RDID)
649 qspi_op_rdid(qspi, din, bytes);
650 else if (qspi->cur_seqid == QSPI_CMD_RDSR)
651 qspi_op_rdsr(qspi, din);
652 #ifdef CONFIG_SPI_FLASH_BAR
653 else if ((qspi->cur_seqid == QSPI_CMD_BRRD) ||
654 (qspi->cur_seqid == QSPI_CMD_RDEAR)) {
656 qspi_op_rdbank(qspi, din, bytes);
664 void spi_release_bus(struct spi_slave *slave)