1 // SPDX-License-Identifier: GPL-2.0+
4 * Freescale QuadSPI driver.
6 * Copyright (C) 2013 Freescale Semiconductor, Inc.
7 * Copyright (C) 2018 Bootlin
8 * Copyright (C) 2018 exceet electronics GmbH
9 * Copyright (C) 2018 Kontron Electronics GmbH
10 * Copyright 2019-2020 NXP
12 * This driver is a ported version of Linux Freescale QSPI driver taken from
13 * v5.5-rc1 tag having following information.
15 * Transition to SPI MEM interface:
17 * Boris Brezillon <bbrezillon@kernel.org>
18 * Frieder Schrempf <frieder.schrempf@kontron.de>
19 * Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
20 * Suresh Gupta <suresh.gupta@nxp.com>
22 * Based on the original fsl-quadspi.c spi-nor driver.
23 * Transition to spi-mem in spi-fsl-qspi.c
29 #include <linux/bitops.h>
30 #include <linux/delay.h>
31 #include <linux/libfdt.h>
32 #include <linux/sizes.h>
33 #include <linux/iopoll.h>
35 #include <linux/iopoll.h>
36 #include <linux/sizes.h>
37 #include <linux/err.h>
41 DECLARE_GLOBAL_DATA_PTR;
44 * The driver only uses one single LUT entry, that is updated on
45 * each call of exec_op(). Index 0 is preset at boot with a basic
46 * read operation, so let's use the last entry (15).
50 /* Registers used by the driver */
51 #define QUADSPI_MCR 0x00
52 #define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)
53 #define QUADSPI_MCR_MDIS_MASK BIT(14)
54 #define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
55 #define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
56 #define QUADSPI_MCR_DDR_EN_MASK BIT(7)
57 #define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
58 #define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
59 #define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
61 #define QUADSPI_IPCR 0x08
62 #define QUADSPI_IPCR_SEQID(x) ((x) << 24)
63 #define QUADSPI_FLSHCR 0x0c
64 #define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)
65 #define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)
66 #define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16)
68 #define QUADSPI_BUF3CR 0x1c
69 #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
70 #define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
71 #define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)
73 #define QUADSPI_BFGENCR 0x20
74 #define QUADSPI_BFGENCR_SEQID(x) ((x) << 12)
76 #define QUADSPI_BUF0IND 0x30
77 #define QUADSPI_BUF1IND 0x34
78 #define QUADSPI_BUF2IND 0x38
79 #define QUADSPI_SFAR 0x100
81 #define QUADSPI_SMPR 0x108
82 #define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)
83 #define QUADSPI_SMPR_FSDLY_MASK BIT(6)
84 #define QUADSPI_SMPR_FSPHS_MASK BIT(5)
85 #define QUADSPI_SMPR_HSENA_MASK BIT(0)
87 #define QUADSPI_RBCT 0x110
88 #define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)
89 #define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
91 #define QUADSPI_TBDR 0x154
93 #define QUADSPI_SR 0x15c
94 #define QUADSPI_SR_IP_ACC_MASK BIT(1)
95 #define QUADSPI_SR_AHB_ACC_MASK BIT(2)
97 #define QUADSPI_FR 0x160
98 #define QUADSPI_FR_TFF_MASK BIT(0)
100 #define QUADSPI_RSER 0x164
101 #define QUADSPI_RSER_TFIE BIT(0)
103 #define QUADSPI_SPTRCLR 0x16c
104 #define QUADSPI_SPTRCLR_IPPTRC BIT(8)
105 #define QUADSPI_SPTRCLR_BFPTRC BIT(0)
107 #define QUADSPI_SFA1AD 0x180
108 #define QUADSPI_SFA2AD 0x184
109 #define QUADSPI_SFB1AD 0x188
110 #define QUADSPI_SFB2AD 0x18c
111 #define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
113 #define QUADSPI_LUTKEY 0x300
114 #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
116 #define QUADSPI_LCKCR 0x304
117 #define QUADSPI_LCKER_LOCK BIT(0)
118 #define QUADSPI_LCKER_UNLOCK BIT(1)
120 #define QUADSPI_LUT_BASE 0x310
121 #define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
122 #define QUADSPI_LUT_REG(idx) \
123 (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
125 /* Instruction set for the LUT register */
133 #define LUT_FSL_READ 7
134 #define LUT_FSL_WRITE 8
135 #define LUT_JMP_ON_CS 9
136 #define LUT_ADDR_DDR 10
137 #define LUT_MODE_DDR 11
138 #define LUT_MODE2_DDR 12
139 #define LUT_MODE4_DDR 13
140 #define LUT_FSL_READ_DDR 14
141 #define LUT_FSL_WRITE_DDR 15
142 #define LUT_DATA_LEARN 16
145 * The PAD definitions for LUT register.
147 * The pad stands for the number of IO lines [0:3].
148 * For example, the quad read needs four IO lines,
149 * so you should use LUT_PAD(4).
151 #define LUT_PAD(x) (fls(x) - 1)
154 * Macro for constructing the LUT entries with the following
157 * ---------------------------------------------------
158 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
159 * ---------------------------------------------------
161 #define LUT_DEF(idx, ins, pad, opr) \
162 ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
164 /* Controller needs driver to swap endianness */
165 #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
167 /* Controller needs 4x internal clock */
168 #define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
171 * TKT253890, the controller needs the driver to fill the txfifo with
172 * 16 bytes at least to trigger a data transfer, even though the extra
173 * data won't be transferred.
175 #define QUADSPI_QUIRK_TKT253890 BIT(2)
177 /* TKT245618, the controller cannot wake up from wait mode */
178 #define QUADSPI_QUIRK_TKT245618 BIT(3)
181 * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
182 * internally. No need to add it when setting SFXXAD and SFAR registers
184 #define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
187 * Controller uses TDH bits in register QUADSPI_FLSHCR.
188 * They need to be set in accordance with the DDR/SDR mode.
190 #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
192 struct fsl_qspi_devtype_data {
195 unsigned int ahb_buf_size;
200 static const struct fsl_qspi_devtype_data vybrid_data = {
203 .ahb_buf_size = SZ_1K,
204 .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
205 .little_endian = true,
208 static const struct fsl_qspi_devtype_data imx6sx_data = {
211 .ahb_buf_size = SZ_1K,
212 .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
213 .little_endian = true,
216 static const struct fsl_qspi_devtype_data imx7d_data = {
219 .ahb_buf_size = SZ_1K,
220 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
221 QUADSPI_QUIRK_USE_TDH_SETTING,
222 .little_endian = true,
225 static const struct fsl_qspi_devtype_data imx6ul_data = {
228 .ahb_buf_size = SZ_1K,
229 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
230 QUADSPI_QUIRK_USE_TDH_SETTING,
231 .little_endian = true,
234 static const struct fsl_qspi_devtype_data ls1021a_data = {
237 .ahb_buf_size = SZ_1K,
239 .little_endian = false,
242 static const struct fsl_qspi_devtype_data ls1088a_data = {
245 .ahb_buf_size = SZ_1K,
246 .quirks = QUADSPI_QUIRK_TKT253890,
247 .little_endian = true,
250 static const struct fsl_qspi_devtype_data ls2080a_data = {
253 .ahb_buf_size = SZ_1K,
254 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
255 .little_endian = true,
260 void __iomem *iobase;
261 void __iomem *ahb_addr;
263 const struct fsl_qspi_devtype_data *devtype_data;
267 static inline int needs_swap_endian(struct fsl_qspi *q)
269 return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
272 static inline int needs_4x_clock(struct fsl_qspi *q)
274 return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
277 static inline int needs_fill_txfifo(struct fsl_qspi *q)
279 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
282 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
284 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
287 static inline int needs_amba_base_offset(struct fsl_qspi *q)
289 return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
292 static inline int needs_tdh_setting(struct fsl_qspi *q)
294 return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
298 * An IC bug makes it necessary to rearrange the 32-bit data.
299 * Later chips, such as IMX6SLX, have fixed this bug.
301 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
303 return needs_swap_endian(q) ? __swab32(a) : a;
307 * R/W functions for big- or little-endian registers:
308 * The QSPI controller's endianness is independent of
309 * the CPU core's endianness. So far, although the CPU
310 * core is little-endian the QSPI controller can use
311 * big-endian or little-endian.
313 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
315 if (q->devtype_data->little_endian)
321 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
323 if (q->devtype_data->little_endian)
324 return in_le32(addr);
326 return in_be32(addr);
329 static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
341 static bool fsl_qspi_supports_op(struct spi_slave *slave,
342 const struct spi_mem_op *op)
344 struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
347 ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
350 ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
352 if (op->dummy.nbytes)
353 ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
356 ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
362 * The number of instructions needed for the op, needs
363 * to fit into a single LUT entry.
365 if (op->addr.nbytes +
366 (op->dummy.nbytes ? 1 : 0) +
367 (op->data.nbytes ? 1 : 0) > 6)
370 /* Max 64 dummy clock cycles supported */
371 if (op->dummy.nbytes &&
372 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
375 /* Max data length, check controller limits and alignment */
376 if (op->data.dir == SPI_MEM_DATA_IN &&
377 (op->data.nbytes > q->devtype_data->ahb_buf_size ||
378 (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
379 !IS_ALIGNED(op->data.nbytes, 8))))
382 if (op->data.dir == SPI_MEM_DATA_OUT &&
383 op->data.nbytes > q->devtype_data->txfifo)
389 static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
390 const struct spi_mem_op *op)
392 void __iomem *base = q->iobase;
396 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
400 * For some unknown reason, using LUT_ADDR doesn't work in some
401 * cases (at least with only one byte long addresses), so
402 * let's use LUT_MODE to write the address bytes one by one
404 for (i = 0; i < op->addr.nbytes; i++) {
405 u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
407 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
408 LUT_PAD(op->addr.buswidth),
413 if (op->dummy.nbytes) {
414 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
415 LUT_PAD(op->dummy.buswidth),
416 op->dummy.nbytes * 8 /
421 if (op->data.nbytes) {
422 lutval[lutidx / 2] |= LUT_DEF(lutidx,
423 op->data.dir == SPI_MEM_DATA_IN ?
424 LUT_FSL_READ : LUT_FSL_WRITE,
425 LUT_PAD(op->data.buswidth),
430 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
433 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
434 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
436 dev_dbg(q->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
437 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
440 for (i = 0; i < ARRAY_SIZE(lutval); i++)
441 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
444 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
445 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
449 * If we have changed the content of the flash by writing or erasing, or if we
450 * read from flash with a different offset into the page buffer, we need to
451 * invalidate the AHB buffer. If we do not do so, we may read out the wrong
452 * data. The spec tells us reset the AHB domain and Serial Flash domain at
455 static void fsl_qspi_invalidate(struct fsl_qspi *q)
459 reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
460 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
461 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
464 * The minimum delay : 1 AHB + 2 SFCK clocks.
465 * Delay 1 us is enough.
469 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
470 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
473 static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
475 struct dm_spi_slave_platdata *plat =
476 dev_get_parent_platdata(slave->dev);
478 if (q->selected == plat->cs)
481 q->selected = plat->cs;
482 fsl_qspi_invalidate(q);
485 static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
487 memcpy_fromio(op->data.buf.in,
488 q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
492 static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
493 const struct spi_mem_op *op)
495 void __iomem *base = q->iobase;
499 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
500 memcpy(&val, op->data.buf.out + i, 4);
501 val = fsl_qspi_endian_xchg(q, val);
502 qspi_writel(q, val, base + QUADSPI_TBDR);
505 if (i < op->data.nbytes) {
506 memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
507 val = fsl_qspi_endian_xchg(q, val);
508 qspi_writel(q, val, base + QUADSPI_TBDR);
511 if (needs_fill_txfifo(q)) {
512 for (i = op->data.nbytes; i < 16; i += 4)
513 qspi_writel(q, 0, base + QUADSPI_TBDR);
517 static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
518 const struct spi_mem_op *op)
520 void __iomem *base = q->iobase;
522 u8 *buf = op->data.buf.in;
525 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
526 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
527 val = fsl_qspi_endian_xchg(q, val);
528 memcpy(buf + i, &val, 4);
531 if (i < op->data.nbytes) {
532 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
533 val = fsl_qspi_endian_xchg(q, val);
534 memcpy(buf + i, &val, op->data.nbytes - i);
538 static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
539 u32 mask, u32 delay_us, u32 timeout_us)
543 if (!q->devtype_data->little_endian)
544 mask = (u32)cpu_to_be32(mask);
546 return readl_poll_timeout(base, reg, !(reg & mask), timeout_us);
549 static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
551 void __iomem *base = q->iobase;
555 * Always start the sequence at the same index since we update
556 * the LUT at each exec_op() call. And also specify the DATA
557 * length, since it's has not been specified in the LUT.
559 qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
560 base + QUADSPI_IPCR);
562 /* wait for the controller being ready */
563 err = fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR,
564 (QUADSPI_SR_IP_ACC_MASK |
565 QUADSPI_SR_AHB_ACC_MASK),
568 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
569 fsl_qspi_read_rxfifo(q, op);
574 static int fsl_qspi_exec_op(struct spi_slave *slave,
575 const struct spi_mem_op *op)
577 struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
578 void __iomem *base = q->iobase;
582 /* wait for the controller being ready */
583 fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
584 QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
586 fsl_qspi_select_mem(q, slave);
588 if (needs_amba_base_offset(q))
589 addr_offset = q->memmap_phy;
592 q->selected * q->devtype_data->ahb_buf_size + addr_offset,
593 base + QUADSPI_SFAR);
595 qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
596 QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
599 qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
600 base + QUADSPI_SPTRCLR);
602 fsl_qspi_prepare_lut(q, op);
605 * If we have large chunks of data, we read them through the AHB bus
606 * by accessing the mapped memory. In all other cases we use
607 * IP commands to access the flash.
609 if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
610 op->data.dir == SPI_MEM_DATA_IN) {
611 fsl_qspi_read_ahb(q, op);
613 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
614 QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
616 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
617 fsl_qspi_fill_txfifo(q, op);
619 err = fsl_qspi_do_op(q, op);
622 /* Invalidate the data in the AHB buffer. */
623 fsl_qspi_invalidate(q);
628 static int fsl_qspi_adjust_op_size(struct spi_slave *slave,
629 struct spi_mem_op *op)
631 struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
633 if (op->data.dir == SPI_MEM_DATA_OUT) {
634 if (op->data.nbytes > q->devtype_data->txfifo)
635 op->data.nbytes = q->devtype_data->txfifo;
637 if (op->data.nbytes > q->devtype_data->ahb_buf_size)
638 op->data.nbytes = q->devtype_data->ahb_buf_size;
639 else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
640 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
646 static int fsl_qspi_default_setup(struct fsl_qspi *q)
648 void __iomem *base = q->iobase;
649 u32 reg, addr_offset = 0;
651 /* Reset the module */
652 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
656 /* Disable the module */
657 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
661 * Previous boot stages (BootROM, bootloader) might have used DDR
662 * mode and did not clear the TDH bits. As we currently use SDR mode
663 * only, clear the TDH bits if necessary.
665 if (needs_tdh_setting(q))
666 qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
667 ~QUADSPI_FLSHCR_TDH_MASK,
668 base + QUADSPI_FLSHCR);
670 reg = qspi_readl(q, base + QUADSPI_SMPR);
671 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
672 | QUADSPI_SMPR_FSPHS_MASK
673 | QUADSPI_SMPR_HSENA_MASK
674 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
676 /* We only use the buffer3 for AHB read */
677 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
678 qspi_writel(q, 0, base + QUADSPI_BUF1IND);
679 qspi_writel(q, 0, base + QUADSPI_BUF2IND);
681 qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
682 q->iobase + QUADSPI_BFGENCR);
683 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
684 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
685 QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
686 base + QUADSPI_BUF3CR);
688 if (needs_amba_base_offset(q))
689 addr_offset = q->memmap_phy;
692 * In HW there can be a maximum of four chips on two buses with
693 * two chip selects on each bus. We use four chip selects in SW
694 * to differentiate between the four chips.
695 * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
696 * SFB2AD accordingly.
698 qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
699 base + QUADSPI_SFA1AD);
700 qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
701 base + QUADSPI_SFA2AD);
702 qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
703 base + QUADSPI_SFB1AD);
704 qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
705 base + QUADSPI_SFB2AD);
709 /* Enable the module */
710 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
715 static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
716 .adjust_op_size = fsl_qspi_adjust_op_size,
717 .supports_op = fsl_qspi_supports_op,
718 .exec_op = fsl_qspi_exec_op,
721 static int fsl_qspi_probe(struct udevice *bus)
723 struct dm_spi_bus *dm_bus = bus->uclass_priv;
724 struct fsl_qspi *q = dev_get_priv(bus);
725 const void *blob = gd->fdt_blob;
726 int node = dev_of_offset(bus);
727 struct fdt_resource res;
731 q->devtype_data = (struct fsl_qspi_devtype_data *)
732 dev_get_driver_data(bus);
734 /* find the resources */
735 ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI",
738 dev_err(bus, "Can't get regs base addresses(ret = %d)!\n", ret);
742 q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
744 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
745 "QuadSPI-memory", &res);
747 dev_err(bus, "Can't get AMBA base addresses(ret = %d)!\n", ret);
751 q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
752 q->memmap_phy = res.start;
754 dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
757 fsl_qspi_default_setup(q);
762 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
763 const void *dout, void *din, unsigned long flags)
768 static int fsl_qspi_claim_bus(struct udevice *dev)
773 static int fsl_qspi_release_bus(struct udevice *dev)
778 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
783 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
788 static const struct dm_spi_ops fsl_qspi_ops = {
789 .claim_bus = fsl_qspi_claim_bus,
790 .release_bus = fsl_qspi_release_bus,
791 .xfer = fsl_qspi_xfer,
792 .set_speed = fsl_qspi_set_speed,
793 .set_mode = fsl_qspi_set_mode,
794 .mem_ops = &fsl_qspi_mem_ops,
797 static const struct udevice_id fsl_qspi_ids[] = {
798 { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data, },
799 { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, },
800 { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, },
801 { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, },
802 { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
803 { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, },
804 { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },
808 U_BOOT_DRIVER(fsl_qspi) = {
811 .of_match = fsl_qspi_ids,
812 .ops = &fsl_qspi_ops,
813 .priv_auto_alloc_size = sizeof(struct fsl_qspi),
814 .probe = fsl_qspi_probe,