1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * Chao Fu (B44548@freescale.com)
9 * Haikun Wang (B53464@freescale.com)
22 #include <asm/arch/clock.h>
25 #include <linux/bitops.h>
26 #include <linux/delay.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 /* fsl_dspi_platdata flags */
31 #define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
34 #define DSPI_IDLE_VAL 0x0
36 /* max chipselect signals number */
37 #define FSL_DSPI_MAX_CHIPSELECT 6
39 /* default SCK frequency, unit: HZ */
40 #define FSL_DSPI_DEFAULT_SCK_FREQ 10000000
42 /* tx/rx data wait timeout value, unit: us */
43 #define DSPI_TXRX_WAIT_TIMEOUT 1000000
45 /* CTAR register pre-configure value */
46 #define DSPI_CTAR_DEFAULT_VALUE (DSPI_CTAR_TRSZ(7) | \
47 DSPI_CTAR_PCSSCK_1CLK | \
50 DSPI_CTAR_CSSCK(0) | \
54 /* CTAR register pre-configure mask */
55 #define DSPI_CTAR_SET_MODE_MASK (DSPI_CTAR_TRSZ(15) | \
56 DSPI_CTAR_PCSSCK(3) | \
59 DSPI_CTAR_CSSCK(15) | \
64 * struct fsl_dspi_platdata - platform data for Freescale DSPI
66 * @flags: Flags for DSPI DSPI_FLAG_...
67 * @speed_hz: Default SCK frequency
68 * @num_chipselect: Number of DSPI chipselect signals
69 * @regs_addr: Base address of DSPI registers
71 struct fsl_dspi_platdata {
79 * struct fsl_dspi_priv - private data for Freescale DSPI
81 * @flags: Flags for DSPI DSPI_FLAG_...
82 * @mode: SPI mode to use for slave device (see SPI mode flags)
83 * @mcr_val: MCR register configure value
84 * @bus_clk: DSPI input clk frequency
85 * @speed_hz: Default SCK frequency
86 * @charbit: How many bits in every transfer
87 * @num_chipselect: Number of DSPI chipselect signals
88 * @ctar_val: CTAR register configure value of per chipselect slave device
89 * @regs: Point to DSPI register structure for I/O access
91 struct fsl_dspi_priv {
99 uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
103 #ifndef CONFIG_DM_SPI
105 struct spi_slave slave;
106 struct fsl_dspi_priv priv;
110 __weak void cpu_dspi_port_conf(void)
114 __weak int cpu_dspi_claim_bus(uint bus, uint cs)
119 __weak void cpu_dspi_release_bus(uint bus, uint cs)
123 static uint dspi_read32(uint flags, uint *addr)
125 return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
126 in_be32(addr) : in_le32(addr);
129 static void dspi_write32(uint flags, uint *addr, uint val)
131 flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
132 out_be32(addr, val) : out_le32(addr, val);
135 static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt)
139 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
142 mcr_val |= DSPI_MCR_HALT;
144 mcr_val &= ~DSPI_MCR_HALT;
146 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
149 static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val)
151 /* halt DSPI module */
154 dspi_write32(priv->flags, &priv->regs->mcr, cfg_val);
159 priv->mcr_val = cfg_val;
162 static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv,
169 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
170 if (state & SPI_CS_HIGH)
171 /* CSx inactive state is low */
172 mcr_val &= ~DSPI_MCR_PCSIS(cs);
174 /* CSx inactive state is high */
175 mcr_val |= DSPI_MCR_PCSIS(cs);
176 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
181 static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv,
186 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
188 bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
189 bus_setup |= priv->ctar_val[cs];
190 bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);
193 bus_setup |= DSPI_CTAR_CPOL;
195 bus_setup |= DSPI_CTAR_CPHA;
196 if (mode & SPI_LSB_FIRST)
197 bus_setup |= DSPI_CTAR_LSBFE;
199 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
202 ((dspi_read32(priv->flags, &priv->regs->ctar[0]) &
203 DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8;
208 static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv)
213 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
214 /* flush RX and TX FIFO */
215 mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
216 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
220 static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data)
222 int timeout = DSPI_TXRX_WAIT_TIMEOUT;
224 /* wait for empty entries in TXFIFO or timeout */
225 while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 &&
230 dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data));
232 debug("dspi_tx: waiting timeout!\n");
235 static u16 dspi_rx(struct fsl_dspi_priv *priv)
237 int timeout = DSPI_TXRX_WAIT_TIMEOUT;
239 /* wait for valid entries in RXFIFO or timeout */
240 while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 &&
245 return (u16)DSPI_RFR_RXDATA(
246 dspi_read32(priv->flags, &priv->regs->rfr));
248 debug("dspi_rx: waiting timeout!\n");
253 static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
254 const void *dout, void *din, unsigned long flags)
256 u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
257 u8 *spi_rd = NULL, *spi_wr = NULL;
259 uint len = bitlen >> 3;
261 if (priv->charbit == 16) {
263 spi_wr16 = (u16 *)dout;
264 spi_rd16 = (u16 *)din;
270 if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
271 ctrl |= DSPI_TFR_CONT;
273 ctrl = ctrl & DSPI_TFR_CONT;
274 ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs);
277 int tmp_len = len - 1;
279 if ((dout != NULL) && (din != NULL)) {
280 if (priv->charbit == 16) {
281 dspi_tx(priv, ctrl, *spi_wr16++);
282 *spi_rd16++ = dspi_rx(priv);
285 dspi_tx(priv, ctrl, *spi_wr++);
286 *spi_rd++ = dspi_rx(priv);
290 else if (dout != NULL) {
291 if (priv->charbit == 16)
292 dspi_tx(priv, ctrl, *spi_wr16++);
294 dspi_tx(priv, ctrl, *spi_wr++);
298 else if (din != NULL) {
299 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
300 if (priv->charbit == 16)
301 *spi_rd16++ = dspi_rx(priv);
303 *spi_rd++ = dspi_rx(priv);
307 len = 1; /* remaining byte */
310 if ((flags & SPI_XFER_END) == SPI_XFER_END)
311 ctrl &= ~DSPI_TFR_CONT;
314 if ((dout != NULL) && (din != NULL)) {
315 if (priv->charbit == 16) {
316 dspi_tx(priv, ctrl, *spi_wr16++);
317 *spi_rd16++ = dspi_rx(priv);
320 dspi_tx(priv, ctrl, *spi_wr++);
321 *spi_rd++ = dspi_rx(priv);
325 else if (dout != NULL) {
326 if (priv->charbit == 16)
327 dspi_tx(priv, ctrl, *spi_wr16);
329 dspi_tx(priv, ctrl, *spi_wr);
333 else if (din != NULL) {
334 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
335 if (priv->charbit == 16)
336 *spi_rd16 = dspi_rx(priv);
338 *spi_rd = dspi_rx(priv);
342 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
350 * Calculate the divide value between input clk frequency and expected SCK frequency
351 * Formula: SCK = (clkrate/pbr) x ((1+dbr)/br)
352 * Dbr: use default value 0
354 * @pbr: return Baud Rate Prescaler value
355 * @br: return Baud Rate Scaler value
356 * @speed_hz: expected SCK frequency
357 * @clkrate: input clk frequency
359 static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
360 int speed_hz, uint clkrate)
362 /* Valid baud rate pre-scaler values */
363 int pbr_tbl[4] = {2, 3, 5, 7};
364 int brs[16] = {2, 4, 6, 8,
366 256, 512, 1024, 2048,
367 4096, 8192, 16384, 32768};
368 int temp, i = 0, j = 0;
370 temp = clkrate / speed_hz;
372 for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
373 for (j = 0; j < ARRAY_SIZE(brs); j++) {
374 if (pbr_tbl[i] * brs[j] >= temp) {
381 debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz);
382 debug("clkrate is %d, we use the max prescaler value.\n", clkrate);
384 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
385 *br = ARRAY_SIZE(brs) - 1;
389 static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
393 int best_i, best_j, bus_clk;
395 bus_clk = priv->bus_clk;
397 debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n",
400 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
401 bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf));
403 ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
405 speed = priv->speed_hz;
406 debug("DSPI set_speed use default SCK rate %u.\n", speed);
407 fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
410 bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
411 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
413 priv->speed_hz = speed;
417 #ifndef CONFIG_DM_SPI
418 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
420 if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
426 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
427 unsigned int max_hz, unsigned int mode)
429 struct fsl_dspi *dspi;
432 dspi = spi_alloc_slave(struct fsl_dspi, bus, cs);
436 cpu_dspi_port_conf();
438 #ifdef CONFIG_SYS_FSL_DSPI_BE
439 dspi->priv.flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
442 dspi->priv.regs = (struct dspi *)MMAP_DSPI;
445 dspi->priv.bus_clk = gd->bus_clk;
447 dspi->priv.bus_clk = mxc_get_clock(MXC_DSPI_CLK);
449 dspi->priv.speed_hz = FSL_DSPI_DEFAULT_SCK_FREQ;
451 /* default: all CS signals inactive state is high */
452 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
453 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
454 fsl_dspi_init_mcr(&dspi->priv, mcr_cfg_val);
456 for (i = 0; i < FSL_DSPI_MAX_CHIPSELECT; i++)
457 dspi->priv.ctar_val[i] = DSPI_CTAR_DEFAULT_VALUE;
459 #ifdef CONFIG_SYS_DSPI_CTAR0
460 if (FSL_DSPI_MAX_CHIPSELECT > 0)
461 dspi->priv.ctar_val[0] = CONFIG_SYS_DSPI_CTAR0;
463 #ifdef CONFIG_SYS_DSPI_CTAR1
464 if (FSL_DSPI_MAX_CHIPSELECT > 1)
465 dspi->priv.ctar_val[1] = CONFIG_SYS_DSPI_CTAR1;
467 #ifdef CONFIG_SYS_DSPI_CTAR2
468 if (FSL_DSPI_MAX_CHIPSELECT > 2)
469 dspi->priv.ctar_val[2] = CONFIG_SYS_DSPI_CTAR2;
471 #ifdef CONFIG_SYS_DSPI_CTAR3
472 if (FSL_DSPI_MAX_CHIPSELECT > 3)
473 dspi->priv.ctar_val[3] = CONFIG_SYS_DSPI_CTAR3;
475 #ifdef CONFIG_SYS_DSPI_CTAR4
476 if (FSL_DSPI_MAX_CHIPSELECT > 4)
477 dspi->priv.ctar_val[4] = CONFIG_SYS_DSPI_CTAR4;
479 #ifdef CONFIG_SYS_DSPI_CTAR5
480 if (FSL_DSPI_MAX_CHIPSELECT > 5)
481 dspi->priv.ctar_val[5] = CONFIG_SYS_DSPI_CTAR5;
483 #ifdef CONFIG_SYS_DSPI_CTAR6
484 if (FSL_DSPI_MAX_CHIPSELECT > 6)
485 dspi->priv.ctar_val[6] = CONFIG_SYS_DSPI_CTAR6;
487 #ifdef CONFIG_SYS_DSPI_CTAR7
488 if (FSL_DSPI_MAX_CHIPSELECT > 7)
489 dspi->priv.ctar_val[7] = CONFIG_SYS_DSPI_CTAR7;
492 fsl_dspi_cfg_speed(&dspi->priv, max_hz);
494 /* configure transfer mode */
495 fsl_dspi_cfg_ctar_mode(&dspi->priv, cs, mode);
497 /* configure active state of CSX */
498 fsl_dspi_cfg_cs_active_state(&dspi->priv, cs, mode);
503 void spi_free_slave(struct spi_slave *slave)
508 int spi_claim_bus(struct spi_slave *slave)
511 struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
513 cpu_dspi_claim_bus(slave->bus, slave->cs);
515 fsl_dspi_clr_fifo(&dspi->priv);
517 /* check module TX and RX status */
518 sr_val = dspi_read32(dspi->priv.flags, &dspi->priv.regs->sr);
519 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
520 debug("DSPI RX/TX not ready!\n");
527 void spi_release_bus(struct spi_slave *slave)
529 struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
531 dspi_halt(&dspi->priv, 1);
532 cpu_dspi_release_bus(slave->bus.slave->cs);
535 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
536 void *din, unsigned long flags)
538 struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
539 return dspi_xfer(&dspi->priv, slave->cs, bitlen, dout, din, flags);
542 static int fsl_dspi_child_pre_probe(struct udevice *dev)
544 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
545 struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
547 if (slave_plat->cs >= priv->num_chipselect) {
548 debug("DSPI invalid chipselect number %d(max %d)!\n",
549 slave_plat->cs, priv->num_chipselect - 1);
553 priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE;
555 debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
556 slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
561 static int fsl_dspi_probe(struct udevice *bus)
563 struct fsl_dspi_platdata *plat = dev_get_platdata(bus);
564 struct fsl_dspi_priv *priv = dev_get_priv(bus);
565 struct dm_spi_bus *dm_spi_bus;
568 dm_spi_bus = bus->uclass_priv;
570 /* cpu speical pin muxing configure */
571 cpu_dspi_port_conf();
573 /* get input clk frequency */
574 priv->regs = (struct dspi *)plat->regs_addr;
575 priv->flags = plat->flags;
577 priv->bus_clk = gd->bus_clk;
579 priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK);
581 priv->num_chipselect = plat->num_chipselect;
582 priv->speed_hz = plat->speed_hz;
583 /* frame data length in bits, default 8bits */
586 dm_spi_bus->max_hz = plat->speed_hz;
588 /* default: all CS signals inactive state is high */
589 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
590 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
591 fsl_dspi_init_mcr(priv, mcr_cfg_val);
593 debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);
598 static int fsl_dspi_claim_bus(struct udevice *dev)
601 struct fsl_dspi_priv *priv;
602 struct udevice *bus = dev->parent;
603 struct dm_spi_slave_platdata *slave_plat =
604 dev_get_parent_platdata(dev);
606 priv = dev_get_priv(bus);
608 /* processor special preparation work */
609 cpu_dspi_claim_bus(bus->seq, slave_plat->cs);
611 /* configure transfer mode */
612 fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode);
614 /* configure active state of CSX */
615 fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs,
618 fsl_dspi_clr_fifo(priv);
620 /* check module TX and RX status */
621 sr_val = dspi_read32(priv->flags, &priv->regs->sr);
622 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
623 debug("DSPI RX/TX not ready!\n");
630 static int fsl_dspi_release_bus(struct udevice *dev)
632 struct udevice *bus = dev->parent;
633 struct fsl_dspi_priv *priv = dev_get_priv(bus);
634 struct dm_spi_slave_platdata *slave_plat =
635 dev_get_parent_platdata(dev);
640 /* processor special release work */
641 cpu_dspi_release_bus(bus->seq, slave_plat->cs);
647 * This function doesn't do anything except help with debugging
649 static int fsl_dspi_bind(struct udevice *bus)
651 debug("%s assigned req_seq %d.\n", bus->name, bus->req_seq);
655 static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
658 struct fsl_dspi_platdata *plat = bus->platdata;
659 const void *blob = gd->fdt_blob;
660 int node = dev_of_offset(bus);
662 if (fdtdec_get_bool(blob, node, "big-endian"))
663 plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
665 plat->num_chipselect =
666 fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
668 addr = devfdt_get_addr(bus);
669 if (addr == FDT_ADDR_T_NONE) {
670 debug("DSPI: Can't get base address or size\n");
673 plat->regs_addr = addr;
675 plat->speed_hz = fdtdec_get_int(blob,
676 node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
678 debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
679 &plat->regs_addr, plat->speed_hz,
680 plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
681 plat->num_chipselect);
686 static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen,
687 const void *dout, void *din, unsigned long flags)
689 struct fsl_dspi_priv *priv;
690 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
694 priv = dev_get_priv(bus);
696 return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags);
699 static int fsl_dspi_set_speed(struct udevice *bus, uint speed)
701 struct fsl_dspi_priv *priv = dev_get_priv(bus);
703 return fsl_dspi_cfg_speed(priv, speed);
706 static int fsl_dspi_set_mode(struct udevice *bus, uint mode)
708 struct fsl_dspi_priv *priv = dev_get_priv(bus);
710 debug("DSPI set_mode: mode 0x%x.\n", mode);
713 * We store some chipselect special configure value in priv->ctar_val,
714 * and we can't get the correct chipselect number here,
715 * so just store mode value.
716 * Do really configuration when claim_bus.
723 static const struct dm_spi_ops fsl_dspi_ops = {
724 .claim_bus = fsl_dspi_claim_bus,
725 .release_bus = fsl_dspi_release_bus,
726 .xfer = fsl_dspi_xfer,
727 .set_speed = fsl_dspi_set_speed,
728 .set_mode = fsl_dspi_set_mode,
731 static const struct udevice_id fsl_dspi_ids[] = {
732 { .compatible = "fsl,vf610-dspi" },
736 U_BOOT_DRIVER(fsl_dspi) = {
739 .of_match = fsl_dspi_ids,
740 .ops = &fsl_dspi_ops,
741 .ofdata_to_platdata = fsl_dspi_ofdata_to_platdata,
742 .platdata_auto_alloc_size = sizeof(struct fsl_dspi_platdata),
743 .priv_auto_alloc_size = sizeof(struct fsl_dspi_priv),
744 .probe = fsl_dspi_probe,
745 .child_pre_probe = fsl_dspi_child_pre_probe,
746 .bind = fsl_dspi_bind,