2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Padmavathi Venna <padma.v@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clk.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/pinmux.h>
17 #include <asm/arch-exynos/spi.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 /* Information about each SPI controller */
24 enum periph_id periph_id;
25 s32 frequency; /* Default clock frequency, -1 for none */
26 struct exynos_spi *regs;
27 int inited; /* 1 if this bus is ready for use */
29 uint deactivate_delay_us; /* Delay to wait after deactivate */
32 /* A list of spi buses that we know about */
33 static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS];
34 static unsigned int bus_count;
36 struct exynos_spi_slave {
37 struct spi_slave slave;
38 struct exynos_spi *regs;
39 unsigned int freq; /* Default frequency */
41 enum periph_id periph_id; /* Peripheral ID for this device */
42 unsigned int fifo_size;
44 struct spi_bus *bus; /* Pointer to our SPI bus info */
45 ulong last_transaction_us; /* Time of last transaction end */
48 static struct spi_bus *spi_get_bus(unsigned dev_index)
50 if (dev_index < bus_count)
51 return &spi_bus[dev_index];
52 debug("%s: invalid bus %d", __func__, dev_index);
57 static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave)
59 return container_of(slave, struct exynos_spi_slave, slave);
63 * Setup the driver private data
65 * @param bus ID of the bus that the slave is attached to
66 * @param cs ID of the chip select connected to the slave
67 * @param max_hz Required spi frequency
68 * @param mode Required spi mode (clk polarity, clk phase and
70 * @return new device or NULL
72 struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
73 unsigned int max_hz, unsigned int mode)
75 struct exynos_spi_slave *spi_slave;
78 if (!spi_cs_is_valid(busnum, cs)) {
79 debug("%s: Invalid bus/chip select %d, %d\n", __func__,
84 spi_slave = spi_alloc_slave(struct exynos_spi_slave, busnum, cs);
86 debug("%s: Could not allocate spi_slave\n", __func__);
90 bus = &spi_bus[busnum];
92 spi_slave->regs = bus->regs;
93 spi_slave->mode = mode;
94 spi_slave->periph_id = bus->periph_id;
95 if (bus->periph_id == PERIPH_ID_SPI1 ||
96 bus->periph_id == PERIPH_ID_SPI2)
97 spi_slave->fifo_size = 64;
99 spi_slave->fifo_size = 256;
101 spi_slave->skip_preamble = 0;
102 spi_slave->last_transaction_us = timer_get_us();
104 spi_slave->freq = bus->frequency;
106 spi_slave->freq = min(max_hz, spi_slave->freq);
108 return &spi_slave->slave;
112 * Free spi controller
114 * @param slave Pointer to spi_slave to which controller has to
117 void spi_free_slave(struct spi_slave *slave)
119 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
125 * Flush spi tx, rx fifos and reset the SPI controller
127 * @param slave Pointer to spi_slave to which controller has to
130 static void spi_flush_fifo(struct spi_slave *slave)
132 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
133 struct exynos_spi *regs = spi_slave->regs;
135 clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
136 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
137 setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
141 * Initialize the spi base registers, set the required clock frequency and
142 * initialize the gpios
144 * @param slave Pointer to spi_slave to which controller has to
146 * @return zero on success else a negative value
148 int spi_claim_bus(struct spi_slave *slave)
150 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
151 struct exynos_spi *regs = spi_slave->regs;
155 ret = set_spi_clk(spi_slave->periph_id,
158 debug("%s: Failed to setup spi clock\n", __func__);
162 exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE);
164 spi_flush_fifo(slave);
166 reg = readl(®s->ch_cfg);
167 reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
169 if (spi_slave->mode & SPI_CPHA)
170 reg |= SPI_CH_CPHA_B;
172 if (spi_slave->mode & SPI_CPOL)
173 reg |= SPI_CH_CPOL_L;
175 writel(reg, ®s->ch_cfg);
176 writel(SPI_FB_DELAY_180, ®s->fb_clk);
182 * Reset the spi H/W and flush the tx and rx fifos
184 * @param slave Pointer to spi_slave to which controller has to
187 void spi_release_bus(struct spi_slave *slave)
189 spi_flush_fifo(slave);
192 static void spi_get_fifo_levels(struct exynos_spi *regs,
193 int *rx_lvl, int *tx_lvl)
195 uint32_t spi_sts = readl(®s->spi_sts);
197 *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
198 *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
202 * If there's something to transfer, do a software reset and set a
205 * @param regs SPI peripheral registers
206 * @param count Number of bytes to transfer
208 static void spi_request_bytes(struct exynos_spi *regs, int count)
210 assert(count && count < (1 << 16));
211 setbits_le32(®s->ch_cfg, SPI_CH_RST);
212 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
213 writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
216 static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
217 void **dinp, void const **doutp, unsigned long flags)
219 struct exynos_spi *regs = spi_slave->regs;
221 const uchar *txp = *doutp;
223 uint out_bytes, in_bytes;
225 unsigned start = get_timer(0);
228 out_bytes = in_bytes = todo;
230 stopping = spi_slave->skip_preamble && (flags & SPI_XFER_END) &&
231 !(spi_slave->mode & SPI_SLAVE);
234 * If there's something to send, do a software reset and set a
237 spi_request_bytes(regs, todo);
240 * Bytes are transmitted/received in pairs. Wait to receive all the
241 * data because then transmission will be done as well.
248 /* Keep the fifos full/empty. */
249 spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
250 if (tx_lvl < spi_slave->fifo_size && out_bytes) {
251 temp = txp ? *txp++ : 0xff;
252 writel(temp, ®s->tx_data);
256 temp = readl(®s->rx_data);
257 if (spi_slave->skip_preamble) {
258 if (temp == SPI_PREAMBLE_END_BYTE) {
259 spi_slave->skip_preamble = 0;
268 } else if (!toread) {
270 * We have run out of input data, but haven't read
271 * enough bytes after the preamble yet. Read some more,
272 * and make sure that we transmit dummy bytes too, to
276 out_bytes = in_bytes;
279 spi_request_bytes(regs, toread);
281 if (spi_slave->skip_preamble && get_timer(start) > 100) {
282 printf("SPI timeout: in_bytes=%d, out_bytes=%d, ",
283 in_bytes, out_bytes);
295 * Transfer and receive data
297 * @param slave Pointer to spi_slave to which controller has to
299 * @param bitlen No of bits to tranfer or receive
300 * @param dout Pointer to transfer buffer
301 * @param din Pointer to receive buffer
302 * @param flags Flags for transfer begin and end
303 * @return zero on success else a negative value
305 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
306 void *din, unsigned long flags)
308 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
313 /* spi core configured to do 8 bit transfers */
315 debug("Non byte aligned SPI transfer.\n");
319 /* Start the transaction, if necessary. */
320 if ((flags & SPI_XFER_BEGIN))
321 spi_cs_activate(slave);
323 /* Exynos SPI limits each transfer to 65535 bytes */
324 bytelen = bitlen / 8;
325 for (upto = 0; !ret && upto < bytelen; upto += todo) {
326 todo = min(bytelen - upto, (1 << 16) - 1);
327 ret = spi_rx_tx(spi_slave, todo, &din, &dout, flags);
332 /* Stop the transaction, if necessary. */
333 if ((flags & SPI_XFER_END) && !(spi_slave->mode & SPI_SLAVE)) {
334 spi_cs_deactivate(slave);
335 if (spi_slave->skip_preamble) {
336 assert(!spi_slave->skip_preamble);
337 debug("Failed to complete premable transaction\n");
346 * Validates the bus and chip select numbers
348 * @param bus ID of the bus that the slave is attached to
349 * @param cs ID of the chip select connected to the slave
350 * @return one on success else zero
352 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
354 return spi_get_bus(bus) && cs == 0;
358 * Activate the CS by driving it LOW
360 * @param slave Pointer to spi_slave to which controller has to
363 void spi_cs_activate(struct spi_slave *slave)
365 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
367 /* If it's too soon to do another transaction, wait */
368 if (spi_slave->bus->deactivate_delay_us &&
369 spi_slave->last_transaction_us) {
370 ulong delay_us; /* The delay completed so far */
371 delay_us = timer_get_us() - spi_slave->last_transaction_us;
372 if (delay_us < spi_slave->bus->deactivate_delay_us)
373 udelay(spi_slave->bus->deactivate_delay_us - delay_us);
376 clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
377 debug("Activate CS, bus %d\n", spi_slave->slave.bus);
378 spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
380 /* Remember time of this transaction so we can honour the bus delay */
381 if (spi_slave->bus->deactivate_delay_us)
382 spi_slave->last_transaction_us = timer_get_us();
386 * Deactivate the CS by driving it HIGH
388 * @param slave Pointer to spi_slave to which controller has to
391 void spi_cs_deactivate(struct spi_slave *slave)
393 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
395 setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
396 debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);
399 static inline struct exynos_spi *get_spi_base(int dev_index)
402 return (struct exynos_spi *)samsung_get_base_spi() + dev_index;
404 return (struct exynos_spi *)samsung_get_base_spi_isp() +
409 * Read the SPI config from the device tree node.
411 * @param blob FDT blob to read from
412 * @param node Node offset to read from
413 * @param bus SPI bus structure to fill with information
414 * @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing
416 #ifdef CONFIG_OF_CONTROL
417 static int spi_get_config(const void *blob, int node, struct spi_bus *bus)
420 bus->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
421 bus->periph_id = pinmux_decode_periph_id(blob, node);
423 if (bus->periph_id == PERIPH_ID_NONE) {
424 debug("%s: Invalid peripheral ID %d\n", __func__,
426 return -FDT_ERR_NOTFOUND;
429 /* Use 500KHz as a suitable default */
430 bus->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
432 bus->deactivate_delay_us = fdtdec_get_int(blob, node,
433 "spi-deactivate-delay", 0);
439 * Process a list of nodes, adding them to our list of SPI ports.
441 * @param blob fdt blob
442 * @param node_list list of nodes to process (any <=0 are ignored)
443 * @param count number of nodes to process
444 * @param is_dvc 1 if these are DVC ports, 0 if standard I2C
445 * @return 0 if ok, -1 on error
447 static int process_nodes(const void *blob, int node_list[], int count)
451 /* build the i2c_controllers[] for each controller */
452 for (i = 0; i < count; i++) {
453 int node = node_list[i];
460 if (spi_get_config(blob, node, bus)) {
461 printf("exynos spi_init: failed to decode bus %d\n",
466 debug("spi: controller bus %d at %p, periph_id %d\n",
467 i, bus->regs, bus->periph_id);
477 * Set up a new SPI slave for an fdt node
479 * @param blob Device tree blob
480 * @param node SPI peripheral node to use
481 * @return 0 if ok, -1 on error
483 struct spi_slave *spi_setup_slave_fdt(const void *blob, int node,
484 unsigned int cs, unsigned int max_hz, unsigned int mode)
489 for (i = 0, bus = spi_bus; i < bus_count; i++, bus++) {
490 if (bus->node == node)
491 return spi_setup_slave(i, cs, max_hz, mode);
494 debug("%s: Failed to find bus node %d\n", __func__, node);
498 /* Sadly there is no error return from this function */
503 #ifdef CONFIG_OF_CONTROL
504 int node_list[EXYNOS5_SPI_NUM_CONTROLLERS];
505 const void *blob = gd->fdt_blob;
507 count = fdtdec_find_aliases_for_id(blob, "spi",
508 COMPAT_SAMSUNG_EXYNOS_SPI, node_list,
509 EXYNOS5_SPI_NUM_CONTROLLERS);
510 if (process_nodes(blob, node_list, count))
516 for (count = 0; count < EXYNOS5_SPI_NUM_CONTROLLERS; count++) {
517 bus = &spi_bus[count];
518 bus->regs = get_spi_base(count);
519 bus->periph_id = PERIPH_ID_SPI0 + count;
521 /* Although Exynos5 supports upto 50Mhz speed,
522 * we are setting it to 10Mhz for safe side
524 bus->frequency = 10000000;
527 bus_count = EXYNOS5_SPI_NUM_CONTROLLERS;