2 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
4 * Driver for SPI controller on DaVinci. Based on atmel_spi.c
7 * Copyright (C) 2007 Atmel Corporation
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/hardware.h>
17 struct davinci_spi_regs {
18 dv_reg gcr0; /* 0x00 */
19 dv_reg gcr1; /* 0x04 */
20 dv_reg int0; /* 0x08 */
21 dv_reg lvl; /* 0x0c */
22 dv_reg flg; /* 0x10 */
23 dv_reg pc0; /* 0x14 */
24 dv_reg pc1; /* 0x18 */
25 dv_reg pc2; /* 0x1c */
26 dv_reg pc3; /* 0x20 */
27 dv_reg pc4; /* 0x24 */
28 dv_reg pc5; /* 0x28 */
30 dv_reg dat0; /* 0x38 */
31 dv_reg dat1; /* 0x3c */
32 dv_reg buf; /* 0x40 */
33 dv_reg emu; /* 0x44 */
34 dv_reg delay; /* 0x48 */
35 dv_reg def; /* 0x4c */
36 dv_reg fmt0; /* 0x50 */
37 dv_reg fmt1; /* 0x54 */
38 dv_reg fmt2; /* 0x58 */
39 dv_reg fmt3; /* 0x5c */
40 dv_reg intvec0; /* 0x60 */
41 dv_reg intvec1; /* 0x64 */
44 #define BIT(x) (1 << (x))
47 #define SPIGCR0_SPIENA_MASK 0x1
48 #define SPIGCR0_SPIRST_MASK 0x0
51 #define SPIGCR1_CLKMOD_MASK BIT(1)
52 #define SPIGCR1_MASTER_MASK BIT(0)
53 #define SPIGCR1_SPIENA_MASK BIT(24)
56 #define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */
57 #define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */
58 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
59 #define SPIPC0_EN0FUN_MASK BIT(0)
62 #define SPIFMT_SHIFTDIR_SHIFT 20
63 #define SPIFMT_POLARITY_SHIFT 17
64 #define SPIFMT_PHASE_SHIFT 16
65 #define SPIFMT_PRESCALE_SHIFT 8
68 #define SPIDAT1_CSHOLD_SHIFT 28
69 #define SPIDAT1_CSNR_SHIFT 16
72 #define SPI_C2TDELAY_SHIFT 24
73 #define SPI_T2CDELAY_SHIFT 16
76 #define SPIBUF_RXEMPTY_MASK BIT(31)
77 #define SPIBUF_TXFULL_MASK BIT(29)
80 #define SPIDEF_CSDEF0_MASK BIT(0)
83 #define SPI0_BASE CONFIG_SYS_SPI_BASE
85 * Define default SPI0_NUM_CS as 1 for existing platforms that uses this
86 * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
87 * if more than one CS is supported and by defining CONFIG_SYS_SPI0.
89 #ifndef CONFIG_SYS_SPI0
92 #define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS
96 * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
97 * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
99 #ifdef CONFIG_SYS_SPI1
101 #define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS
102 #define SPI1_BASE CONFIG_SYS_SPI1_BASE
106 * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
107 * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
109 #ifdef CONFIG_SYS_SPI2
111 #define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS
112 #define SPI2_BASE CONFIG_SYS_SPI2_BASE
115 struct davinci_spi_slave {
116 struct spi_slave slave;
117 struct davinci_spi_regs *regs;
121 static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
123 return container_of(slave, struct davinci_spi_slave, slave);
131 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
132 unsigned int max_hz, unsigned int mode)
134 struct davinci_spi_slave *ds;
136 if (!spi_cs_is_valid(bus, cs))
139 ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs);
145 ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
147 #ifdef CONFIG_SYS_SPI1
149 ds->regs = (struct davinci_spi_regs *)SPI1_BASE;
152 #ifdef CONFIG_SYS_SPI2
154 ds->regs = (struct davinci_spi_regs *)SPI2_BASE;
157 default: /* Invalid bus number */
166 void spi_free_slave(struct spi_slave *slave)
168 struct davinci_spi_slave *ds = to_davinci_spi(slave);
173 int spi_claim_bus(struct spi_slave *slave)
175 struct davinci_spi_slave *ds = to_davinci_spi(slave);
178 /* Enable the SPI hardware */
179 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
181 writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
183 /* Set master mode, powered up and not activated */
184 writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
186 /* CS, CLK, SIMO and SOMI are functional pins */
187 writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK |
188 SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
191 scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
194 * Use following format:
195 * character length = 8,
196 * clock signal delayed by half clk cycle,
197 * clock low in idle state - Mode 0,
198 * MSB shifted out first
200 writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
201 (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
204 * Including a minor delay. No science here. Should be good even with
207 writel((50 << SPI_C2TDELAY_SHIFT) |
208 (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
210 /* default chip select register */
211 writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
214 writel(0, &ds->regs->int0);
215 writel(0, &ds->regs->lvl);
218 writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
223 void spi_release_bus(struct spi_slave *slave)
225 struct davinci_spi_slave *ds = to_davinci_spi(slave);
227 /* Disable the SPI hardware */
228 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
232 * This functions needs to act like a macro to avoid pipeline reloads in the
233 * loops below. Use always_inline. This gains us about 160KiB/s and the bloat
234 * appears to be zero bytes (da830).
236 __attribute__((always_inline))
237 static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
242 writel(data, &ds->regs->dat1);
244 /* wait for the data to clock in/out */
245 while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK)
251 static int davinci_spi_read(struct spi_slave *slave, unsigned int len,
252 u8 *rxp, unsigned long flags)
254 struct davinci_spi_slave *ds = to_davinci_spi(slave);
255 unsigned int data1_reg_val;
257 /* enable CS hold, CS[n] and clear the data bits */
258 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
259 (slave->cs << SPIDAT1_CSNR_SHIFT));
261 /* wait till TXFULL is deasserted */
262 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
265 /* preload the TX buffer to avoid clock starvation */
266 writel(data1_reg_val, &ds->regs->dat1);
268 /* keep reading 1 byte until only 1 byte left */
270 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val);
272 /* clear CS hold when we reach the end */
273 if (flags & SPI_XFER_END)
274 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
276 /* read the last byte */
277 *rxp = davinci_spi_xfer_data(ds, data1_reg_val);
282 static int davinci_spi_write(struct spi_slave *slave, unsigned int len,
283 const u8 *txp, unsigned long flags)
285 struct davinci_spi_slave *ds = to_davinci_spi(slave);
286 unsigned int data1_reg_val;
288 /* enable CS hold and clear the data bits */
289 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
290 (slave->cs << SPIDAT1_CSNR_SHIFT));
292 /* wait till TXFULL is deasserted */
293 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
296 /* preload the TX buffer to avoid clock starvation */
298 writel(data1_reg_val | *txp++, &ds->regs->dat1);
302 /* keep writing 1 byte until only 1 byte left */
304 davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
306 /* clear CS hold when we reach the end */
307 if (flags & SPI_XFER_END)
308 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
310 /* write the last byte */
311 davinci_spi_xfer_data(ds, data1_reg_val | *txp);
316 #ifndef CONFIG_SPI_HALF_DUPLEX
317 static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len,
318 u8 *rxp, const u8 *txp, unsigned long flags)
320 struct davinci_spi_slave *ds = to_davinci_spi(slave);
321 unsigned int data1_reg_val;
323 /* enable CS hold and clear the data bits */
324 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
325 (slave->cs << SPIDAT1_CSNR_SHIFT));
327 /* wait till TXFULL is deasserted */
328 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
331 /* keep reading and writing 1 byte until only 1 byte left */
333 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
335 /* clear CS hold when we reach the end */
336 if (flags & SPI_XFER_END)
337 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
339 /* read and write the last byte */
340 *rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp);
346 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
347 const void *dout, void *din, unsigned long flags)
352 /* Finish any previously submitted transfers */
356 * It's not clear how non-8-bit-aligned transfers are supposed to be
357 * represented as a stream of bytes...this is a limitation of
358 * the current SPI interface - here we terminate on receiving such a
362 /* Errors always terminate an ongoing transfer */
363 flags |= SPI_XFER_END;
370 return davinci_spi_read(slave, len, din, flags);
372 return davinci_spi_write(slave, len, dout, flags);
373 #ifndef CONFIG_SPI_HALF_DUPLEX
375 return davinci_spi_read_write(slave, len, din, dout, flags);
377 printf("SPI full duplex transaction requested with "
378 "CONFIG_SPI_HALF_DUPLEX defined.\n");
379 flags |= SPI_XFER_END;
383 if (flags & SPI_XFER_END) {
385 davinci_spi_write(slave, 1, &dummy, flags);
390 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
396 if (cs < SPI0_NUM_CS)
399 #ifdef CONFIG_SYS_SPI1
401 if (cs < SPI1_NUM_CS)
405 #ifdef CONFIG_SYS_SPI2
407 if (cs < SPI2_NUM_CS)
412 /* Invalid bus number. Do nothing */
418 void spi_cs_activate(struct spi_slave *slave)
423 void spi_cs_deactivate(struct spi_slave *slave)