1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2000-2003
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * Support for DM and DT, non-DM code removed.
11 * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
13 * TODO: fsl_dspi.c should work as a driver for the DSPI module.
18 #include <dm/platform_data/spi_coldfire.h>
21 #include <asm/coldfire/dspi.h>
24 struct coldfire_spi_priv {
31 DECLARE_GLOBAL_DATA_PTR;
33 #ifndef CONFIG_SPI_IDLE_VAL
34 #if defined(CONFIG_SPI_MMC)
35 #define CONFIG_SPI_IDLE_VAL 0xFFFF
37 #define CONFIG_SPI_IDLE_VAL 0x0
44 * bit 31 - 28: Transfer size 3 to 16 bits
45 * 27 - 26: PCS to SCK delay prescaler
46 * 25 - 24: After SCK delay prescaler
47 * 23 - 22: Delay after transfer prescaler
48 * 21 : Allow overwrite for bit 31-22 and bit 20-8
49 * 20 : Double baud rate
50 * 19 - 16: PCS to SCK delay scaler
51 * 15 - 12: After SCK delay scaler
52 * 11 - 8: Delay after transfer scaler
53 * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
55 #define SPI_MODE_MOD 0x00200000
56 #define SPI_MODE_DBLRATE 0x00100000
58 #define SPI_MODE_XFER_SZ_MASK 0xf0000000
59 #define SPI_MODE_DLY_PRE_MASK 0x0fc00000
60 #define SPI_MODE_DLY_SCA_MASK 0x000fff00
62 #define MCF_FRM_SZ_16BIT DSPI_CTAR_TRSZ(0xf)
63 #define MCF_DSPI_SPEED_BESTMATCH 0x7FFFFFFF
64 #define MCF_DSPI_MAX_CTAR_REGS 8
67 #define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
68 #define MCF_DSPI_DEFAULT_MAX_CS 4
69 #define MCF_DSPI_DEFAULT_MODE 0
71 #define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
72 DSPI_CTAR_PCSSCK_1CLK | \
75 DSPI_CTAR_CSSCK(0) | \
80 #define MCF_CTAR_MODE_MASK (MCF_FRM_SZ_16BIT | \
81 DSPI_CTAR_PCSSCK(3) | \
82 DSPI_CTAR_PASC_7CLK | \
84 DSPI_CTAR_CSSCK(0x0f) | \
85 DSPI_CTAR_ASC(0x0f) | \
88 #define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16))
90 static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
94 * Need to check fifo level here
96 while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
99 writel(ctrl | data, &cfspi->regs->tfr);
102 static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
105 while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
108 return readw(&cfspi->regs->rfr);
111 static int coldfire_spi_claim_bus(struct udevice *dev)
113 struct udevice *bus = dev->parent;
114 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
115 struct dspi *dspi = cfspi->regs;
116 struct dm_spi_slave_platdata *slave_plat =
117 dev_get_parent_platdata(dev);
119 if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
122 /* Clear FIFO and resume transfer */
123 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
125 dspi_chip_select(slave_plat->cs);
130 static int coldfire_spi_release_bus(struct udevice *dev)
132 struct udevice *bus = dev->parent;
133 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
134 struct dspi *dspi = cfspi->regs;
135 struct dm_spi_slave_platdata *slave_plat =
136 dev_get_parent_platdata(dev);
139 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
141 dspi_chip_unselect(slave_plat->cs);
146 static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
147 const void *dout, void *din,
150 struct udevice *bus = dev_get_parent(dev);
151 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
152 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
153 u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
154 u8 *spi_rd = NULL, *spi_wr = NULL;
156 uint len = bitlen >> 3;
158 if (cfspi->charbit == 16) {
160 spi_wr16 = (u16 *)dout;
161 spi_rd16 = (u16 *)din;
167 if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
168 ctrl |= DSPI_TFR_CONT;
170 ctrl = setup_ctrl(ctrl, slave_plat->cs);
173 int tmp_len = len - 1;
177 if (cfspi->charbit == 16)
178 cfspi_tx(cfspi, ctrl, *spi_wr16++);
180 cfspi_tx(cfspi, ctrl, *spi_wr++);
185 cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
186 if (cfspi->charbit == 16)
187 *spi_rd16++ = cfspi_rx(cfspi);
189 *spi_rd++ = cfspi_rx(cfspi);
193 len = 1; /* remaining byte */
196 if (flags & SPI_XFER_END)
197 ctrl &= ~DSPI_TFR_CONT;
201 if (cfspi->charbit == 16)
202 cfspi_tx(cfspi, ctrl, *spi_wr16);
204 cfspi_tx(cfspi, ctrl, *spi_wr);
209 cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
210 if (cfspi->charbit == 16)
211 *spi_rd16 = cfspi_rx(cfspi);
213 *spi_rd = cfspi_rx(cfspi);
217 cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
224 static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
226 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
227 struct dspi *dspi = cfspi->regs;
228 int prescaler[] = { 2, 3, 5, 7 };
232 256, 512, 1024, 2048,
233 4096, 8192, 16384, 32768
235 int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
236 int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
239 cfspi->baudrate = max_hz;
241 /* Read current setup */
242 bus_setup = readl(&dspi->ctar[bus->seq]);
244 tmp = (prescaler[3] * scaler[15]);
245 /* Maximum and minimum baudrate it can handle */
246 if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
247 (cfspi->baudrate < (gd->bus_clk / tmp))) {
248 printf("Exceed baudrate limitation: Max %d - Min %d\n",
249 (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
253 /* Activate Double Baud when it exceed 1/4 the bus clk */
254 if ((bus_setup & DSPI_CTAR_DBR) ||
255 (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
256 bus_setup |= DSPI_CTAR_DBR;
260 /* Overwrite default value set in platform configuration file */
261 if (cfspi->mode & SPI_MODE_MOD) {
263 * Check to see if it is enabled by default in platform
264 * config, or manual setting passed by mode parameter
266 if (cfspi->mode & SPI_MODE_DBLRATE) {
267 bus_setup |= DSPI_CTAR_DBR;
272 pbrcnt = sizeof(prescaler) / sizeof(int);
273 brcnt = sizeof(scaler) / sizeof(int);
275 /* baudrate calculation - to closer value, may not be exact match */
276 for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
277 baud_speed = gd->bus_clk / prescaler[i];
278 for (j = 0; j < brcnt; j++) {
279 tmp = (baud_speed / scaler[j]) * (1 + dbr);
281 if (tmp > cfspi->baudrate)
282 diff = tmp - cfspi->baudrate;
284 diff = cfspi->baudrate - tmp;
286 if (diff < bestmatch) {
294 bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
295 bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
296 writel(bus_setup, &dspi->ctar[bus->seq]);
301 static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
303 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
304 struct dspi *dspi = cfspi->regs;
309 if (cfspi->mode & SPI_CPOL)
310 bus_setup |= DSPI_CTAR_CPOL;
311 if (cfspi->mode & SPI_CPHA)
312 bus_setup |= DSPI_CTAR_CPHA;
313 if (cfspi->mode & SPI_LSB_FIRST)
314 bus_setup |= DSPI_CTAR_LSBFE;
316 /* Overwrite default value set in platform configuration file */
317 if (cfspi->mode & SPI_MODE_MOD) {
318 if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
320 readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT;
323 ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
325 /* PSCSCK, PASC, PDT */
326 bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
328 bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
331 (readl(&dspi->ctar[bus->seq]) & MCF_CTAR_MODE_MASK);
335 ((readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT) ==
336 MCF_FRM_SZ_16BIT) ? 16 : 8;
338 setbits_be32(&dspi->ctar[bus->seq], bus_setup);
343 static int coldfire_spi_probe(struct udevice *bus)
345 struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
346 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
347 struct dspi *dspi = cfspi->regs;
350 cfspi->regs = (struct dspi *)plat->regs_addr;
352 cfspi->baudrate = plat->speed_hz;
353 cfspi->mode = plat->mode;
355 for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
356 unsigned int ctar = 0;
358 if (plat->ctar[i][0] == 0)
361 ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
362 DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
363 DSPI_CTAR_PASC(plat->ctar[i][2]) |
364 DSPI_CTAR_PDT(plat->ctar[i][3]) |
365 DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
366 DSPI_CTAR_ASC(plat->ctar[i][5]) |
367 DSPI_CTAR_DT(plat->ctar[i][6]) |
368 DSPI_CTAR_BR(plat->ctar[i][7]);
370 writel(ctar, &cfspi->regs->ctar[i]);
374 for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
375 writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
377 dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
378 DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
379 DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
380 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
389 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
390 static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
393 struct coldfire_spi_platdata *plat = bus->platdata;
394 const void *blob = gd->fdt_blob;
395 int node = dev_of_offset(bus);
398 addr = devfdt_get_addr(bus);
399 if (addr == FDT_ADDR_T_NONE)
402 plat->regs_addr = addr;
404 plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
405 MCF_DSPI_DEFAULT_MAX_CS);
407 plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
408 MCF_DSPI_DEFAULT_SCK_FREQ);
410 plat->mode = fdtdec_get_int(blob, node, "spi-mode",
411 MCF_DSPI_DEFAULT_MODE);
413 memset(plat->ctar, 0, sizeof(plat->ctar));
415 ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
420 ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
422 if (ctar_regs > MAX_CTAR_REGS)
423 ctar_regs = MAX_CTAR_REGS;
425 for (i = 0; i < ctar_regs; i++) {
426 for (q = 0; q < MAX_CTAR_FIELDS; q++)
427 plat->ctar[i][q] = *ctar++;
431 debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
432 (void *)plat->regs_addr,
433 plat->speed_hz, plat->num_cs, plat->mode);
438 static const struct udevice_id coldfire_spi_ids[] = {
439 { .compatible = "fsl,mcf-dspi" },
444 static const struct dm_spi_ops coldfire_spi_ops = {
445 .claim_bus = coldfire_spi_claim_bus,
446 .release_bus = coldfire_spi_release_bus,
447 .xfer = coldfire_spi_xfer,
448 .set_speed = coldfire_spi_set_speed,
449 .set_mode = coldfire_spi_set_mode,
452 U_BOOT_DRIVER(coldfire_spi) = {
453 .name = "spi_coldfire",
455 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
456 .of_match = coldfire_spi_ids,
457 .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
458 .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
460 .probe = coldfire_spi_probe,
461 .ops = &coldfire_spi_ops,
462 .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),