drivers/spi/cadence_qspi_apb.c

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *  - Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  *  - Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *  - Neither the name of the Altera Corporation nor the
  13  *    names of its contributors may be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <linux/errno.h>
  31 #include <wait_bit.h>
  32 #include <spi.h>
  33 #include "cadence_qspi.h"
  34
  35 #define CQSPI_REG_POLL_US                       (1) /* 1us */
  36 #define CQSPI_REG_RETRY                         (10000)
  37 #define CQSPI_POLL_IDLE_RETRY                   (3)
  38
  39 #define CQSPI_FIFO_WIDTH                        (4)
  40
  41 #define CQSPI_REG_SRAM_THRESHOLD_WORDS          (50)
  42
  43 /* Transfer mode */
  44 #define CQSPI_INST_TYPE_SINGLE                  (0)
  45 #define CQSPI_INST_TYPE_DUAL                    (1)
  46 #define CQSPI_INST_TYPE_QUAD                    (2)
  47
  48 #define CQSPI_STIG_DATA_LEN_MAX                 (8)
  49
  50 #define CQSPI_DUMMY_CLKS_PER_BYTE               (8)
  51 #define CQSPI_DUMMY_BYTES_MAX                   (4)
  52
  53
  54 #define CQSPI_REG_SRAM_FILL_THRESHOLD   \
  55         ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
  56 /****************************************************************************
  57  * Controller's configuration and status register (offset from QSPI_BASE)
  58  ****************************************************************************/
  59 #define CQSPI_REG_CONFIG                        0x00
  60 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
  61 #define CQSPI_REG_CONFIG_CLK_POL                BIT(1)
  62 #define CQSPI_REG_CONFIG_CLK_PHA                BIT(2)
  63 #define CQSPI_REG_CONFIG_DIRECT_MASK            BIT(7)
  64 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
  65 #define CQSPI_REG_CONFIG_XIP_IMM_MASK           BIT(18)
  66 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
  67 #define CQSPI_REG_CONFIG_BAUD_LSB               19
  68 #define CQSPI_REG_CONFIG_IDLE_LSB               31
  69 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
  70 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
  71
  72 #define CQSPI_REG_RD_INSTR                      0x04
  73 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
  74 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
  75 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
  76 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
  77 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
  78 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
  79 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
  80 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
  81 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
  82 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
  83
  84 #define CQSPI_REG_WR_INSTR                      0x08
  85 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
  86
  87 #define CQSPI_REG_DELAY                         0x0C
  88 #define CQSPI_REG_DELAY_TSLCH_LSB               0
  89 #define CQSPI_REG_DELAY_TCHSH_LSB               8
  90 #define CQSPI_REG_DELAY_TSD2D_LSB               16
  91 #define CQSPI_REG_DELAY_TSHSL_LSB               24
  92 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
  93 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
  94 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
  95 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
  96
  97 #define CQSPI_REG_RD_DATA_CAPTURE               0x10
  98 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS        BIT(0)
  99 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB     1
 100 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK    0xF
 101
 102 #define CQSPI_REG_SIZE                          0x14
 103 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 104 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 105 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 106 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 107 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 108 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 109
 110 #define CQSPI_REG_SRAMPARTITION                 0x18
 111 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 112
 113 #define CQSPI_REG_REMAP                         0x24
 114 #define CQSPI_REG_MODE_BIT                      0x28
 115
 116 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 117 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 118 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 119 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 120 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 121
 122 #define CQSPI_REG_IRQSTATUS                     0x40
 123 #define CQSPI_REG_IRQMASK                       0x44
 124
 125 #define CQSPI_REG_INDIRECTRD                    0x60
 126 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 127 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 128 #define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK    BIT(2)
 129 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 130
 131 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 132 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 133 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 134
 135 #define CQSPI_REG_CMDCTRL                       0x90
 136 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 137 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 138 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 139 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 140 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 141 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 142 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 143 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 144 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 145 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 146 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 147 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 148 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 149 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 150 #define CQSPI_REG_CMDCTRL_OPCODE_MASK           0xFF
 151
 152 #define CQSPI_REG_INDIRECTWR                    0x70
 153 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 154 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 155 #define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK    BIT(2)
 156 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 157
 158 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 159 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 160 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 161
 162 #define CQSPI_REG_CMDADDRESS                    0x94
 163 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 164 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 165 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 166 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 167
 168 #define CQSPI_REG_IS_IDLE(base)                                 \
 169         ((readl(base + CQSPI_REG_CONFIG) >>             \
 170                 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
 171
 172 #define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns)           \
 173         ((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
 174
 175 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)                       \
 176         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 177         CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
 178
 179 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)                       \
 180         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 181         CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
 182
 183 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
 184         unsigned int addr_width)
 185 {
 186         unsigned int addr;
 187
 188         addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
 189
 190         if (addr_width == 4)
 191                 addr = (addr << 8) | addr_buf[3];
 192
 193         return addr;
 194 }
 195
 196 void cadence_qspi_apb_controller_enable(void *reg_base)
 197 {
 198         unsigned int reg;
 199         reg = readl(reg_base + CQSPI_REG_CONFIG);
 200         reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 201         writel(reg, reg_base + CQSPI_REG_CONFIG);
 202         return;
 203 }
 204
 205 void cadence_qspi_apb_controller_disable(void *reg_base)
 206 {
 207         unsigned int reg;
 208         reg = readl(reg_base + CQSPI_REG_CONFIG);
 209         reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 210         writel(reg, reg_base + CQSPI_REG_CONFIG);
 211         return;
 212 }
 213
 214 /* Return 1 if idle, otherwise return 0 (busy). */
 215 static unsigned int cadence_qspi_wait_idle(void *reg_base)
 216 {
 217         unsigned int start, count = 0;
 218         /* timeout in unit of ms */
 219         unsigned int timeout = 5000;
 220
 221         start = get_timer(0);
 222         for ( ; get_timer(start) < timeout ; ) {
 223                 if (CQSPI_REG_IS_IDLE(reg_base))
 224                         count++;
 225                 else
 226                         count = 0;
 227                 /*
 228                  * Ensure the QSPI controller is in true idle state after
 229                  * reading back the same idle status consecutively
 230                  */
 231                 if (count >= CQSPI_POLL_IDLE_RETRY)
 232                         return 1;
 233         }
 234
 235         /* Timeout, still in busy mode. */
 236         printf("QSPI: QSPI is still busy after poll for %d times.\n",
 237                CQSPI_REG_RETRY);
 238         return 0;
 239 }
 240
 241 void cadence_qspi_apb_readdata_capture(void *reg_base,
 242                                 unsigned int bypass, unsigned int delay)
 243 {
 244         unsigned int reg;
 245         cadence_qspi_apb_controller_disable(reg_base);
 246
 247         reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 248
 249         if (bypass)
 250                 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 251         else
 252                 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 253
 254         reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
 255                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
 256
 257         reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
 258                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
 259
 260         writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 261
 262         cadence_qspi_apb_controller_enable(reg_base);
 263         return;
 264 }
 265
 266 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 267         unsigned int ref_clk_hz, unsigned int sclk_hz)
 268 {
 269         unsigned int reg;
 270         unsigned int div;
 271
 272         cadence_qspi_apb_controller_disable(reg_base);
 273         reg = readl(reg_base + CQSPI_REG_CONFIG);
 274         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 275
 276         /*
 277          * The baud_div field in the config reg is 4 bits, and the ref clock is
 278          * divided by 2 * (baud_div + 1). Round up the divider to ensure the
 279          * SPI clock rate is less than or equal to the requested clock rate.
 280          */
 281         div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
 282
 283         /* ensure the baud rate doesn't exceed the max value */
 284         if (div > CQSPI_REG_CONFIG_BAUD_MASK)
 285                 div = CQSPI_REG_CONFIG_BAUD_MASK;
 286
 287         debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
 288               ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
 289
 290         reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
 291         writel(reg, reg_base + CQSPI_REG_CONFIG);
 292
 293         cadence_qspi_apb_controller_enable(reg_base);
 294         return;
 295 }
 296
 297 void cadence_qspi_apb_set_clk_mode(void *reg_base,
 298         unsigned int clk_pol, unsigned int clk_pha)
 299 {
 300         unsigned int reg;
 301
 302         cadence_qspi_apb_controller_disable(reg_base);
 303         reg = readl(reg_base + CQSPI_REG_CONFIG);
 304         reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
 305
 306         if (clk_pol)
 307                 reg |= CQSPI_REG_CONFIG_CLK_POL;
 308         if (clk_pha)
 309                 reg |= CQSPI_REG_CONFIG_CLK_PHA;
 310
 311         writel(reg, reg_base + CQSPI_REG_CONFIG);
 312
 313         cadence_qspi_apb_controller_enable(reg_base);
 314         return;
 315 }
 316
 317 void cadence_qspi_apb_chipselect(void *reg_base,
 318         unsigned int chip_select, unsigned int decoder_enable)
 319 {
 320         unsigned int reg;
 321
 322         cadence_qspi_apb_controller_disable(reg_base);
 323
 324         debug("%s : chipselect %d decode %d\n", __func__, chip_select,
 325               decoder_enable);
 326
 327         reg = readl(reg_base + CQSPI_REG_CONFIG);
 328         /* docoder */
 329         if (decoder_enable) {
 330                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 331         } else {
 332                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 333                 /* Convert CS if without decoder.
 334                  * CS0 to 4b'1110
 335                  * CS1 to 4b'1101
 336                  * CS2 to 4b'1011
 337                  * CS3 to 4b'0111
 338                  */
 339                 chip_select = 0xF & ~(1 << chip_select);
 340         }
 341
 342         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 343                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 344         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 345                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 346         writel(reg, reg_base + CQSPI_REG_CONFIG);
 347
 348         cadence_qspi_apb_controller_enable(reg_base);
 349         return;
 350 }
 351
 352 void cadence_qspi_apb_delay(void *reg_base,
 353         unsigned int ref_clk, unsigned int sclk_hz,
 354         unsigned int tshsl_ns, unsigned int tsd2d_ns,
 355         unsigned int tchsh_ns, unsigned int tslch_ns)
 356 {
 357         unsigned int ref_clk_ns;
 358         unsigned int sclk_ns;
 359         unsigned int tshsl, tchsh, tslch, tsd2d;
 360         unsigned int reg;
 361
 362         cadence_qspi_apb_controller_disable(reg_base);
 363
 364         /* Convert to ns. */
 365         ref_clk_ns = (1000000000) / ref_clk;
 366
 367         /* Convert to ns. */
 368         sclk_ns = (1000000000) / sclk_hz;
 369
 370         /* Plus 1 to round up 1 clock cycle. */
 371         tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
 372         tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
 373         tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
 374         tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
 375
 376         reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 377                         << CQSPI_REG_DELAY_TSHSL_LSB);
 378         reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 379                         << CQSPI_REG_DELAY_TCHSH_LSB);
 380         reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 381                         << CQSPI_REG_DELAY_TSLCH_LSB);
 382         reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 383                         << CQSPI_REG_DELAY_TSD2D_LSB);
 384         writel(reg, reg_base + CQSPI_REG_DELAY);
 385
 386         cadence_qspi_apb_controller_enable(reg_base);
 387         return;
 388 }
 389
 390 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 391 {
 392         unsigned reg;
 393
 394         cadence_qspi_apb_controller_disable(plat->regbase);
 395
 396         /* Configure the device size and address bytes */
 397         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 398         /* Clear the previous value */
 399         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 400         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 401         reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 402         reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
 403         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 404
 405         /* Configure the remap address register, no remap */
 406         writel(0, plat->regbase + CQSPI_REG_REMAP);
 407
 408         /* Indirect mode configurations */
 409         writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
 410
 411         /* Disable all interrupts */
 412         writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 413
 414         cadence_qspi_apb_controller_enable(plat->regbase);
 415         return;
 416 }
 417
 418 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
 419         unsigned int reg)
 420 {
 421         unsigned int retry = CQSPI_REG_RETRY;
 422
 423         /* Write the CMDCTRL without start execution. */
 424         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 425         /* Start execute */
 426         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 427         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 428
 429         while (retry--) {
 430                 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
 431                 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
 432                         break;
 433                 udelay(1);
 434         }
 435
 436         if (!retry) {
 437                 printf("QSPI: flash command execution timeout\n");
 438                 return -EIO;
 439         }
 440
 441         /* Polling QSPI idle status. */
 442         if (!cadence_qspi_wait_idle(reg_base))
 443                 return -EIO;
 444
 445         return 0;
 446 }
 447
 448 /* For command RDID, RDSR. */
 449 int cadence_qspi_apb_command_read(void *reg_base,
 450         unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
 451         u8 *rxbuf)
 452 {
 453         unsigned int reg;
 454         unsigned int read_len;
 455         int status;
 456
 457         if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
 458                 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
 459                        cmdlen, rxlen);
 460                 return -EINVAL;
 461         }
 462
 463         reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 464
 465         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 466
 467         /* 0 means 1 byte. */
 468         reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 469                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 470         status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 471         if (status != 0)
 472                 return status;
 473
 474         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 475
 476         /* Put the read value into rx_buf */
 477         read_len = (rxlen > 4) ? 4 : rxlen;
 478         memcpy(rxbuf, &reg, read_len);
 479         rxbuf += read_len;
 480
 481         if (rxlen > 4) {
 482                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 483
 484                 read_len = rxlen - read_len;
 485                 memcpy(rxbuf, &reg, read_len);
 486         }
 487         return 0;
 488 }
 489
 490 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
 491 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
 492         const u8 *cmdbuf, unsigned int txlen,  const u8 *txbuf)
 493 {
 494         unsigned int reg = 0;
 495         unsigned int addr_value;
 496         unsigned int wr_data;
 497         unsigned int wr_len;
 498
 499         if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
 500                 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
 501                        cmdlen, txlen);
 502                 return -EINVAL;
 503         }
 504
 505         reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 506
 507         if (cmdlen == 4 || cmdlen == 5) {
 508                 /* Command with address */
 509                 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 510                 /* Number of bytes to write. */
 511                 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 512                         << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 513                 /* Get address */
 514                 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
 515                         cmdlen >= 5 ? 4 : 3);
 516
 517                 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
 518         }
 519
 520         if (txlen) {
 521                 /* writing data = yes */
 522                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 523                 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 524                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 525
 526                 wr_len = txlen > 4 ? 4 : txlen;
 527                 memcpy(&wr_data, txbuf, wr_len);
 528                 writel(wr_data, reg_base +
 529                         CQSPI_REG_CMDWRITEDATALOWER);
 530
 531                 if (txlen > 4) {
 532                         txbuf += wr_len;
 533                         wr_len = txlen - wr_len;
 534                         memcpy(&wr_data, txbuf, wr_len);
 535                         writel(wr_data, reg_base +
 536                                 CQSPI_REG_CMDWRITEDATAUPPER);
 537                 }
 538         }
 539
 540         /* Execute the command */
 541         return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 542 }
 543
 544 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
 545 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 546         unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf)
 547 {
 548         unsigned int reg;
 549         unsigned int rd_reg;
 550         unsigned int addr_value;
 551         unsigned int dummy_clk;
 552         unsigned int dummy_bytes;
 553         unsigned int addr_bytes;
 554
 555         /*
 556          * Identify addr_byte. All NOR flash device drivers are using fast read
 557          * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
 558          * With that, the length is in value of 5 or 6. Only FRAM chip from
 559          * ramtron using normal read (which won't need dummy byte).
 560          * Unlikely NOR flash using normal read due to performance issue.
 561          */
 562         if (cmdlen >= 5)
 563                 /* to cater fast read where cmd + addr + dummy */
 564                 addr_bytes = cmdlen - 2;
 565         else
 566                 /* for normal read (only ramtron as of now) */
 567                 addr_bytes = cmdlen - 1;
 568
 569         /* Setup the indirect trigger address */
 570         writel((u32)plat->ahbbase,
 571                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 572
 573         /* Configure the opcode */
 574         rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 575
 576         if (rx_width & SPI_RX_QUAD)
 577                 /* Instruction and address at DQ0, data at DQ0-3. */
 578                 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 579
 580         /* Get address */
 581         addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 582         writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 583
 584         /* The remaining lenght is dummy bytes. */
 585         dummy_bytes = cmdlen - addr_bytes - 1;
 586         if (dummy_bytes) {
 587                 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
 588                         dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
 589
 590                 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 591 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
 592                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
 593 #else
 594                 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
 595 #endif
 596
 597                 /* Convert to clock cycles. */
 598                 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
 599                 /* Need to minus the mode byte (8 clocks). */
 600                 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
 601
 602                 if (dummy_clk)
 603                         rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 604                                 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 605         }
 606
 607         writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
 608
 609         /* set device size */
 610         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 611         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 612         reg |= (addr_bytes - 1);
 613         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 614         return 0;
 615 }
 616
 617 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
 618 {
 619         u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
 620         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 621         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 622 }
 623
 624 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
 625 {
 626         unsigned int timeout = 10000;
 627         u32 reg;
 628
 629         while (timeout--) {
 630                 reg = cadence_qspi_get_rd_sram_level(plat);
 631                 if (reg)
 632                         return reg;
 633                 udelay(1);
 634         }
 635
 636         return -ETIMEDOUT;
 637 }
 638
 639 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 640         unsigned int n_rx, u8 *rxbuf)
 641 {
 642         unsigned int remaining = n_rx;
 643         unsigned int bytes_to_read = 0;
 644         int ret;
 645
 646         writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
 647
 648         /* Start the indirect read transfer */
 649         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 650                plat->regbase + CQSPI_REG_INDIRECTRD);
 651
 652         while (remaining > 0) {
 653                 ret = cadence_qspi_wait_for_data(plat);
 654                 if (ret < 0) {
 655                         printf("Indirect write timed out (%i)\n", ret);
 656                         goto failrd;
 657                 }
 658
 659                 bytes_to_read = ret;
 660
 661                 while (bytes_to_read != 0) {
 662                         bytes_to_read *= CQSPI_FIFO_WIDTH;
 663                         bytes_to_read = bytes_to_read > remaining ?
 664                                         remaining : bytes_to_read;
 665                         /* Handle non-4-byte aligned access to avoid data abort. */
 666                         if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
 667                                 readsb(plat->ahbbase, rxbuf, bytes_to_read);
 668                         else
 669                                 readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
 670                         rxbuf += bytes_to_read;
 671                         remaining -= bytes_to_read;
 672                         bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
 673                 }
 674         }
 675
 676         /* Check indirect done status */
 677         ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
 678                            CQSPI_REG_INDIRECTRD_DONE_MASK, 1, 10, 0);
 679         if (ret) {
 680                 printf("Indirect read completion error (%i)\n", ret);
 681                 goto failrd;
 682         }
 683
 684         /* Clear indirect completion status */
 685         writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
 686                plat->regbase + CQSPI_REG_INDIRECTRD);
 687
 688         return 0;
 689
 690 failrd:
 691         /* Cancel the indirect read */
 692         writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
 693                plat->regbase + CQSPI_REG_INDIRECTRD);
 694         return ret;
 695 }
 696
 697 /* Opcode + Address (3/4 bytes) */
 698 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 699         unsigned int cmdlen, const u8 *cmdbuf)
 700 {
 701         unsigned int reg;
 702         unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
 703
 704         if (cmdlen < 4 || cmdbuf == NULL) {
 705                 printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
 706                        cmdlen, (unsigned int)cmdbuf);
 707                 return -EINVAL;
 708         }
 709         /* Setup the indirect trigger address */
 710         writel((u32)plat->ahbbase,
 711                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 712
 713         /* Configure the opcode */
 714         reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 715         writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
 716
 717         /* Setup write address. */
 718         reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 719         writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 720
 721         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 722         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 723         reg |= (addr_bytes - 1);
 724         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 725         return 0;
 726 }
 727
 728 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 729         unsigned int n_tx, const u8 *txbuf)
 730 {
 731         unsigned int page_size = plat->page_size;
 732         unsigned int remaining = n_tx;
 733         unsigned int write_bytes;
 734         int ret;
 735
 736         /* Configure the indirect read transfer bytes */
 737         writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
 738
 739         /* Start the indirect write transfer */
 740         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 741                plat->regbase + CQSPI_REG_INDIRECTWR);
 742
 743         while (remaining > 0) {
 744                 write_bytes = remaining > page_size ? page_size : remaining;
 745                 /* Handle non-4-byte aligned access to avoid data abort. */
 746                 if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
 747                         writesb(plat->ahbbase, txbuf, write_bytes);
 748                 else
 749                         writesl(plat->ahbbase, txbuf, write_bytes >> 2);
 750
 751                 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
 752                                    CQSPI_REG_SDRAMLEVEL_WR_MASK <<
 753                                    CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
 754                 if (ret) {
 755                         printf("Indirect write timed out (%i)\n", ret);
 756                         goto failwr;
 757                 }
 758
 759                 txbuf += write_bytes;
 760                 remaining -= write_bytes;
 761         }
 762
 763         /* Check indirect done status */
 764         ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
 765                            CQSPI_REG_INDIRECTWR_DONE_MASK, 1, 10, 0);
 766         if (ret) {
 767                 printf("Indirect write completion error (%i)\n", ret);
 768                 goto failwr;
 769         }
 770
 771         /* Clear indirect completion status */
 772         writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
 773                plat->regbase + CQSPI_REG_INDIRECTWR);
 774         return 0;
 775
 776 failwr:
 777         /* Cancel the indirect write */
 778         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 779                plat->regbase + CQSPI_REG_INDIRECTWR);
 780         return ret;
 781 }
 782
 783 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
 784 {
 785         unsigned int reg;
 786
 787         /* enter XiP mode immediately and enable direct mode */
 788         reg = readl(reg_base + CQSPI_REG_CONFIG);
 789         reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 790         reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
 791         reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
 792         writel(reg, reg_base + CQSPI_REG_CONFIG);
 793
 794         /* keep the XiP mode */
 795         writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
 796
 797         /* Enable mode bit at devrd */
 798         reg = readl(reg_base + CQSPI_REG_RD_INSTR);
 799         reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 800         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 801 }