drivers/spi/cadence_qspi_apb.c

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *  - Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  *  - Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *  - Neither the name of the Altera Corporation nor the
  13  *    names of its contributors may be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <asm/errno.h>
  31 #include "cadence_qspi.h"
  32
  33 #define CQSPI_REG_POLL_US                       (1) /* 1us */
  34 #define CQSPI_REG_RETRY                         (10000)
  35 #define CQSPI_POLL_IDLE_RETRY                   (3)
  36
  37 #define CQSPI_FIFO_WIDTH                        (4)
  38
  39 /* Controller sram size in word */
  40 #define CQSPI_REG_SRAM_SIZE_WORD                (128)
  41 #define CQSPI_REG_SRAM_PARTITION_RD             (CQSPI_REG_SRAM_SIZE_WORD/2)
  42 #define CQSPI_REG_SRAM_THRESHOLD_WORDS          (50)
  43
  44 /* Transfer mode */
  45 #define CQSPI_INST_TYPE_SINGLE                  (0)
  46 #define CQSPI_INST_TYPE_DUAL                    (1)
  47 #define CQSPI_INST_TYPE_QUAD                    (2)
  48
  49 #define CQSPI_STIG_DATA_LEN_MAX                 (8)
  50 #define CQSPI_INDIRECTTRIGGER_ADDR_MASK         (0xFFFFF)
  51
  52 #define CQSPI_DUMMY_CLKS_PER_BYTE               (8)
  53 #define CQSPI_DUMMY_BYTES_MAX                   (4)
  54
  55
  56 #define CQSPI_REG_SRAM_FILL_THRESHOLD   \
  57         ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
  58 /****************************************************************************
  59  * Controller's configuration and status register (offset from QSPI_BASE)
  60  ****************************************************************************/
  61 #define CQSPI_REG_CONFIG                        0x00
  62 #define CQSPI_REG_CONFIG_CLK_POL_LSB            1
  63 #define CQSPI_REG_CONFIG_CLK_PHA_LSB            2
  64 #define CQSPI_REG_CONFIG_ENABLE_MASK            (1 << 0)
  65 #define CQSPI_REG_CONFIG_DIRECT_MASK            (1 << 7)
  66 #define CQSPI_REG_CONFIG_DECODE_MASK            (1 << 9)
  67 #define CQSPI_REG_CONFIG_XIP_IMM_MASK           (1 << 18)
  68 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
  69 #define CQSPI_REG_CONFIG_BAUD_LSB               19
  70 #define CQSPI_REG_CONFIG_IDLE_LSB               31
  71 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
  72 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
  73
  74 #define CQSPI_REG_RD_INSTR                      0x04
  75 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
  76 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
  77 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
  78 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
  79 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
  80 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
  81 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
  82 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
  83 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
  84 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
  85
  86 #define CQSPI_REG_WR_INSTR                      0x08
  87 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
  88
  89 #define CQSPI_REG_DELAY                         0x0C
  90 #define CQSPI_REG_DELAY_TSLCH_LSB               0
  91 #define CQSPI_REG_DELAY_TCHSH_LSB               8
  92 #define CQSPI_REG_DELAY_TSD2D_LSB               16
  93 #define CQSPI_REG_DELAY_TSHSL_LSB               24
  94 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
  95 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
  96 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
  97 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
  98
  99 #define CQSPI_READLCAPTURE                      0x10
 100 #define CQSPI_READLCAPTURE_BYPASS_LSB           0
 101 #define CQSPI_READLCAPTURE_DELAY_LSB            1
 102 #define CQSPI_READLCAPTURE_DELAY_MASK           0xF
 103
 104 #define CQSPI_REG_SIZE                          0x14
 105 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 106 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 107 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 108 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 109 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 110 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 111
 112 #define CQSPI_REG_SRAMPARTITION                 0x18
 113 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 114
 115 #define CQSPI_REG_REMAP                         0x24
 116 #define CQSPI_REG_MODE_BIT                      0x28
 117
 118 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 119 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 120 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 121 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 122 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 123
 124 #define CQSPI_REG_IRQSTATUS                     0x40
 125 #define CQSPI_REG_IRQMASK                       0x44
 126
 127 #define CQSPI_REG_INDIRECTRD                    0x60
 128 #define CQSPI_REG_INDIRECTRD_START_MASK         (1 << 0)
 129 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        (1 << 1)
 130 #define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK    (1 << 2)
 131 #define CQSPI_REG_INDIRECTRD_DONE_MASK          (1 << 5)
 132
 133 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 134 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 135 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 136
 137 #define CQSPI_REG_CMDCTRL                       0x90
 138 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          (1 << 0)
 139 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       (1 << 1)
 140 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 141 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 142 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 143 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 144 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 145 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 146 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 147 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 148 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 149 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 150 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 151 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 152 #define CQSPI_REG_CMDCTRL_OPCODE_MASK           0xFF
 153
 154 #define CQSPI_REG_INDIRECTWR                    0x70
 155 #define CQSPI_REG_INDIRECTWR_START_MASK         (1 << 0)
 156 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        (1 << 1)
 157 #define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK    (1 << 2)
 158 #define CQSPI_REG_INDIRECTWR_DONE_MASK          (1 << 5)
 159
 160 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 161 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 162 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 163
 164 #define CQSPI_REG_CMDADDRESS                    0x94
 165 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 166 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 167 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 168 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 169
 170 #define CQSPI_REG_IS_IDLE(base)                                 \
 171         ((readl(base + CQSPI_REG_CONFIG) >>             \
 172                 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
 173
 174 #define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns)           \
 175         ((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
 176
 177 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)                       \
 178         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 179         CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
 180
 181 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)                       \
 182         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 183         CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
 184
 185 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
 186         unsigned int addr_width)
 187 {
 188         unsigned int addr;
 189
 190         addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
 191
 192         if (addr_width == 4)
 193                 addr = (addr << 8) | addr_buf[3];
 194
 195         return addr;
 196 }
 197
 198 static void cadence_qspi_apb_read_fifo_data(void *dest,
 199         const void *src_ahb_addr, unsigned int bytes)
 200 {
 201         unsigned int temp;
 202         int remaining = bytes;
 203         unsigned int *dest_ptr = (unsigned int *)dest;
 204         unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
 205
 206         while (remaining > 0) {
 207                 if (remaining >= CQSPI_FIFO_WIDTH) {
 208                         *dest_ptr = readl(src_ptr);
 209                         remaining -= CQSPI_FIFO_WIDTH;
 210                 } else {
 211                         /* dangling bytes */
 212                         temp = readl(src_ptr);
 213                         memcpy(dest_ptr, &temp, remaining);
 214                         break;
 215                 }
 216                 dest_ptr++;
 217         }
 218
 219         return;
 220 }
 221
 222 static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
 223         const void *src, unsigned int bytes)
 224 {
 225         unsigned int temp;
 226         int remaining = bytes;
 227         unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
 228         unsigned int *src_ptr = (unsigned int *)src;
 229
 230         while (remaining > 0) {
 231                 if (remaining >= CQSPI_FIFO_WIDTH) {
 232                         writel(*src_ptr, dest_ptr);
 233                         remaining -= sizeof(unsigned int);
 234                 } else {
 235                         /* dangling bytes */
 236                         memcpy(&temp, src_ptr, remaining);
 237                         writel(temp, dest_ptr);
 238                         break;
 239                 }
 240                 src_ptr++;
 241         }
 242
 243         return;
 244 }
 245
 246 /* Read from SRAM FIFO with polling SRAM fill level. */
 247 static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
 248                         const void *src_addr,  unsigned int num_bytes)
 249 {
 250         unsigned int remaining = num_bytes;
 251         unsigned int retry;
 252         unsigned int sram_level = 0;
 253         unsigned char *dest = (unsigned char *)dest_addr;
 254
 255         while (remaining > 0) {
 256                 retry = CQSPI_REG_RETRY;
 257                 while (retry--) {
 258                         sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base);
 259                         if (sram_level)
 260                                 break;
 261                         udelay(1);
 262                 }
 263
 264                 if (!retry) {
 265                         printf("QSPI: No receive data after polling for %d times\n",
 266                                CQSPI_REG_RETRY);
 267                         return -1;
 268                 }
 269
 270                 sram_level *= CQSPI_FIFO_WIDTH;
 271                 sram_level = sram_level > remaining ? remaining : sram_level;
 272
 273                 /* Read data from FIFO. */
 274                 cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level);
 275                 dest += sram_level;
 276                 remaining -= sram_level;
 277                 udelay(1);
 278         }
 279         return 0;
 280 }
 281
 282 /* Write to SRAM FIFO with polling SRAM fill level. */
 283 static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
 284                                 const void *src_addr, unsigned int num_bytes)
 285 {
 286         const void *reg_base = plat->regbase;
 287         void *dest_addr = plat->ahbbase;
 288         unsigned int retry = CQSPI_REG_RETRY;
 289         unsigned int sram_level;
 290         unsigned int wr_bytes;
 291         unsigned char *src = (unsigned char *)src_addr;
 292         int remaining = num_bytes;
 293         unsigned int page_size = plat->page_size;
 294         unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS;
 295
 296         while (remaining > 0) {
 297                 retry = CQSPI_REG_RETRY;
 298                 while (retry--) {
 299                         sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base);
 300                         if (sram_level <= sram_threshold_words)
 301                                 break;
 302                 }
 303                 if (!retry) {
 304                         printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)",
 305                                sram_level, sram_threshold_words);
 306                         return -1;
 307                 }
 308                 /* Write a page or remaining bytes. */
 309                 wr_bytes = (remaining > page_size) ?
 310                                         page_size : remaining;
 311
 312                 cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes);
 313                 src += wr_bytes;
 314                 remaining -= wr_bytes;
 315         }
 316
 317         return 0;
 318 }
 319
 320 void cadence_qspi_apb_controller_enable(void *reg_base)
 321 {
 322         unsigned int reg;
 323         reg = readl(reg_base + CQSPI_REG_CONFIG);
 324         reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 325         writel(reg, reg_base + CQSPI_REG_CONFIG);
 326         return;
 327 }
 328
 329 void cadence_qspi_apb_controller_disable(void *reg_base)
 330 {
 331         unsigned int reg;
 332         reg = readl(reg_base + CQSPI_REG_CONFIG);
 333         reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 334         writel(reg, reg_base + CQSPI_REG_CONFIG);
 335         return;
 336 }
 337
 338 /* Return 1 if idle, otherwise return 0 (busy). */
 339 static unsigned int cadence_qspi_wait_idle(void *reg_base)
 340 {
 341         unsigned int start, count = 0;
 342         /* timeout in unit of ms */
 343         unsigned int timeout = 5000;
 344
 345         start = get_timer(0);
 346         for ( ; get_timer(start) < timeout ; ) {
 347                 if (CQSPI_REG_IS_IDLE(reg_base))
 348                         count++;
 349                 else
 350                         count = 0;
 351                 /*
 352                  * Ensure the QSPI controller is in true idle state after
 353                  * reading back the same idle status consecutively
 354                  */
 355                 if (count >= CQSPI_POLL_IDLE_RETRY)
 356                         return 1;
 357         }
 358
 359         /* Timeout, still in busy mode. */
 360         printf("QSPI: QSPI is still busy after poll for %d times.\n",
 361                CQSPI_REG_RETRY);
 362         return 0;
 363 }
 364
 365 void cadence_qspi_apb_readdata_capture(void *reg_base,
 366                                 unsigned int bypass, unsigned int delay)
 367 {
 368         unsigned int reg;
 369         cadence_qspi_apb_controller_disable(reg_base);
 370
 371         reg = readl(reg_base + CQSPI_READLCAPTURE);
 372
 373         if (bypass)
 374                 reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
 375         else
 376                 reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
 377
 378         reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
 379                 << CQSPI_READLCAPTURE_DELAY_LSB);
 380
 381         reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
 382                 << CQSPI_READLCAPTURE_DELAY_LSB);
 383
 384         writel(reg, reg_base + CQSPI_READLCAPTURE);
 385
 386         cadence_qspi_apb_controller_enable(reg_base);
 387         return;
 388 }
 389
 390 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 391         unsigned int ref_clk_hz, unsigned int sclk_hz)
 392 {
 393         unsigned int reg;
 394         unsigned int div;
 395
 396         cadence_qspi_apb_controller_disable(reg_base);
 397         reg = readl(reg_base + CQSPI_REG_CONFIG);
 398         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 399
 400         div = ref_clk_hz / sclk_hz;
 401
 402         if (div > 32)
 403                 div = 32;
 404
 405         /* Check if even number. */
 406         if ((div & 1)) {
 407                 div = (div / 2);
 408         } else {
 409                 if (ref_clk_hz % sclk_hz)
 410                         /* ensure generated SCLK doesn't exceed user
 411                         specified sclk_hz */
 412                         div = (div / 2);
 413                 else
 414                         div = (div / 2) - 1;
 415         }
 416
 417         debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
 418               ref_clk_hz, sclk_hz, div);
 419
 420         div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 421         reg |= div;
 422         writel(reg, reg_base + CQSPI_REG_CONFIG);
 423
 424         cadence_qspi_apb_controller_enable(reg_base);
 425         return;
 426 }
 427
 428 void cadence_qspi_apb_set_clk_mode(void *reg_base,
 429         unsigned int clk_pol, unsigned int clk_pha)
 430 {
 431         unsigned int reg;
 432
 433         cadence_qspi_apb_controller_disable(reg_base);
 434         reg = readl(reg_base + CQSPI_REG_CONFIG);
 435         reg &= ~(1 <<
 436                 (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
 437
 438         reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
 439         reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
 440
 441         writel(reg, reg_base + CQSPI_REG_CONFIG);
 442
 443         cadence_qspi_apb_controller_enable(reg_base);
 444         return;
 445 }
 446
 447 void cadence_qspi_apb_chipselect(void *reg_base,
 448         unsigned int chip_select, unsigned int decoder_enable)
 449 {
 450         unsigned int reg;
 451
 452         cadence_qspi_apb_controller_disable(reg_base);
 453
 454         debug("%s : chipselect %d decode %d\n", __func__, chip_select,
 455               decoder_enable);
 456
 457         reg = readl(reg_base + CQSPI_REG_CONFIG);
 458         /* docoder */
 459         if (decoder_enable) {
 460                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 461         } else {
 462                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 463                 /* Convert CS if without decoder.
 464                  * CS0 to 4b'1110
 465                  * CS1 to 4b'1101
 466                  * CS2 to 4b'1011
 467                  * CS3 to 4b'0111
 468                  */
 469                 chip_select = 0xF & ~(1 << chip_select);
 470         }
 471
 472         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 473                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 474         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 475                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 476         writel(reg, reg_base + CQSPI_REG_CONFIG);
 477
 478         cadence_qspi_apb_controller_enable(reg_base);
 479         return;
 480 }
 481
 482 void cadence_qspi_apb_delay(void *reg_base,
 483         unsigned int ref_clk, unsigned int sclk_hz,
 484         unsigned int tshsl_ns, unsigned int tsd2d_ns,
 485         unsigned int tchsh_ns, unsigned int tslch_ns)
 486 {
 487         unsigned int ref_clk_ns;
 488         unsigned int sclk_ns;
 489         unsigned int tshsl, tchsh, tslch, tsd2d;
 490         unsigned int reg;
 491
 492         cadence_qspi_apb_controller_disable(reg_base);
 493
 494         /* Convert to ns. */
 495         ref_clk_ns = (1000000000) / ref_clk;
 496
 497         /* Convert to ns. */
 498         sclk_ns = (1000000000) / sclk_hz;
 499
 500         /* Plus 1 to round up 1 clock cycle. */
 501         tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
 502         tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
 503         tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
 504         tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
 505
 506         reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 507                         << CQSPI_REG_DELAY_TSHSL_LSB);
 508         reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 509                         << CQSPI_REG_DELAY_TCHSH_LSB);
 510         reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 511                         << CQSPI_REG_DELAY_TSLCH_LSB);
 512         reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 513                         << CQSPI_REG_DELAY_TSD2D_LSB);
 514         writel(reg, reg_base + CQSPI_REG_DELAY);
 515
 516         cadence_qspi_apb_controller_enable(reg_base);
 517         return;
 518 }
 519
 520 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 521 {
 522         unsigned reg;
 523
 524         cadence_qspi_apb_controller_disable(plat->regbase);
 525
 526         /* Configure the device size and address bytes */
 527         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 528         /* Clear the previous value */
 529         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 530         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 531         reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 532         reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
 533         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 534
 535         /* Configure the remap address register, no remap */
 536         writel(0, plat->regbase + CQSPI_REG_REMAP);
 537
 538         /* Indirect mode configurations */
 539         writel(CQSPI_REG_SRAM_PARTITION_RD,
 540                plat->regbase + CQSPI_REG_SRAMPARTITION);
 541
 542         /* Disable all interrupts */
 543         writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 544
 545         cadence_qspi_apb_controller_enable(plat->regbase);
 546         return;
 547 }
 548
 549 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
 550         unsigned int reg)
 551 {
 552         unsigned int retry = CQSPI_REG_RETRY;
 553
 554         /* Write the CMDCTRL without start execution. */
 555         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 556         /* Start execute */
 557         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 558         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 559
 560         while (retry--) {
 561                 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
 562                 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
 563                         break;
 564                 udelay(1);
 565         }
 566
 567         if (!retry) {
 568                 printf("QSPI: flash command execution timeout\n");
 569                 return -EIO;
 570         }
 571
 572         /* Polling QSPI idle status. */
 573         if (!cadence_qspi_wait_idle(reg_base))
 574                 return -EIO;
 575
 576         return 0;
 577 }
 578
 579 /* For command RDID, RDSR. */
 580 int cadence_qspi_apb_command_read(void *reg_base,
 581         unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
 582         u8 *rxbuf)
 583 {
 584         unsigned int reg;
 585         unsigned int read_len;
 586         int status;
 587
 588         if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
 589                 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
 590                        cmdlen, rxlen);
 591                 return -EINVAL;
 592         }
 593
 594         reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 595
 596         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 597
 598         /* 0 means 1 byte. */
 599         reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 600                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 601         status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 602         if (status != 0)
 603                 return status;
 604
 605         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 606
 607         /* Put the read value into rx_buf */
 608         read_len = (rxlen > 4) ? 4 : rxlen;
 609         memcpy(rxbuf, &reg, read_len);
 610         rxbuf += read_len;
 611
 612         if (rxlen > 4) {
 613                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 614
 615                 read_len = rxlen - read_len;
 616                 memcpy(rxbuf, &reg, read_len);
 617         }
 618         return 0;
 619 }
 620
 621 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
 622 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
 623         const u8 *cmdbuf, unsigned int txlen,  const u8 *txbuf)
 624 {
 625         unsigned int reg = 0;
 626         unsigned int addr_value;
 627         unsigned int wr_data;
 628         unsigned int wr_len;
 629
 630         if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
 631                 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
 632                        cmdlen, txlen);
 633                 return -EINVAL;
 634         }
 635
 636         reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 637
 638         if (cmdlen == 4 || cmdlen == 5) {
 639                 /* Command with address */
 640                 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 641                 /* Number of bytes to write. */
 642                 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 643                         << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 644                 /* Get address */
 645                 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
 646                         cmdlen >= 5 ? 4 : 3);
 647
 648                 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
 649         }
 650
 651         if (txlen) {
 652                 /* writing data = yes */
 653                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 654                 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 655                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 656
 657                 wr_len = txlen > 4 ? 4 : txlen;
 658                 memcpy(&wr_data, txbuf, wr_len);
 659                 writel(wr_data, reg_base +
 660                         CQSPI_REG_CMDWRITEDATALOWER);
 661
 662                 if (txlen > 4) {
 663                         txbuf += wr_len;
 664                         wr_len = txlen - wr_len;
 665                         memcpy(&wr_data, txbuf, wr_len);
 666                         writel(wr_data, reg_base +
 667                                 CQSPI_REG_CMDWRITEDATAUPPER);
 668                 }
 669         }
 670
 671         /* Execute the command */
 672         return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 673 }
 674
 675 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
 676 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 677         unsigned int cmdlen, const u8 *cmdbuf)
 678 {
 679         unsigned int reg;
 680         unsigned int rd_reg;
 681         unsigned int addr_value;
 682         unsigned int dummy_clk;
 683         unsigned int dummy_bytes;
 684         unsigned int addr_bytes;
 685
 686         /*
 687          * Identify addr_byte. All NOR flash device drivers are using fast read
 688          * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
 689          * With that, the length is in value of 5 or 6. Only FRAM chip from
 690          * ramtron using normal read (which won't need dummy byte).
 691          * Unlikely NOR flash using normal read due to performance issue.
 692          */
 693         if (cmdlen >= 5)
 694                 /* to cater fast read where cmd + addr + dummy */
 695                 addr_bytes = cmdlen - 2;
 696         else
 697                 /* for normal read (only ramtron as of now) */
 698                 addr_bytes = cmdlen - 1;
 699
 700         /* Setup the indirect trigger address */
 701         writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
 702                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 703
 704         /* Configure the opcode */
 705         rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 706
 707 #if (CONFIG_SPI_FLASH_QUAD == 1)
 708         /* Instruction and address at DQ0, data at DQ0-3. */
 709         rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 710 #endif
 711
 712         /* Get address */
 713         addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 714         writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 715
 716         /* The remaining lenght is dummy bytes. */
 717         dummy_bytes = cmdlen - addr_bytes - 1;
 718         if (dummy_bytes) {
 719                 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
 720                         dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
 721
 722                 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 723 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
 724                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
 725 #else
 726                 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
 727 #endif
 728
 729                 /* Convert to clock cycles. */
 730                 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
 731                 /* Need to minus the mode byte (8 clocks). */
 732                 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
 733
 734                 if (dummy_clk)
 735                         rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 736                                 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 737         }
 738
 739         writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
 740
 741         /* set device size */
 742         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 743         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 744         reg |= (addr_bytes - 1);
 745         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 746         return 0;
 747 }
 748
 749 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 750         unsigned int rxlen, u8 *rxbuf)
 751 {
 752         unsigned int reg;
 753
 754         writel(rxlen, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
 755
 756         /* Start the indirect read transfer */
 757         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 758                plat->regbase + CQSPI_REG_INDIRECTRD);
 759
 760         if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
 761                                      (const void *)plat->ahbbase, rxlen))
 762                 goto failrd;
 763
 764         /* Check flash indirect controller */
 765         reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
 766         if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) {
 767                 reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
 768                 printf("QSPI: indirect completion status error with reg 0x%08x\n",
 769                        reg);
 770                 goto failrd;
 771         }
 772
 773         /* Clear indirect completion status */
 774         writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
 775                plat->regbase + CQSPI_REG_INDIRECTRD);
 776         return 0;
 777
 778 failrd:
 779         /* Cancel the indirect read */
 780         writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
 781                plat->regbase + CQSPI_REG_INDIRECTRD);
 782         return -1;
 783 }
 784
 785 /* Opcode + Address (3/4 bytes) */
 786 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 787         unsigned int cmdlen, const u8 *cmdbuf)
 788 {
 789         unsigned int reg;
 790         unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
 791
 792         if (cmdlen < 4 || cmdbuf == NULL) {
 793                 printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
 794                        cmdlen, (unsigned int)cmdbuf);
 795                 return -EINVAL;
 796         }
 797         /* Setup the indirect trigger address */
 798         writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
 799                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 800
 801         /* Configure the opcode */
 802         reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 803         writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
 804
 805         /* Setup write address. */
 806         reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 807         writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 808
 809         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 810         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 811         reg |= (addr_bytes - 1);
 812         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 813         return 0;
 814 }
 815
 816 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 817         unsigned int txlen, const u8 *txbuf)
 818 {
 819         unsigned int reg = 0;
 820         unsigned int retry;
 821
 822         /* Configure the indirect read transfer bytes */
 823         writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
 824
 825         /* Start the indirect write transfer */
 826         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 827                plat->regbase + CQSPI_REG_INDIRECTWR);
 828
 829         if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen))
 830                 goto failwr;
 831
 832         /* Wait until last write is completed (FIFO empty) */
 833         retry = CQSPI_REG_RETRY;
 834         while (retry--) {
 835                 reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase);
 836                 if (reg == 0)
 837                         break;
 838
 839                 udelay(1);
 840         }
 841
 842         if (reg != 0) {
 843                 printf("QSPI: timeout for indirect write\n");
 844                 goto failwr;
 845         }
 846
 847         /* Check flash indirect controller status */
 848         retry = CQSPI_REG_RETRY;
 849         while (retry--) {
 850                 reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR);
 851                 if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
 852                         break;
 853                 udelay(1);
 854         }
 855
 856         if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) {
 857                 printf("QSPI: indirect completion status error with reg 0x%08x\n",
 858                        reg);
 859                 goto failwr;
 860         }
 861
 862         /* Clear indirect completion status */
 863         writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
 864                plat->regbase + CQSPI_REG_INDIRECTWR);
 865         return 0;
 866
 867 failwr:
 868         /* Cancel the indirect write */
 869         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 870                plat->regbase + CQSPI_REG_INDIRECTWR);
 871         return -1;
 872 }
 873
 874 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
 875 {
 876         unsigned int reg;
 877
 878         /* enter XiP mode immediately and enable direct mode */
 879         reg = readl(reg_base + CQSPI_REG_CONFIG);
 880         reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 881         reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
 882         reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
 883         writel(reg, reg_base + CQSPI_REG_CONFIG);
 884
 885         /* keep the XiP mode */
 886         writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
 887
 888         /* Enable mode bit at devrd */
 889         reg = readl(reg_base + CQSPI_REG_RD_INSTR);
 890         reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 891         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 892 }