drivers/spi/cadence_qspi_apb.c

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *  - Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  *  - Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *  - Neither the name of the Altera Corporation nor the
  13  *    names of its contributors may be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <linux/errno.h>
  31 #include <wait_bit.h>
  32 #include <spi.h>
  33 #include <spi-mem.h>
  34 #include <malloc.h>
  35 #include "cadence_qspi.h"
  36
  37 #define CQSPI_REG_POLL_US                       1 /* 1us */
  38 #define CQSPI_REG_RETRY                         10000
  39 #define CQSPI_POLL_IDLE_RETRY                   3
  40
  41 /* Transfer mode */
  42 #define CQSPI_INST_TYPE_SINGLE                  0
  43 #define CQSPI_INST_TYPE_DUAL                    1
  44 #define CQSPI_INST_TYPE_QUAD                    2
  45
  46 #define CQSPI_STIG_DATA_LEN_MAX                 8
  47
  48 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
  49 #define CQSPI_DUMMY_BYTES_MAX                   4
  50
  51 /****************************************************************************
  52  * Controller's configuration and status register (offset from QSPI_BASE)
  53  ****************************************************************************/
  54 #define CQSPI_REG_CONFIG                        0x00
  55 #define CQSPI_REG_CONFIG_ENABLE                 BIT(0)
  56 #define CQSPI_REG_CONFIG_CLK_POL                BIT(1)
  57 #define CQSPI_REG_CONFIG_CLK_PHA                BIT(2)
  58 #define CQSPI_REG_CONFIG_DIRECT                 BIT(7)
  59 #define CQSPI_REG_CONFIG_DECODE                 BIT(9)
  60 #define CQSPI_REG_CONFIG_XIP_IMM                BIT(18)
  61 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
  62 #define CQSPI_REG_CONFIG_BAUD_LSB               19
  63 #define CQSPI_REG_CONFIG_IDLE_LSB               31
  64 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
  65 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
  66
  67 #define CQSPI_REG_RD_INSTR                      0x04
  68 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
  69 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
  70 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
  71 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
  72 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
  73 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
  74 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
  75 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
  76 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
  77 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
  78
  79 #define CQSPI_REG_WR_INSTR                      0x08
  80 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
  81 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
  82
  83 #define CQSPI_REG_DELAY                         0x0C
  84 #define CQSPI_REG_DELAY_TSLCH_LSB               0
  85 #define CQSPI_REG_DELAY_TCHSH_LSB               8
  86 #define CQSPI_REG_DELAY_TSD2D_LSB               16
  87 #define CQSPI_REG_DELAY_TSHSL_LSB               24
  88 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
  89 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
  90 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
  91 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
  92
  93 #define CQSPI_REG_RD_DATA_CAPTURE               0x10
  94 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS        BIT(0)
  95 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB     1
  96 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK    0xF
  97
  98 #define CQSPI_REG_SIZE                          0x14
  99 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 100 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 101 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 102 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 103 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 104 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 105
 106 #define CQSPI_REG_SRAMPARTITION                 0x18
 107 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 108
 109 #define CQSPI_REG_REMAP                         0x24
 110 #define CQSPI_REG_MODE_BIT                      0x28
 111
 112 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 113 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 114 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 115 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 116 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 117
 118 #define CQSPI_REG_IRQSTATUS                     0x40
 119 #define CQSPI_REG_IRQMASK                       0x44
 120
 121 #define CQSPI_REG_INDIRECTRD                    0x60
 122 #define CQSPI_REG_INDIRECTRD_START              BIT(0)
 123 #define CQSPI_REG_INDIRECTRD_CANCEL             BIT(1)
 124 #define CQSPI_REG_INDIRECTRD_INPROGRESS         BIT(2)
 125 #define CQSPI_REG_INDIRECTRD_DONE               BIT(5)
 126
 127 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 128 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 129 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 130
 131 #define CQSPI_REG_CMDCTRL                       0x90
 132 #define CQSPI_REG_CMDCTRL_EXECUTE               BIT(0)
 133 #define CQSPI_REG_CMDCTRL_INPROGRESS            BIT(1)
 134 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 135 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 136 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 137 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 138 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 139 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 140 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 141 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 142 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 143 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 144 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 145 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 146 #define CQSPI_REG_CMDCTRL_OPCODE_MASK           0xFF
 147
 148 #define CQSPI_REG_INDIRECTWR                    0x70
 149 #define CQSPI_REG_INDIRECTWR_START              BIT(0)
 150 #define CQSPI_REG_INDIRECTWR_CANCEL             BIT(1)
 151 #define CQSPI_REG_INDIRECTWR_INPROGRESS         BIT(2)
 152 #define CQSPI_REG_INDIRECTWR_DONE               BIT(5)
 153
 154 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 155 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 156 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 157
 158 #define CQSPI_REG_CMDADDRESS                    0x94
 159 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 160 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 161 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 162 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 163
 164 #define CQSPI_REG_IS_IDLE(base)                                 \
 165         ((readl(base + CQSPI_REG_CONFIG) >>             \
 166                 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
 167
 168 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)                       \
 169         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 170         CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
 171
 172 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)                       \
 173         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 174         CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
 175
 176 void cadence_qspi_apb_controller_enable(void *reg_base)
 177 {
 178         unsigned int reg;
 179         reg = readl(reg_base + CQSPI_REG_CONFIG);
 180         reg |= CQSPI_REG_CONFIG_ENABLE;
 181         writel(reg, reg_base + CQSPI_REG_CONFIG);
 182 }
 183
 184 void cadence_qspi_apb_controller_disable(void *reg_base)
 185 {
 186         unsigned int reg;
 187         reg = readl(reg_base + CQSPI_REG_CONFIG);
 188         reg &= ~CQSPI_REG_CONFIG_ENABLE;
 189         writel(reg, reg_base + CQSPI_REG_CONFIG);
 190 }
 191
 192 /* Return 1 if idle, otherwise return 0 (busy). */
 193 static unsigned int cadence_qspi_wait_idle(void *reg_base)
 194 {
 195         unsigned int start, count = 0;
 196         /* timeout in unit of ms */
 197         unsigned int timeout = 5000;
 198
 199         start = get_timer(0);
 200         for ( ; get_timer(start) < timeout ; ) {
 201                 if (CQSPI_REG_IS_IDLE(reg_base))
 202                         count++;
 203                 else
 204                         count = 0;
 205                 /*
 206                  * Ensure the QSPI controller is in true idle state after
 207                  * reading back the same idle status consecutively
 208                  */
 209                 if (count >= CQSPI_POLL_IDLE_RETRY)
 210                         return 1;
 211         }
 212
 213         /* Timeout, still in busy mode. */
 214         printf("QSPI: QSPI is still busy after poll for %d times.\n",
 215                CQSPI_REG_RETRY);
 216         return 0;
 217 }
 218
 219 void cadence_qspi_apb_readdata_capture(void *reg_base,
 220                                 unsigned int bypass, unsigned int delay)
 221 {
 222         unsigned int reg;
 223         cadence_qspi_apb_controller_disable(reg_base);
 224
 225         reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 226
 227         if (bypass)
 228                 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 229         else
 230                 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 231
 232         reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
 233                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
 234
 235         reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
 236                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
 237
 238         writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 239
 240         cadence_qspi_apb_controller_enable(reg_base);
 241 }
 242
 243 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 244         unsigned int ref_clk_hz, unsigned int sclk_hz)
 245 {
 246         unsigned int reg;
 247         unsigned int div;
 248
 249         cadence_qspi_apb_controller_disable(reg_base);
 250         reg = readl(reg_base + CQSPI_REG_CONFIG);
 251         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 252
 253         /*
 254          * The baud_div field in the config reg is 4 bits, and the ref clock is
 255          * divided by 2 * (baud_div + 1). Round up the divider to ensure the
 256          * SPI clock rate is less than or equal to the requested clock rate.
 257          */
 258         div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
 259
 260         /* ensure the baud rate doesn't exceed the max value */
 261         if (div > CQSPI_REG_CONFIG_BAUD_MASK)
 262                 div = CQSPI_REG_CONFIG_BAUD_MASK;
 263
 264         debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
 265               ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
 266
 267         reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
 268         writel(reg, reg_base + CQSPI_REG_CONFIG);
 269
 270         cadence_qspi_apb_controller_enable(reg_base);
 271 }
 272
 273 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
 274 {
 275         unsigned int reg;
 276
 277         cadence_qspi_apb_controller_disable(reg_base);
 278         reg = readl(reg_base + CQSPI_REG_CONFIG);
 279         reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
 280
 281         if (mode & SPI_CPOL)
 282                 reg |= CQSPI_REG_CONFIG_CLK_POL;
 283         if (mode & SPI_CPHA)
 284                 reg |= CQSPI_REG_CONFIG_CLK_PHA;
 285
 286         writel(reg, reg_base + CQSPI_REG_CONFIG);
 287
 288         cadence_qspi_apb_controller_enable(reg_base);
 289 }
 290
 291 void cadence_qspi_apb_chipselect(void *reg_base,
 292         unsigned int chip_select, unsigned int decoder_enable)
 293 {
 294         unsigned int reg;
 295
 296         cadence_qspi_apb_controller_disable(reg_base);
 297
 298         debug("%s : chipselect %d decode %d\n", __func__, chip_select,
 299               decoder_enable);
 300
 301         reg = readl(reg_base + CQSPI_REG_CONFIG);
 302         /* docoder */
 303         if (decoder_enable) {
 304                 reg |= CQSPI_REG_CONFIG_DECODE;
 305         } else {
 306                 reg &= ~CQSPI_REG_CONFIG_DECODE;
 307                 /* Convert CS if without decoder.
 308                  * CS0 to 4b'1110
 309                  * CS1 to 4b'1101
 310                  * CS2 to 4b'1011
 311                  * CS3 to 4b'0111
 312                  */
 313                 chip_select = 0xF & ~(1 << chip_select);
 314         }
 315
 316         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 317                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 318         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 319                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 320         writel(reg, reg_base + CQSPI_REG_CONFIG);
 321
 322         cadence_qspi_apb_controller_enable(reg_base);
 323 }
 324
 325 void cadence_qspi_apb_delay(void *reg_base,
 326         unsigned int ref_clk, unsigned int sclk_hz,
 327         unsigned int tshsl_ns, unsigned int tsd2d_ns,
 328         unsigned int tchsh_ns, unsigned int tslch_ns)
 329 {
 330         unsigned int ref_clk_ns;
 331         unsigned int sclk_ns;
 332         unsigned int tshsl, tchsh, tslch, tsd2d;
 333         unsigned int reg;
 334
 335         cadence_qspi_apb_controller_disable(reg_base);
 336
 337         /* Convert to ns. */
 338         ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
 339
 340         /* Convert to ns. */
 341         sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
 342
 343         /* The controller adds additional delay to that programmed in the reg */
 344         if (tshsl_ns >= sclk_ns + ref_clk_ns)
 345                 tshsl_ns -= sclk_ns + ref_clk_ns;
 346         if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
 347                 tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
 348         tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
 349         tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
 350         tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
 351         tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
 352
 353         reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 354                         << CQSPI_REG_DELAY_TSHSL_LSB);
 355         reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 356                         << CQSPI_REG_DELAY_TCHSH_LSB);
 357         reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 358                         << CQSPI_REG_DELAY_TSLCH_LSB);
 359         reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 360                         << CQSPI_REG_DELAY_TSD2D_LSB);
 361         writel(reg, reg_base + CQSPI_REG_DELAY);
 362
 363         cadence_qspi_apb_controller_enable(reg_base);
 364 }
 365
 366 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 367 {
 368         unsigned reg;
 369
 370         cadence_qspi_apb_controller_disable(plat->regbase);
 371
 372         /* Configure the device size and address bytes */
 373         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 374         /* Clear the previous value */
 375         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 376         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 377         reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 378         reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
 379         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 380
 381         /* Configure the remap address register, no remap */
 382         writel(0, plat->regbase + CQSPI_REG_REMAP);
 383
 384         /* Indirect mode configurations */
 385         writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);
 386
 387         /* Disable all interrupts */
 388         writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 389
 390         cadence_qspi_apb_controller_enable(plat->regbase);
 391 }
 392
 393 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
 394         unsigned int reg)
 395 {
 396         unsigned int retry = CQSPI_REG_RETRY;
 397
 398         /* Write the CMDCTRL without start execution. */
 399         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 400         /* Start execute */
 401         reg |= CQSPI_REG_CMDCTRL_EXECUTE;
 402         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 403
 404         while (retry--) {
 405                 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
 406                 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
 407                         break;
 408                 udelay(1);
 409         }
 410
 411         if (!retry) {
 412                 printf("QSPI: flash command execution timeout\n");
 413                 return -EIO;
 414         }
 415
 416         /* Polling QSPI idle status. */
 417         if (!cadence_qspi_wait_idle(reg_base))
 418                 return -EIO;
 419
 420         return 0;
 421 }
 422
 423 /* For command RDID, RDSR. */
 424 int cadence_qspi_apb_command_read(void *reg_base, const struct spi_mem_op *op)
 425 {
 426         unsigned int reg;
 427         unsigned int read_len;
 428         int status;
 429         unsigned int rxlen = op->data.nbytes;
 430         void *rxbuf = op->data.buf.in;
 431
 432         if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 433                 printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
 434                 return -EINVAL;
 435         }
 436
 437         reg = op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 438
 439         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 440
 441         /* 0 means 1 byte. */
 442         reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 443                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 444         status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 445         if (status != 0)
 446                 return status;
 447
 448         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 449
 450         /* Put the read value into rx_buf */
 451         read_len = (rxlen > 4) ? 4 : rxlen;
 452         memcpy(rxbuf, &reg, read_len);
 453         rxbuf += read_len;
 454
 455         if (rxlen > 4) {
 456                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 457
 458                 read_len = rxlen - read_len;
 459                 memcpy(rxbuf, &reg, read_len);
 460         }
 461         return 0;
 462 }
 463
 464 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
 465 int cadence_qspi_apb_command_write(void *reg_base, const struct spi_mem_op *op)
 466 {
 467         unsigned int reg = 0;
 468         unsigned int wr_data;
 469         unsigned int wr_len;
 470         unsigned int txlen = op->data.nbytes;
 471         const void *txbuf = op->data.buf.out;
 472         u32 addr;
 473
 474         /* Reorder address to SPI bus order if only transferring address */
 475         if (!txlen) {
 476                 addr = cpu_to_be32(op->addr.val);
 477                 if (op->addr.nbytes == 3)
 478                         addr >>= 8;
 479                 txbuf = &addr;
 480                 txlen = op->addr.nbytes;
 481         }
 482
 483         if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
 484                 printf("QSPI: Invalid input arguments txlen %u\n", txlen);
 485                 return -EINVAL;
 486         }
 487
 488         reg |= op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 489
 490         if (txlen) {
 491                 /* writing data = yes */
 492                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 493                 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 494                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 495
 496                 wr_len = txlen > 4 ? 4 : txlen;
 497                 memcpy(&wr_data, txbuf, wr_len);
 498                 writel(wr_data, reg_base +
 499                         CQSPI_REG_CMDWRITEDATALOWER);
 500
 501                 if (txlen > 4) {
 502                         txbuf += wr_len;
 503                         wr_len = txlen - wr_len;
 504                         memcpy(&wr_data, txbuf, wr_len);
 505                         writel(wr_data, reg_base +
 506                                 CQSPI_REG_CMDWRITEDATAUPPER);
 507                 }
 508         }
 509
 510         /* Execute the command */
 511         return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 512 }
 513
 514 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
 515 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 516         const struct spi_mem_op *op)
 517 {
 518         unsigned int reg;
 519         unsigned int rd_reg;
 520         unsigned int dummy_clk;
 521         unsigned int dummy_bytes = op->dummy.nbytes;
 522
 523         /* Setup the indirect trigger address */
 524         writel(plat->trigger_address,
 525                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 526
 527         /* Configure the opcode */
 528         rd_reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 529
 530         if (op->data.buswidth == 4)
 531                 /* Instruction and address at DQ0, data at DQ0-3. */
 532                 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 533
 534         writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 535
 536         if (dummy_bytes) {
 537                 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
 538                         dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
 539
 540                 /* Convert to clock cycles. */
 541                 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
 542
 543                 if (dummy_clk)
 544                         rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 545                                 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 546         }
 547
 548         writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
 549
 550         /* set device size */
 551         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 552         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 553         reg |= (op->addr.nbytes - 1);
 554         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 555         return 0;
 556 }
 557
 558 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
 559 {
 560         u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
 561         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 562         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 563 }
 564
 565 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
 566 {
 567         unsigned int timeout = 10000;
 568         u32 reg;
 569
 570         while (timeout--) {
 571                 reg = cadence_qspi_get_rd_sram_level(plat);
 572                 if (reg)
 573                         return reg;
 574                 udelay(1);
 575         }
 576
 577         return -ETIMEDOUT;
 578 }
 579
 580 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 581         unsigned int n_rx, u8 *rxbuf)
 582 {
 583         unsigned int remaining = n_rx;
 584         unsigned int bytes_to_read = 0;
 585         int ret;
 586
 587         writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
 588
 589         /* Start the indirect read transfer */
 590         writel(CQSPI_REG_INDIRECTRD_START,
 591                plat->regbase + CQSPI_REG_INDIRECTRD);
 592
 593         while (remaining > 0) {
 594                 ret = cadence_qspi_wait_for_data(plat);
 595                 if (ret < 0) {
 596                         printf("Indirect write timed out (%i)\n", ret);
 597                         goto failrd;
 598                 }
 599
 600                 bytes_to_read = ret;
 601
 602                 while (bytes_to_read != 0) {
 603                         bytes_to_read *= plat->fifo_width;
 604                         bytes_to_read = bytes_to_read > remaining ?
 605                                         remaining : bytes_to_read;
 606                         /*
 607                          * Handle non-4-byte aligned access to avoid
 608                          * data abort.
 609                          */
 610                         if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
 611                                 readsb(plat->ahbbase, rxbuf, bytes_to_read);
 612                         else
 613                                 readsl(plat->ahbbase, rxbuf,
 614                                        bytes_to_read >> 2);
 615                         rxbuf += bytes_to_read;
 616                         remaining -= bytes_to_read;
 617                         bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
 618                 }
 619         }
 620
 621         /* Check indirect done status */
 622         ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
 623                                 CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
 624         if (ret) {
 625                 printf("Indirect read completion error (%i)\n", ret);
 626                 goto failrd;
 627         }
 628
 629         /* Clear indirect completion status */
 630         writel(CQSPI_REG_INDIRECTRD_DONE,
 631                plat->regbase + CQSPI_REG_INDIRECTRD);
 632
 633         return 0;
 634
 635 failrd:
 636         /* Cancel the indirect read */
 637         writel(CQSPI_REG_INDIRECTRD_CANCEL,
 638                plat->regbase + CQSPI_REG_INDIRECTRD);
 639         return ret;
 640 }
 641
 642 /* Opcode + Address (3/4 bytes) */
 643 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 644         const struct spi_mem_op *op)
 645 {
 646         unsigned int reg;
 647
 648         /* Setup the indirect trigger address */
 649         writel(plat->trigger_address,
 650                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 651
 652         /* Configure the opcode */
 653         reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 654         writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
 655
 656         writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 657
 658         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 659         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 660         reg |= (op->addr.nbytes - 1);
 661         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 662         return 0;
 663 }
 664
 665 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 666         unsigned int n_tx, const u8 *txbuf)
 667 {
 668         unsigned int page_size = plat->page_size;
 669         unsigned int remaining = n_tx;
 670         const u8 *bb_txbuf = txbuf;
 671         void *bounce_buf = NULL;
 672         unsigned int write_bytes;
 673         int ret;
 674
 675         /*
 676          * Use bounce buffer for non 32 bit aligned txbuf to avoid data
 677          * aborts
 678          */
 679         if ((uintptr_t)txbuf % 4) {
 680                 bounce_buf = malloc(n_tx);
 681                 if (!bounce_buf)
 682                         return -ENOMEM;
 683                 memcpy(bounce_buf, txbuf, n_tx);
 684                 bb_txbuf = bounce_buf;
 685         }
 686
 687         /* Configure the indirect read transfer bytes */
 688         writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
 689
 690         /* Start the indirect write transfer */
 691         writel(CQSPI_REG_INDIRECTWR_START,
 692                plat->regbase + CQSPI_REG_INDIRECTWR);
 693
 694         while (remaining > 0) {
 695                 write_bytes = remaining > page_size ? page_size : remaining;
 696                 writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
 697                 if (write_bytes % 4)
 698                         writesb(plat->ahbbase,
 699                                 bb_txbuf + rounddown(write_bytes, 4),
 700                                 write_bytes % 4);
 701
 702                 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
 703                                         CQSPI_REG_SDRAMLEVEL_WR_MASK <<
 704                                         CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
 705                 if (ret) {
 706                         printf("Indirect write timed out (%i)\n", ret);
 707                         goto failwr;
 708                 }
 709
 710                 bb_txbuf += write_bytes;
 711                 remaining -= write_bytes;
 712         }
 713
 714         /* Check indirect done status */
 715         ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
 716                                 CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
 717         if (ret) {
 718                 printf("Indirect write completion error (%i)\n", ret);
 719                 goto failwr;
 720         }
 721
 722         /* Clear indirect completion status */
 723         writel(CQSPI_REG_INDIRECTWR_DONE,
 724                plat->regbase + CQSPI_REG_INDIRECTWR);
 725         if (bounce_buf)
 726                 free(bounce_buf);
 727         return 0;
 728
 729 failwr:
 730         /* Cancel the indirect write */
 731         writel(CQSPI_REG_INDIRECTWR_CANCEL,
 732                plat->regbase + CQSPI_REG_INDIRECTWR);
 733         if (bounce_buf)
 734                 free(bounce_buf);
 735         return ret;
 736 }
 737
 738 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
 739 {
 740         unsigned int reg;
 741
 742         /* enter XiP mode immediately and enable direct mode */
 743         reg = readl(reg_base + CQSPI_REG_CONFIG);
 744         reg |= CQSPI_REG_CONFIG_ENABLE;
 745         reg |= CQSPI_REG_CONFIG_DIRECT;
 746         reg |= CQSPI_REG_CONFIG_XIP_IMM;
 747         writel(reg, reg_base + CQSPI_REG_CONFIG);
 748
 749         /* keep the XiP mode */
 750         writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
 751
 752         /* Enable mode bit at devrd */
 753         reg = readl(reg_base + CQSPI_REG_RD_INSTR);
 754         reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 755         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 756 }