drivers/spi/cadence_qspi_apb.c

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *  - Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  *  - Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *  - Neither the name of the Altera Corporation nor the
  13  *    names of its contributors may be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <linux/errno.h>
  31 #include <wait_bit.h>
  32 #include <spi.h>
  33 #include <malloc.h>
  34 #include "cadence_qspi.h"
  35
  36 #define CQSPI_REG_POLL_US                       1 /* 1us */
  37 #define CQSPI_REG_RETRY                         10000
  38 #define CQSPI_POLL_IDLE_RETRY                   3
  39
  40 /* Transfer mode */
  41 #define CQSPI_INST_TYPE_SINGLE                  0
  42 #define CQSPI_INST_TYPE_DUAL                    1
  43 #define CQSPI_INST_TYPE_QUAD                    2
  44
  45 #define CQSPI_STIG_DATA_LEN_MAX                 8
  46
  47 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
  48 #define CQSPI_DUMMY_BYTES_MAX                   4
  49
  50 /****************************************************************************
  51  * Controller's configuration and status register (offset from QSPI_BASE)
  52  ****************************************************************************/
  53 #define CQSPI_REG_CONFIG                        0x00
  54 #define CQSPI_REG_CONFIG_ENABLE                 BIT(0)
  55 #define CQSPI_REG_CONFIG_CLK_POL                BIT(1)
  56 #define CQSPI_REG_CONFIG_CLK_PHA                BIT(2)
  57 #define CQSPI_REG_CONFIG_DIRECT                 BIT(7)
  58 #define CQSPI_REG_CONFIG_DECODE                 BIT(9)
  59 #define CQSPI_REG_CONFIG_XIP_IMM                BIT(18)
  60 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
  61 #define CQSPI_REG_CONFIG_BAUD_LSB               19
  62 #define CQSPI_REG_CONFIG_IDLE_LSB               31
  63 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
  64 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
  65
  66 #define CQSPI_REG_RD_INSTR                      0x04
  67 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
  68 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
  69 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
  70 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
  71 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
  72 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
  73 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
  74 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
  75 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
  76 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
  77
  78 #define CQSPI_REG_WR_INSTR                      0x08
  79 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
  80 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
  81
  82 #define CQSPI_REG_DELAY                         0x0C
  83 #define CQSPI_REG_DELAY_TSLCH_LSB               0
  84 #define CQSPI_REG_DELAY_TCHSH_LSB               8
  85 #define CQSPI_REG_DELAY_TSD2D_LSB               16
  86 #define CQSPI_REG_DELAY_TSHSL_LSB               24
  87 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
  88 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
  89 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
  90 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
  91
  92 #define CQSPI_REG_RD_DATA_CAPTURE               0x10
  93 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS        BIT(0)
  94 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB     1
  95 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK    0xF
  96
  97 #define CQSPI_REG_SIZE                          0x14
  98 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
  99 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 100 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 101 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 102 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 103 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 104
 105 #define CQSPI_REG_SRAMPARTITION                 0x18
 106 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 107
 108 #define CQSPI_REG_REMAP                         0x24
 109 #define CQSPI_REG_MODE_BIT                      0x28
 110
 111 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 112 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 113 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 114 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 115 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 116
 117 #define CQSPI_REG_IRQSTATUS                     0x40
 118 #define CQSPI_REG_IRQMASK                       0x44
 119
 120 #define CQSPI_REG_INDIRECTRD                    0x60
 121 #define CQSPI_REG_INDIRECTRD_START              BIT(0)
 122 #define CQSPI_REG_INDIRECTRD_CANCEL             BIT(1)
 123 #define CQSPI_REG_INDIRECTRD_INPROGRESS         BIT(2)
 124 #define CQSPI_REG_INDIRECTRD_DONE               BIT(5)
 125
 126 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 127 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 128 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 129
 130 #define CQSPI_REG_CMDCTRL                       0x90
 131 #define CQSPI_REG_CMDCTRL_EXECUTE               BIT(0)
 132 #define CQSPI_REG_CMDCTRL_INPROGRESS            BIT(1)
 133 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 134 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 135 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 136 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 137 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 138 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 139 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 140 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 141 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 142 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 143 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 144 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 145 #define CQSPI_REG_CMDCTRL_OPCODE_MASK           0xFF
 146
 147 #define CQSPI_REG_INDIRECTWR                    0x70
 148 #define CQSPI_REG_INDIRECTWR_START              BIT(0)
 149 #define CQSPI_REG_INDIRECTWR_CANCEL             BIT(1)
 150 #define CQSPI_REG_INDIRECTWR_INPROGRESS         BIT(2)
 151 #define CQSPI_REG_INDIRECTWR_DONE               BIT(5)
 152
 153 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 154 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 155 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 156
 157 #define CQSPI_REG_CMDADDRESS                    0x94
 158 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 159 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 160 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 161 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 162
 163 #define CQSPI_REG_IS_IDLE(base)                                 \
 164         ((readl(base + CQSPI_REG_CONFIG) >>             \
 165                 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
 166
 167 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)                       \
 168         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 169         CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
 170
 171 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)                       \
 172         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 173         CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
 174
 175 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
 176         unsigned int addr_width)
 177 {
 178         unsigned int addr;
 179
 180         addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
 181
 182         if (addr_width == 4)
 183                 addr = (addr << 8) | addr_buf[3];
 184
 185         return addr;
 186 }
 187
 188 void cadence_qspi_apb_controller_enable(void *reg_base)
 189 {
 190         unsigned int reg;
 191         reg = readl(reg_base + CQSPI_REG_CONFIG);
 192         reg |= CQSPI_REG_CONFIG_ENABLE;
 193         writel(reg, reg_base + CQSPI_REG_CONFIG);
 194 }
 195
 196 void cadence_qspi_apb_controller_disable(void *reg_base)
 197 {
 198         unsigned int reg;
 199         reg = readl(reg_base + CQSPI_REG_CONFIG);
 200         reg &= ~CQSPI_REG_CONFIG_ENABLE;
 201         writel(reg, reg_base + CQSPI_REG_CONFIG);
 202 }
 203
 204 /* Return 1 if idle, otherwise return 0 (busy). */
 205 static unsigned int cadence_qspi_wait_idle(void *reg_base)
 206 {
 207         unsigned int start, count = 0;
 208         /* timeout in unit of ms */
 209         unsigned int timeout = 5000;
 210
 211         start = get_timer(0);
 212         for ( ; get_timer(start) < timeout ; ) {
 213                 if (CQSPI_REG_IS_IDLE(reg_base))
 214                         count++;
 215                 else
 216                         count = 0;
 217                 /*
 218                  * Ensure the QSPI controller is in true idle state after
 219                  * reading back the same idle status consecutively
 220                  */
 221                 if (count >= CQSPI_POLL_IDLE_RETRY)
 222                         return 1;
 223         }
 224
 225         /* Timeout, still in busy mode. */
 226         printf("QSPI: QSPI is still busy after poll for %d times.\n",
 227                CQSPI_REG_RETRY);
 228         return 0;
 229 }
 230
 231 void cadence_qspi_apb_readdata_capture(void *reg_base,
 232                                 unsigned int bypass, unsigned int delay)
 233 {
 234         unsigned int reg;
 235         cadence_qspi_apb_controller_disable(reg_base);
 236
 237         reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 238
 239         if (bypass)
 240                 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 241         else
 242                 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 243
 244         reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
 245                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
 246
 247         reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
 248                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
 249
 250         writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 251
 252         cadence_qspi_apb_controller_enable(reg_base);
 253 }
 254
 255 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 256         unsigned int ref_clk_hz, unsigned int sclk_hz)
 257 {
 258         unsigned int reg;
 259         unsigned int div;
 260
 261         cadence_qspi_apb_controller_disable(reg_base);
 262         reg = readl(reg_base + CQSPI_REG_CONFIG);
 263         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 264
 265         /*
 266          * The baud_div field in the config reg is 4 bits, and the ref clock is
 267          * divided by 2 * (baud_div + 1). Round up the divider to ensure the
 268          * SPI clock rate is less than or equal to the requested clock rate.
 269          */
 270         div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
 271
 272         /* ensure the baud rate doesn't exceed the max value */
 273         if (div > CQSPI_REG_CONFIG_BAUD_MASK)
 274                 div = CQSPI_REG_CONFIG_BAUD_MASK;
 275
 276         debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
 277               ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
 278
 279         reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
 280         writel(reg, reg_base + CQSPI_REG_CONFIG);
 281
 282         cadence_qspi_apb_controller_enable(reg_base);
 283 }
 284
 285 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
 286 {
 287         unsigned int reg;
 288
 289         cadence_qspi_apb_controller_disable(reg_base);
 290         reg = readl(reg_base + CQSPI_REG_CONFIG);
 291         reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
 292
 293         if (mode & SPI_CPOL)
 294                 reg |= CQSPI_REG_CONFIG_CLK_POL;
 295         if (mode & SPI_CPHA)
 296                 reg |= CQSPI_REG_CONFIG_CLK_PHA;
 297
 298         writel(reg, reg_base + CQSPI_REG_CONFIG);
 299
 300         cadence_qspi_apb_controller_enable(reg_base);
 301 }
 302
 303 void cadence_qspi_apb_chipselect(void *reg_base,
 304         unsigned int chip_select, unsigned int decoder_enable)
 305 {
 306         unsigned int reg;
 307
 308         cadence_qspi_apb_controller_disable(reg_base);
 309
 310         debug("%s : chipselect %d decode %d\n", __func__, chip_select,
 311               decoder_enable);
 312
 313         reg = readl(reg_base + CQSPI_REG_CONFIG);
 314         /* docoder */
 315         if (decoder_enable) {
 316                 reg |= CQSPI_REG_CONFIG_DECODE;
 317         } else {
 318                 reg &= ~CQSPI_REG_CONFIG_DECODE;
 319                 /* Convert CS if without decoder.
 320                  * CS0 to 4b'1110
 321                  * CS1 to 4b'1101
 322                  * CS2 to 4b'1011
 323                  * CS3 to 4b'0111
 324                  */
 325                 chip_select = 0xF & ~(1 << chip_select);
 326         }
 327
 328         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 329                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 330         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 331                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 332         writel(reg, reg_base + CQSPI_REG_CONFIG);
 333
 334         cadence_qspi_apb_controller_enable(reg_base);
 335 }
 336
 337 void cadence_qspi_apb_delay(void *reg_base,
 338         unsigned int ref_clk, unsigned int sclk_hz,
 339         unsigned int tshsl_ns, unsigned int tsd2d_ns,
 340         unsigned int tchsh_ns, unsigned int tslch_ns)
 341 {
 342         unsigned int ref_clk_ns;
 343         unsigned int sclk_ns;
 344         unsigned int tshsl, tchsh, tslch, tsd2d;
 345         unsigned int reg;
 346
 347         cadence_qspi_apb_controller_disable(reg_base);
 348
 349         /* Convert to ns. */
 350         ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
 351
 352         /* Convert to ns. */
 353         sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
 354
 355         /* The controller adds additional delay to that programmed in the reg */
 356         if (tshsl_ns >= sclk_ns + ref_clk_ns)
 357                 tshsl_ns -= sclk_ns + ref_clk_ns;
 358         if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
 359                 tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
 360         tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
 361         tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
 362         tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
 363         tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
 364
 365         reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 366                         << CQSPI_REG_DELAY_TSHSL_LSB);
 367         reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 368                         << CQSPI_REG_DELAY_TCHSH_LSB);
 369         reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 370                         << CQSPI_REG_DELAY_TSLCH_LSB);
 371         reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 372                         << CQSPI_REG_DELAY_TSD2D_LSB);
 373         writel(reg, reg_base + CQSPI_REG_DELAY);
 374
 375         cadence_qspi_apb_controller_enable(reg_base);
 376 }
 377
 378 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 379 {
 380         unsigned reg;
 381
 382         cadence_qspi_apb_controller_disable(plat->regbase);
 383
 384         /* Configure the device size and address bytes */
 385         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 386         /* Clear the previous value */
 387         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 388         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 389         reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 390         reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
 391         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 392
 393         /* Configure the remap address register, no remap */
 394         writel(0, plat->regbase + CQSPI_REG_REMAP);
 395
 396         /* Indirect mode configurations */
 397         writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);
 398
 399         /* Disable all interrupts */
 400         writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 401
 402         cadence_qspi_apb_controller_enable(plat->regbase);
 403 }
 404
 405 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
 406         unsigned int reg)
 407 {
 408         unsigned int retry = CQSPI_REG_RETRY;
 409
 410         /* Write the CMDCTRL without start execution. */
 411         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 412         /* Start execute */
 413         reg |= CQSPI_REG_CMDCTRL_EXECUTE;
 414         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 415
 416         while (retry--) {
 417                 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
 418                 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
 419                         break;
 420                 udelay(1);
 421         }
 422
 423         if (!retry) {
 424                 printf("QSPI: flash command execution timeout\n");
 425                 return -EIO;
 426         }
 427
 428         /* Polling QSPI idle status. */
 429         if (!cadence_qspi_wait_idle(reg_base))
 430                 return -EIO;
 431
 432         return 0;
 433 }
 434
 435 /* For command RDID, RDSR. */
 436 int cadence_qspi_apb_command_read(void *reg_base,
 437         unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
 438         u8 *rxbuf)
 439 {
 440         unsigned int reg;
 441         unsigned int read_len;
 442         int status;
 443
 444         if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
 445                 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
 446                        cmdlen, rxlen);
 447                 return -EINVAL;
 448         }
 449
 450         reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 451
 452         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 453
 454         /* 0 means 1 byte. */
 455         reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 456                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 457         status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 458         if (status != 0)
 459                 return status;
 460
 461         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 462
 463         /* Put the read value into rx_buf */
 464         read_len = (rxlen > 4) ? 4 : rxlen;
 465         memcpy(rxbuf, &reg, read_len);
 466         rxbuf += read_len;
 467
 468         if (rxlen > 4) {
 469                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 470
 471                 read_len = rxlen - read_len;
 472                 memcpy(rxbuf, &reg, read_len);
 473         }
 474         return 0;
 475 }
 476
 477 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
 478 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
 479         const u8 *cmdbuf, unsigned int txlen,  const u8 *txbuf)
 480 {
 481         unsigned int reg = 0;
 482         unsigned int addr_value;
 483         unsigned int wr_data;
 484         unsigned int wr_len;
 485
 486         if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
 487                 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
 488                        cmdlen, txlen);
 489                 return -EINVAL;
 490         }
 491
 492         reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 493
 494         if (cmdlen == 4 || cmdlen == 5) {
 495                 /* Command with address */
 496                 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 497                 /* Number of bytes to write. */
 498                 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 499                         << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 500                 /* Get address */
 501                 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
 502                         cmdlen >= 5 ? 4 : 3);
 503
 504                 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
 505         }
 506
 507         if (txlen) {
 508                 /* writing data = yes */
 509                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 510                 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 511                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 512
 513                 wr_len = txlen > 4 ? 4 : txlen;
 514                 memcpy(&wr_data, txbuf, wr_len);
 515                 writel(wr_data, reg_base +
 516                         CQSPI_REG_CMDWRITEDATALOWER);
 517
 518                 if (txlen > 4) {
 519                         txbuf += wr_len;
 520                         wr_len = txlen - wr_len;
 521                         memcpy(&wr_data, txbuf, wr_len);
 522                         writel(wr_data, reg_base +
 523                                 CQSPI_REG_CMDWRITEDATAUPPER);
 524                 }
 525         }
 526
 527         /* Execute the command */
 528         return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 529 }
 530
 531 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
 532 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 533         unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf)
 534 {
 535         unsigned int reg;
 536         unsigned int rd_reg;
 537         unsigned int addr_value;
 538         unsigned int dummy_clk;
 539         unsigned int dummy_bytes;
 540         unsigned int addr_bytes;
 541
 542         /*
 543          * Identify addr_byte. All NOR flash device drivers are using fast read
 544          * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
 545          * With that, the length is in value of 5 or 6. Only FRAM chip from
 546          * ramtron using normal read (which won't need dummy byte).
 547          * Unlikely NOR flash using normal read due to performance issue.
 548          */
 549         if (cmdlen >= 5)
 550                 /* to cater fast read where cmd + addr + dummy */
 551                 addr_bytes = cmdlen - 2;
 552         else
 553                 /* for normal read (only ramtron as of now) */
 554                 addr_bytes = cmdlen - 1;
 555
 556         /* Setup the indirect trigger address */
 557         writel(plat->trigger_address,
 558                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 559
 560         /* Configure the opcode */
 561         rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 562
 563         if (rx_width & SPI_RX_QUAD)
 564                 /* Instruction and address at DQ0, data at DQ0-3. */
 565                 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 566
 567         /* Get address */
 568         addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 569         writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 570
 571         /* The remaining lenght is dummy bytes. */
 572         dummy_bytes = cmdlen - addr_bytes - 1;
 573         if (dummy_bytes) {
 574                 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
 575                         dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
 576
 577                 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 578 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
 579                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
 580 #else
 581                 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
 582 #endif
 583
 584                 /* Convert to clock cycles. */
 585                 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
 586                 /* Need to minus the mode byte (8 clocks). */
 587                 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
 588
 589                 if (dummy_clk)
 590                         rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 591                                 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 592         }
 593
 594         writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
 595
 596         /* set device size */
 597         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 598         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 599         reg |= (addr_bytes - 1);
 600         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 601         return 0;
 602 }
 603
 604 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
 605 {
 606         u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
 607         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 608         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 609 }
 610
 611 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
 612 {
 613         unsigned int timeout = 10000;
 614         u32 reg;
 615
 616         while (timeout--) {
 617                 reg = cadence_qspi_get_rd_sram_level(plat);
 618                 if (reg)
 619                         return reg;
 620                 udelay(1);
 621         }
 622
 623         return -ETIMEDOUT;
 624 }
 625
 626 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 627         unsigned int n_rx, u8 *rxbuf)
 628 {
 629         unsigned int remaining = n_rx;
 630         unsigned int bytes_to_read = 0;
 631         int ret;
 632
 633         writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
 634
 635         /* Start the indirect read transfer */
 636         writel(CQSPI_REG_INDIRECTRD_START,
 637                plat->regbase + CQSPI_REG_INDIRECTRD);
 638
 639         while (remaining > 0) {
 640                 ret = cadence_qspi_wait_for_data(plat);
 641                 if (ret < 0) {
 642                         printf("Indirect write timed out (%i)\n", ret);
 643                         goto failrd;
 644                 }
 645
 646                 bytes_to_read = ret;
 647
 648                 while (bytes_to_read != 0) {
 649                         bytes_to_read *= plat->fifo_width;
 650                         bytes_to_read = bytes_to_read > remaining ?
 651                                         remaining : bytes_to_read;
 652                         /*
 653                          * Handle non-4-byte aligned access to avoid
 654                          * data abort.
 655                          */
 656                         if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
 657                                 readsb(plat->ahbbase, rxbuf, bytes_to_read);
 658                         else
 659                                 readsl(plat->ahbbase, rxbuf,
 660                                        bytes_to_read >> 2);
 661                         rxbuf += bytes_to_read;
 662                         remaining -= bytes_to_read;
 663                         bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
 664                 }
 665         }
 666
 667         /* Check indirect done status */
 668         ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
 669                                 CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
 670         if (ret) {
 671                 printf("Indirect read completion error (%i)\n", ret);
 672                 goto failrd;
 673         }
 674
 675         /* Clear indirect completion status */
 676         writel(CQSPI_REG_INDIRECTRD_DONE,
 677                plat->regbase + CQSPI_REG_INDIRECTRD);
 678
 679         return 0;
 680
 681 failrd:
 682         /* Cancel the indirect read */
 683         writel(CQSPI_REG_INDIRECTRD_CANCEL,
 684                plat->regbase + CQSPI_REG_INDIRECTRD);
 685         return ret;
 686 }
 687
 688 /* Opcode + Address (3/4 bytes) */
 689 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 690         unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf)
 691 {
 692         unsigned int reg;
 693         unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
 694
 695         if (cmdlen < 4 || cmdbuf == NULL) {
 696                 printf("QSPI: Invalid input argument, len %d cmdbuf %p\n",
 697                        cmdlen, cmdbuf);
 698                 return -EINVAL;
 699         }
 700         /* Setup the indirect trigger address */
 701         writel(plat->trigger_address,
 702                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 703
 704         /* Configure the opcode */
 705         reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 706
 707         if (tx_width & SPI_TX_QUAD)
 708                 reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
 709
 710         writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
 711
 712         /* Setup write address. */
 713         reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 714         writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 715
 716         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 717         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 718         reg |= (addr_bytes - 1);
 719         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 720         return 0;
 721 }
 722
 723 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 724         unsigned int n_tx, const u8 *txbuf)
 725 {
 726         unsigned int page_size = plat->page_size;
 727         unsigned int remaining = n_tx;
 728         const u8 *bb_txbuf = txbuf;
 729         void *bounce_buf = NULL;
 730         unsigned int write_bytes;
 731         int ret;
 732
 733         /*
 734          * Use bounce buffer for non 32 bit aligned txbuf to avoid data
 735          * aborts
 736          */
 737         if ((uintptr_t)txbuf % 4) {
 738                 bounce_buf = malloc(n_tx);
 739                 if (!bounce_buf)
 740                         return -ENOMEM;
 741                 memcpy(bounce_buf, txbuf, n_tx);
 742                 bb_txbuf = bounce_buf;
 743         }
 744
 745         /* Configure the indirect read transfer bytes */
 746         writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
 747
 748         /* Start the indirect write transfer */
 749         writel(CQSPI_REG_INDIRECTWR_START,
 750                plat->regbase + CQSPI_REG_INDIRECTWR);
 751
 752         while (remaining > 0) {
 753                 write_bytes = remaining > page_size ? page_size : remaining;
 754                 writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
 755                 if (write_bytes % 4)
 756                         writesb(plat->ahbbase,
 757                                 bb_txbuf + rounddown(write_bytes, 4),
 758                                 write_bytes % 4);
 759
 760                 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
 761                                         CQSPI_REG_SDRAMLEVEL_WR_MASK <<
 762                                         CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
 763                 if (ret) {
 764                         printf("Indirect write timed out (%i)\n", ret);
 765                         goto failwr;
 766                 }
 767
 768                 bb_txbuf += write_bytes;
 769                 remaining -= write_bytes;
 770         }
 771
 772         /* Check indirect done status */
 773         ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
 774                                 CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
 775         if (ret) {
 776                 printf("Indirect write completion error (%i)\n", ret);
 777                 goto failwr;
 778         }
 779
 780         /* Clear indirect completion status */
 781         writel(CQSPI_REG_INDIRECTWR_DONE,
 782                plat->regbase + CQSPI_REG_INDIRECTWR);
 783         if (bounce_buf)
 784                 free(bounce_buf);
 785         return 0;
 786
 787 failwr:
 788         /* Cancel the indirect write */
 789         writel(CQSPI_REG_INDIRECTWR_CANCEL,
 790                plat->regbase + CQSPI_REG_INDIRECTWR);
 791         if (bounce_buf)
 792                 free(bounce_buf);
 793         return ret;
 794 }
 795
 796 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
 797 {
 798         unsigned int reg;
 799
 800         /* enter XiP mode immediately and enable direct mode */
 801         reg = readl(reg_base + CQSPI_REG_CONFIG);
 802         reg |= CQSPI_REG_CONFIG_ENABLE;
 803         reg |= CQSPI_REG_CONFIG_DIRECT;
 804         reg |= CQSPI_REG_CONFIG_XIP_IMM;
 805         writel(reg, reg_base + CQSPI_REG_CONFIG);
 806
 807         /* keep the XiP mode */
 808         writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
 809
 810         /* Enable mode bit at devrd */
 811         reg = readl(reg_base + CQSPI_REG_RD_INSTR);
 812         reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 813         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 814 }