2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * - Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * - Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * - Neither the name of the Altera Corporation nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <asm/errno.h>
31 #include "cadence_qspi.h"
33 #define CQSPI_REG_POLL_US (1) /* 1us */
34 #define CQSPI_REG_RETRY (10000)
35 #define CQSPI_POLL_IDLE_RETRY (3)
37 #define CQSPI_FIFO_WIDTH (4)
39 /* Controller sram size in word */
40 #define CQSPI_REG_SRAM_SIZE_WORD (128)
41 #define CQSPI_REG_SRAM_RESV_WORDS (2)
42 #define CQSPI_REG_SRAM_PARTITION_WR (1)
43 #define CQSPI_REG_SRAM_PARTITION_RD \
44 (CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS)
45 #define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
48 #define CQSPI_INST_TYPE_SINGLE (0)
49 #define CQSPI_INST_TYPE_DUAL (1)
50 #define CQSPI_INST_TYPE_QUAD (2)
52 #define CQSPI_STIG_DATA_LEN_MAX (8)
53 #define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF)
55 #define CQSPI_DUMMY_CLKS_PER_BYTE (8)
56 #define CQSPI_DUMMY_BYTES_MAX (4)
59 #define CQSPI_REG_SRAM_FILL_THRESHOLD \
60 ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
61 /****************************************************************************
62 * Controller's configuration and status register (offset from QSPI_BASE)
63 ****************************************************************************/
64 #define CQSPI_REG_CONFIG 0x00
65 #define CQSPI_REG_CONFIG_CLK_POL_LSB 1
66 #define CQSPI_REG_CONFIG_CLK_PHA_LSB 2
67 #define CQSPI_REG_CONFIG_ENABLE_MASK (1 << 0)
68 #define CQSPI_REG_CONFIG_DIRECT_MASK (1 << 7)
69 #define CQSPI_REG_CONFIG_DECODE_MASK (1 << 9)
70 #define CQSPI_REG_CONFIG_XIP_IMM_MASK (1 << 18)
71 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
72 #define CQSPI_REG_CONFIG_BAUD_LSB 19
73 #define CQSPI_REG_CONFIG_IDLE_LSB 31
74 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
75 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
77 #define CQSPI_REG_RD_INSTR 0x04
78 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
79 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
80 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
81 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
82 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
83 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
84 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
85 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
86 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
87 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
89 #define CQSPI_REG_WR_INSTR 0x08
90 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
92 #define CQSPI_REG_DELAY 0x0C
93 #define CQSPI_REG_DELAY_TSLCH_LSB 0
94 #define CQSPI_REG_DELAY_TCHSH_LSB 8
95 #define CQSPI_REG_DELAY_TSD2D_LSB 16
96 #define CQSPI_REG_DELAY_TSHSL_LSB 24
97 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
98 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
99 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
100 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
102 #define CQSPI_READLCAPTURE 0x10
103 #define CQSPI_READLCAPTURE_BYPASS_LSB 0
104 #define CQSPI_READLCAPTURE_DELAY_LSB 1
105 #define CQSPI_READLCAPTURE_DELAY_MASK 0xF
107 #define CQSPI_REG_SIZE 0x14
108 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
109 #define CQSPI_REG_SIZE_PAGE_LSB 4
110 #define CQSPI_REG_SIZE_BLOCK_LSB 16
111 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
112 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
113 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
115 #define CQSPI_REG_SRAMPARTITION 0x18
116 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
118 #define CQSPI_REG_REMAP 0x24
119 #define CQSPI_REG_MODE_BIT 0x28
121 #define CQSPI_REG_SDRAMLEVEL 0x2C
122 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
123 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
124 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
125 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
127 #define CQSPI_REG_IRQSTATUS 0x40
128 #define CQSPI_REG_IRQMASK 0x44
130 #define CQSPI_REG_INDIRECTRD 0x60
131 #define CQSPI_REG_INDIRECTRD_START_MASK (1 << 0)
132 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK (1 << 1)
133 #define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK (1 << 2)
134 #define CQSPI_REG_INDIRECTRD_DONE_MASK (1 << 5)
136 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
137 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
138 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
140 #define CQSPI_REG_CMDCTRL 0x90
141 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK (1 << 0)
142 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK (1 << 1)
143 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
144 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
145 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
146 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
147 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
148 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
149 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
150 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
151 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
152 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
153 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
154 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
155 #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
157 #define CQSPI_REG_INDIRECTWR 0x70
158 #define CQSPI_REG_INDIRECTWR_START_MASK (1 << 0)
159 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK (1 << 1)
160 #define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK (1 << 2)
161 #define CQSPI_REG_INDIRECTWR_DONE_MASK (1 << 5)
163 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
164 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
165 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
167 #define CQSPI_REG_CMDADDRESS 0x94
168 #define CQSPI_REG_CMDREADDATALOWER 0xA0
169 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
170 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
171 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
173 #define CQSPI_REG_IS_IDLE(base) \
174 ((readl(base + CQSPI_REG_CONFIG) >> \
175 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
177 #define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \
178 ((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
180 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
181 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
182 CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
184 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
185 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
186 CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
188 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
189 unsigned int addr_width)
193 addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
196 addr = (addr << 8) | addr_buf[3];
201 static void cadence_qspi_apb_read_fifo_data(void *dest,
202 const void *src_ahb_addr, unsigned int bytes)
205 int remaining = bytes;
206 unsigned int *dest_ptr = (unsigned int *)dest;
207 unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
209 while (remaining > 0) {
210 if (remaining >= CQSPI_FIFO_WIDTH) {
211 *dest_ptr = readl(src_ptr);
212 remaining -= CQSPI_FIFO_WIDTH;
215 temp = readl(src_ptr);
216 memcpy(dest_ptr, &temp, remaining);
225 static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
226 const void *src, unsigned int bytes)
229 int remaining = bytes;
230 unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
231 unsigned int *src_ptr = (unsigned int *)src;
233 while (remaining > 0) {
234 if (remaining >= CQSPI_FIFO_WIDTH) {
235 writel(*src_ptr, dest_ptr);
236 remaining -= sizeof(unsigned int);
239 memcpy(&temp, src_ptr, remaining);
240 writel(temp, dest_ptr);
249 /* Read from SRAM FIFO with polling SRAM fill level. */
250 static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
251 const void *src_addr, unsigned int num_bytes)
253 unsigned int remaining = num_bytes;
255 unsigned int sram_level = 0;
256 unsigned char *dest = (unsigned char *)dest_addr;
258 while (remaining > 0) {
259 retry = CQSPI_REG_RETRY;
261 sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base);
268 printf("QSPI: No receive data after polling for %d times\n",
273 sram_level *= CQSPI_FIFO_WIDTH;
274 sram_level = sram_level > remaining ? remaining : sram_level;
276 /* Read data from FIFO. */
277 cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level);
279 remaining -= sram_level;
285 /* Write to SRAM FIFO with polling SRAM fill level. */
286 static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
287 const void *src_addr, unsigned int num_bytes)
289 const void *reg_base = plat->regbase;
290 void *dest_addr = plat->ahbbase;
291 unsigned int retry = CQSPI_REG_RETRY;
292 unsigned int sram_level;
293 unsigned int wr_bytes;
294 unsigned char *src = (unsigned char *)src_addr;
295 int remaining = num_bytes;
296 unsigned int page_size = plat->page_size;
297 unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS;
299 while (remaining > 0) {
300 retry = CQSPI_REG_RETRY;
302 sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base);
303 if (sram_level <= sram_threshold_words)
307 printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)",
308 sram_level, sram_threshold_words);
311 /* Write a page or remaining bytes. */
312 wr_bytes = (remaining > page_size) ?
313 page_size : remaining;
315 cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes);
317 remaining -= wr_bytes;
323 void cadence_qspi_apb_controller_enable(void *reg_base)
326 reg = readl(reg_base + CQSPI_REG_CONFIG);
327 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
328 writel(reg, reg_base + CQSPI_REG_CONFIG);
332 void cadence_qspi_apb_controller_disable(void *reg_base)
335 reg = readl(reg_base + CQSPI_REG_CONFIG);
336 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
337 writel(reg, reg_base + CQSPI_REG_CONFIG);
341 /* Return 1 if idle, otherwise return 0 (busy). */
342 static unsigned int cadence_qspi_wait_idle(void *reg_base)
344 unsigned int start, count = 0;
345 /* timeout in unit of ms */
346 unsigned int timeout = 5000;
348 start = get_timer(0);
349 for ( ; get_timer(start) < timeout ; ) {
350 if (CQSPI_REG_IS_IDLE(reg_base))
355 * Ensure the QSPI controller is in true idle state after
356 * reading back the same idle status consecutively
358 if (count >= CQSPI_POLL_IDLE_RETRY)
362 /* Timeout, still in busy mode. */
363 printf("QSPI: QSPI is still busy after poll for %d times.\n",
368 void cadence_qspi_apb_readdata_capture(void *reg_base,
369 unsigned int bypass, unsigned int delay)
372 cadence_qspi_apb_controller_disable(reg_base);
374 reg = readl(reg_base + CQSPI_READLCAPTURE);
377 reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
379 reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
381 reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
382 << CQSPI_READLCAPTURE_DELAY_LSB);
384 reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
385 << CQSPI_READLCAPTURE_DELAY_LSB);
387 writel(reg, reg_base + CQSPI_READLCAPTURE);
389 cadence_qspi_apb_controller_enable(reg_base);
393 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
394 unsigned int ref_clk_hz, unsigned int sclk_hz)
399 cadence_qspi_apb_controller_disable(reg_base);
400 reg = readl(reg_base + CQSPI_REG_CONFIG);
401 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
403 div = ref_clk_hz / sclk_hz;
408 /* Check if even number. */
412 if (ref_clk_hz % sclk_hz)
413 /* ensure generated SCLK doesn't exceed user
420 debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
421 ref_clk_hz, sclk_hz, div);
423 div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
425 writel(reg, reg_base + CQSPI_REG_CONFIG);
427 cadence_qspi_apb_controller_enable(reg_base);
431 void cadence_qspi_apb_set_clk_mode(void *reg_base,
432 unsigned int clk_pol, unsigned int clk_pha)
436 cadence_qspi_apb_controller_disable(reg_base);
437 reg = readl(reg_base + CQSPI_REG_CONFIG);
439 (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
441 reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
442 reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
444 writel(reg, reg_base + CQSPI_REG_CONFIG);
446 cadence_qspi_apb_controller_enable(reg_base);
450 void cadence_qspi_apb_chipselect(void *reg_base,
451 unsigned int chip_select, unsigned int decoder_enable)
455 cadence_qspi_apb_controller_disable(reg_base);
457 debug("%s : chipselect %d decode %d\n", __func__, chip_select,
460 reg = readl(reg_base + CQSPI_REG_CONFIG);
462 if (decoder_enable) {
463 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
465 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
466 /* Convert CS if without decoder.
472 chip_select = 0xF & ~(1 << chip_select);
475 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
476 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
477 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
478 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
479 writel(reg, reg_base + CQSPI_REG_CONFIG);
481 cadence_qspi_apb_controller_enable(reg_base);
485 void cadence_qspi_apb_delay(void *reg_base,
486 unsigned int ref_clk, unsigned int sclk_hz,
487 unsigned int tshsl_ns, unsigned int tsd2d_ns,
488 unsigned int tchsh_ns, unsigned int tslch_ns)
490 unsigned int ref_clk_ns;
491 unsigned int sclk_ns;
492 unsigned int tshsl, tchsh, tslch, tsd2d;
495 cadence_qspi_apb_controller_disable(reg_base);
498 ref_clk_ns = (1000000000) / ref_clk;
501 sclk_ns = (1000000000) / sclk_hz;
503 /* Plus 1 to round up 1 clock cycle. */
504 tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
505 tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
506 tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
507 tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
509 reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
510 << CQSPI_REG_DELAY_TSHSL_LSB);
511 reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
512 << CQSPI_REG_DELAY_TCHSH_LSB);
513 reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
514 << CQSPI_REG_DELAY_TSLCH_LSB);
515 reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
516 << CQSPI_REG_DELAY_TSD2D_LSB);
517 writel(reg, reg_base + CQSPI_REG_DELAY);
519 cadence_qspi_apb_controller_enable(reg_base);
523 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
527 cadence_qspi_apb_controller_disable(plat->regbase);
529 /* Configure the device size and address bytes */
530 reg = readl(plat->regbase + CQSPI_REG_SIZE);
531 /* Clear the previous value */
532 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
533 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
534 reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
535 reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
536 writel(reg, plat->regbase + CQSPI_REG_SIZE);
538 /* Configure the remap address register, no remap */
539 writel(0, plat->regbase + CQSPI_REG_REMAP);
541 /* Disable all interrupts */
542 writel(0, plat->regbase + CQSPI_REG_IRQMASK);
544 cadence_qspi_apb_controller_enable(plat->regbase);
548 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
551 unsigned int retry = CQSPI_REG_RETRY;
553 /* Write the CMDCTRL without start execution. */
554 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
556 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
557 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
560 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
561 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
567 printf("QSPI: flash command execution timeout\n");
571 /* Polling QSPI idle status. */
572 if (!cadence_qspi_wait_idle(reg_base))
578 /* For command RDID, RDSR. */
579 int cadence_qspi_apb_command_read(void *reg_base,
580 unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
584 unsigned int read_len;
587 if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
588 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
593 reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
595 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
597 /* 0 means 1 byte. */
598 reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
599 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
600 status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
604 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
606 /* Put the read value into rx_buf */
607 read_len = (rxlen > 4) ? 4 : rxlen;
608 memcpy(rxbuf, ®, read_len);
612 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
614 read_len = rxlen - read_len;
615 memcpy(rxbuf, ®, read_len);
620 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
621 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
622 const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf)
624 unsigned int reg = 0;
625 unsigned int addr_value;
626 unsigned int wr_data;
629 if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
630 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
635 reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
637 if (cmdlen == 4 || cmdlen == 5) {
638 /* Command with address */
639 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
640 /* Number of bytes to write. */
641 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
642 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
644 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
645 cmdlen >= 5 ? 4 : 3);
647 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
651 /* writing data = yes */
652 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
653 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
654 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
656 wr_len = txlen > 4 ? 4 : txlen;
657 memcpy(&wr_data, txbuf, wr_len);
658 writel(wr_data, reg_base +
659 CQSPI_REG_CMDWRITEDATALOWER);
663 wr_len = txlen - wr_len;
664 memcpy(&wr_data, txbuf, wr_len);
665 writel(wr_data, reg_base +
666 CQSPI_REG_CMDWRITEDATAUPPER);
670 /* Execute the command */
671 return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
674 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
675 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
676 unsigned int cmdlen, const u8 *cmdbuf)
680 unsigned int addr_value;
681 unsigned int dummy_clk;
682 unsigned int dummy_bytes;
683 unsigned int addr_bytes;
686 * Identify addr_byte. All NOR flash device drivers are using fast read
687 * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
688 * With that, the length is in value of 5 or 6. Only FRAM chip from
689 * ramtron using normal read (which won't need dummy byte).
690 * Unlikely NOR flash using normal read due to performance issue.
693 /* to cater fast read where cmd + addr + dummy */
694 addr_bytes = cmdlen - 2;
696 /* for normal read (only ramtron as of now) */
697 addr_bytes = cmdlen - 1;
699 /* Setup the indirect trigger address */
700 writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
701 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
703 /* Configure SRAM partition for read. */
704 writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase +
705 CQSPI_REG_SRAMPARTITION);
707 /* Configure the opcode */
708 rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
710 #if (CONFIG_SPI_FLASH_QUAD == 1)
711 /* Instruction and address at DQ0, data at DQ0-3. */
712 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
716 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
717 writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
719 /* The remaining lenght is dummy bytes. */
720 dummy_bytes = cmdlen - addr_bytes - 1;
722 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
723 dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
725 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
726 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
727 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
729 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
732 /* Convert to clock cycles. */
733 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
734 /* Need to minus the mode byte (8 clocks). */
735 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
738 rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
739 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
742 writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
744 /* set device size */
745 reg = readl(plat->regbase + CQSPI_REG_SIZE);
746 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
747 reg |= (addr_bytes - 1);
748 writel(reg, plat->regbase + CQSPI_REG_SIZE);
752 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
753 unsigned int rxlen, u8 *rxbuf)
757 writel(rxlen, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
759 /* Start the indirect read transfer */
760 writel(CQSPI_REG_INDIRECTRD_START_MASK,
761 plat->regbase + CQSPI_REG_INDIRECTRD);
763 if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
764 (const void *)plat->ahbbase, rxlen))
767 /* Check flash indirect controller */
768 reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
769 if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) {
770 reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
771 printf("QSPI: indirect completion status error with reg 0x%08x\n",
776 /* Clear indirect completion status */
777 writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
778 plat->regbase + CQSPI_REG_INDIRECTRD);
782 /* Cancel the indirect read */
783 writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
784 plat->regbase + CQSPI_REG_INDIRECTRD);
788 /* Opcode + Address (3/4 bytes) */
789 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
790 unsigned int cmdlen, const u8 *cmdbuf)
793 unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
795 if (cmdlen < 4 || cmdbuf == NULL) {
796 printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
797 cmdlen, (unsigned int)cmdbuf);
800 /* Setup the indirect trigger address */
801 writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
802 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
804 writel(CQSPI_REG_SRAM_PARTITION_WR,
805 plat->regbase + CQSPI_REG_SRAMPARTITION);
807 /* Configure the opcode */
808 reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
809 writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
811 /* Setup write address. */
812 reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
813 writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
815 reg = readl(plat->regbase + CQSPI_REG_SIZE);
816 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
817 reg |= (addr_bytes - 1);
818 writel(reg, plat->regbase + CQSPI_REG_SIZE);
822 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
823 unsigned int txlen, const u8 *txbuf)
825 unsigned int reg = 0;
828 /* Configure the indirect read transfer bytes */
829 writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
831 /* Start the indirect write transfer */
832 writel(CQSPI_REG_INDIRECTWR_START_MASK,
833 plat->regbase + CQSPI_REG_INDIRECTWR);
835 if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen))
838 /* Wait until last write is completed (FIFO empty) */
839 retry = CQSPI_REG_RETRY;
841 reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase);
849 printf("QSPI: timeout for indirect write\n");
853 /* Check flash indirect controller status */
854 retry = CQSPI_REG_RETRY;
856 reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR);
857 if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
862 if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) {
863 printf("QSPI: indirect completion status error with reg 0x%08x\n",
868 /* Clear indirect completion status */
869 writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
870 plat->regbase + CQSPI_REG_INDIRECTWR);
874 /* Cancel the indirect write */
875 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
876 plat->regbase + CQSPI_REG_INDIRECTWR);
880 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
884 /* enter XiP mode immediately and enable direct mode */
885 reg = readl(reg_base + CQSPI_REG_CONFIG);
886 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
887 reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
888 reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
889 writel(reg, reg_base + CQSPI_REG_CONFIG);
891 /* keep the XiP mode */
892 writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
894 /* Enable mode bit at devrd */
895 reg = readl(reg_base + CQSPI_REG_RD_INSTR);
896 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
897 writel(reg, reg_base + CQSPI_REG_RD_INSTR);