1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Altera Corporation <www.altera.com>
7 #ifndef __CADENCE_QSPI_H__
8 #define __CADENCE_QSPI_H__
12 #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
14 #define CQSPI_NO_DECODER_MAX_CS 4
15 #define CQSPI_DECODER_MAX_CS 16
16 #define CQSPI_READ_CAPTURE_MAX_DELAY 16
18 struct cadence_spi_platdata {
19 unsigned int ref_clk_hz;
28 /* Flash parameters */
37 struct cadence_spi_priv {
45 unsigned int qspi_calibrated_hz;
46 unsigned int qspi_calibrated_cs;
47 unsigned int previous_hz;
49 struct reset_ctl_bulk resets;
52 /* Functions call declaration */
53 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
54 void cadence_qspi_apb_controller_enable(void *reg_base_addr);
55 void cadence_qspi_apb_controller_disable(void *reg_base_addr);
57 int cadence_qspi_apb_command_read(void *reg_base_addr,
58 unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
59 int cadence_qspi_apb_command_write(void *reg_base_addr,
60 unsigned int cmdlen, const u8 *cmdbuf,
61 unsigned int txlen, const u8 *txbuf);
63 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
64 unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
65 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
66 unsigned int rxlen, u8 *rxbuf);
67 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
68 unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf);
69 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
70 unsigned int txlen, const u8 *txbuf);
72 void cadence_qspi_apb_chipselect(void *reg_base,
73 unsigned int chip_select, unsigned int decoder_enable);
74 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
75 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
76 unsigned int ref_clk_hz, unsigned int sclk_hz);
77 void cadence_qspi_apb_delay(void *reg_base,
78 unsigned int ref_clk, unsigned int sclk_hz,
79 unsigned int tshsl_ns, unsigned int tsd2d_ns,
80 unsigned int tchsh_ns, unsigned int tslch_ns);
81 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
82 void cadence_qspi_apb_readdata_capture(void *reg_base,
83 unsigned int bypass, unsigned int delay);
85 #endif /* __CADENCE_QSPI_H__ */