1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Altera Corporation <www.altera.com>
7 #ifndef __CADENCE_QSPI_H__
8 #define __CADENCE_QSPI_H__
12 #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
14 #define CQSPI_NO_DECODER_MAX_CS 4
15 #define CQSPI_DECODER_MAX_CS 16
16 #define CQSPI_READ_CAPTURE_MAX_DELAY 16
18 struct cadence_spi_platdata {
19 unsigned int ref_clk_hz;
30 /* Flash parameters */
39 struct cadence_spi_priv {
47 unsigned int qspi_calibrated_hz;
48 unsigned int qspi_calibrated_cs;
49 unsigned int previous_hz;
51 struct reset_ctl_bulk resets;
54 /* Functions call declaration */
55 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
56 void cadence_qspi_apb_controller_enable(void *reg_base_addr);
57 void cadence_qspi_apb_controller_disable(void *reg_base_addr);
58 void cadence_qspi_apb_dac_mode_enable(void *reg_base);
60 int cadence_qspi_apb_command_read(void *reg_base_addr,
61 const struct spi_mem_op *op);
62 int cadence_qspi_apb_command_write(void *reg_base_addr,
63 const struct spi_mem_op *op);
65 int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
66 const struct spi_mem_op *op);
67 int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
68 const struct spi_mem_op *op);
69 int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
70 const struct spi_mem_op *op);
71 int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
72 const struct spi_mem_op *op);
74 void cadence_qspi_apb_chipselect(void *reg_base,
75 unsigned int chip_select, unsigned int decoder_enable);
76 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
77 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
78 unsigned int ref_clk_hz, unsigned int sclk_hz);
79 void cadence_qspi_apb_delay(void *reg_base,
80 unsigned int ref_clk, unsigned int sclk_hz,
81 unsigned int tshsl_ns, unsigned int tsd2d_ns,
82 unsigned int tchsh_ns, unsigned int tslch_ns);
83 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
84 void cadence_qspi_apb_readdata_capture(void *reg_base,
85 unsigned int bypass, unsigned int delay);
87 #endif /* __CADENCE_QSPI_H__ */