drivers/spi/cadence_qspi.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2012
   4  * Altera Corporation <www.altera.com>
   5  */
   6
   7 #ifndef __CADENCE_QSPI_H__
   8 #define __CADENCE_QSPI_H__
   9
  10 #include <reset.h>
  11
  12 #define CQSPI_IS_ADDR(cmd_len)          (cmd_len > 1 ? 1 : 0)
  13
  14 #define CQSPI_NO_DECODER_MAX_CS         4
  15 #define CQSPI_DECODER_MAX_CS            16
  16 #define CQSPI_READ_CAPTURE_MAX_DELAY    16
  17
  18 struct cadence_spi_platdata {
  19         unsigned int    ref_clk_hz;
  20         unsigned int    max_hz;
  21         void            *regbase;
  22         void            *ahbbase;
  23         bool            is_decoded_cs;
  24         u32             fifo_depth;
  25         u32             fifo_width;
  26         u32             trigger_address;
  27
  28         /* Flash parameters */
  29         u32             page_size;
  30         u32             block_size;
  31         u32             tshsl_ns;
  32         u32             tsd2d_ns;
  33         u32             tchsh_ns;
  34         u32             tslch_ns;
  35 };
  36
  37 struct cadence_spi_priv {
  38         void            *regbase;
  39         void            *ahbbase;
  40         size_t          cmd_len;
  41         u8              cmd_buf[32];
  42         size_t          data_len;
  43
  44         int             qspi_is_init;
  45         unsigned int    qspi_calibrated_hz;
  46         unsigned int    qspi_calibrated_cs;
  47         unsigned int    previous_hz;
  48
  49         struct reset_ctl_bulk resets;
  50 };
  51
  52 /* Functions call declaration */
  53 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
  54 void cadence_qspi_apb_controller_enable(void *reg_base_addr);
  55 void cadence_qspi_apb_controller_disable(void *reg_base_addr);
  56
  57 int cadence_qspi_apb_command_read(void *reg_base_addr,
  58         unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
  59 int cadence_qspi_apb_command_write(void *reg_base_addr,
  60         unsigned int cmdlen, const u8 *cmdbuf,
  61         unsigned int txlen,  const u8 *txbuf);
  62
  63 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
  64         unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
  65 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
  66         unsigned int rxlen, u8 *rxbuf);
  67 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
  68         unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf);
  69 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
  70         unsigned int txlen, const u8 *txbuf);
  71
  72 void cadence_qspi_apb_chipselect(void *reg_base,
  73         unsigned int chip_select, unsigned int decoder_enable);
  74 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
  75 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
  76         unsigned int ref_clk_hz, unsigned int sclk_hz);
  77 void cadence_qspi_apb_delay(void *reg_base,
  78         unsigned int ref_clk, unsigned int sclk_hz,
  79         unsigned int tshsl_ns, unsigned int tsd2d_ns,
  80         unsigned int tchsh_ns, unsigned int tslch_ns);
  81 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
  82 void cadence_qspi_apb_readdata_capture(void *reg_base,
  83         unsigned int bypass, unsigned int delay);
  84
  85 #endif /* __CADENCE_QSPI_H__ */