drivers/spi/cadence_qspi.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2012
   4  * Altera Corporation <www.altera.com>
   5  */
   6
   7 #ifndef __CADENCE_QSPI_H__
   8 #define __CADENCE_QSPI_H__
   9
  10 #include <reset.h>
  11
  12 #define CQSPI_IS_ADDR(cmd_len)          (cmd_len > 1 ? 1 : 0)
  13
  14 #define CQSPI_NO_DECODER_MAX_CS         4
  15 #define CQSPI_DECODER_MAX_CS            16
  16 #define CQSPI_READ_CAPTURE_MAX_DELAY    16
  17
  18 struct cadence_spi_platdata {
  19         unsigned int    max_hz;
  20         void            *regbase;
  21         void            *ahbbase;
  22         bool            is_decoded_cs;
  23         u32             fifo_depth;
  24         u32             fifo_width;
  25         u32             trigger_address;
  26
  27         /* Flash parameters */
  28         u32             page_size;
  29         u32             block_size;
  30         u32             tshsl_ns;
  31         u32             tsd2d_ns;
  32         u32             tchsh_ns;
  33         u32             tslch_ns;
  34 };
  35
  36 struct cadence_spi_priv {
  37         void            *regbase;
  38         void            *ahbbase;
  39         size_t          cmd_len;
  40         u8              cmd_buf[32];
  41         size_t          data_len;
  42
  43         int             qspi_is_init;
  44         unsigned int    qspi_calibrated_hz;
  45         unsigned int    qspi_calibrated_cs;
  46         unsigned int    previous_hz;
  47
  48         struct reset_ctl_bulk resets;
  49 };
  50
  51 /* Functions call declaration */
  52 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
  53 void cadence_qspi_apb_controller_enable(void *reg_base_addr);
  54 void cadence_qspi_apb_controller_disable(void *reg_base_addr);
  55
  56 int cadence_qspi_apb_command_read(void *reg_base_addr,
  57         unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
  58 int cadence_qspi_apb_command_write(void *reg_base_addr,
  59         unsigned int cmdlen, const u8 *cmdbuf,
  60         unsigned int txlen,  const u8 *txbuf);
  61
  62 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
  63         unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
  64 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
  65         unsigned int rxlen, u8 *rxbuf);
  66 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
  67         unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf);
  68 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
  69         unsigned int txlen, const u8 *txbuf);
  70
  71 void cadence_qspi_apb_chipselect(void *reg_base,
  72         unsigned int chip_select, unsigned int decoder_enable);
  73 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
  74 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
  75         unsigned int ref_clk_hz, unsigned int sclk_hz);
  76 void cadence_qspi_apb_delay(void *reg_base,
  77         unsigned int ref_clk, unsigned int sclk_hz,
  78         unsigned int tshsl_ns, unsigned int tsd2d_ns,
  79         unsigned int tchsh_ns, unsigned int tslch_ns);
  80 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
  81 void cadence_qspi_apb_readdata_capture(void *reg_base,
  82         unsigned int bypass, unsigned int delay);
  83
  84 #endif /* __CADENCE_QSPI_H__ */