1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Altera Corporation <www.altera.com>
7 #ifndef __CADENCE_QSPI_H__
8 #define __CADENCE_QSPI_H__
12 #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
14 #define CQSPI_NO_DECODER_MAX_CS 4
15 #define CQSPI_DECODER_MAX_CS 16
16 #define CQSPI_READ_CAPTURE_MAX_DELAY 16
18 struct cadence_spi_platdata {
27 /* Flash parameters */
36 struct cadence_spi_priv {
44 unsigned int qspi_calibrated_hz;
45 unsigned int qspi_calibrated_cs;
46 unsigned int previous_hz;
48 struct reset_ctl_bulk resets;
51 /* Functions call declaration */
52 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
53 void cadence_qspi_apb_controller_enable(void *reg_base_addr);
54 void cadence_qspi_apb_controller_disable(void *reg_base_addr);
56 int cadence_qspi_apb_command_read(void *reg_base_addr,
57 unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
58 int cadence_qspi_apb_command_write(void *reg_base_addr,
59 unsigned int cmdlen, const u8 *cmdbuf,
60 unsigned int txlen, const u8 *txbuf);
62 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
63 unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
64 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
65 unsigned int rxlen, u8 *rxbuf);
66 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
67 unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf);
68 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
69 unsigned int txlen, const u8 *txbuf);
71 void cadence_qspi_apb_chipselect(void *reg_base,
72 unsigned int chip_select, unsigned int decoder_enable);
73 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
74 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
75 unsigned int ref_clk_hz, unsigned int sclk_hz);
76 void cadence_qspi_apb_delay(void *reg_base,
77 unsigned int ref_clk, unsigned int sclk_hz,
78 unsigned int tshsl_ns, unsigned int tsd2d_ns,
79 unsigned int tchsh_ns, unsigned int tslch_ns);
80 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
81 void cadence_qspi_apb_readdata_capture(void *reg_base,
82 unsigned int bypass, unsigned int delay);
84 #endif /* __CADENCE_QSPI_H__ */