drivers/spi/cadence_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012
   4  * Altera Corporation <www.altera.com>
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <fdtdec.h>
  10 #include <malloc.h>
  11 #include <reset.h>
  12 #include <spi.h>
  13 #include <linux/errno.h>
  14 #include "cadence_qspi.h"
  15
  16 #define CQSPI_STIG_READ                 0
  17 #define CQSPI_STIG_WRITE                1
  18 #define CQSPI_INDIRECT_READ             2
  19 #define CQSPI_INDIRECT_WRITE            3
  20
  21 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
  22 {
  23         struct cadence_spi_platdata *plat = bus->platdata;
  24         struct cadence_spi_priv *priv = dev_get_priv(bus);
  25
  26         cadence_qspi_apb_config_baudrate_div(priv->regbase,
  27                                              CONFIG_CQSPI_REF_CLK, hz);
  28
  29         /* Reconfigure delay timing if speed is changed. */
  30         cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
  31                                plat->tshsl_ns, plat->tsd2d_ns,
  32                                plat->tchsh_ns, plat->tslch_ns);
  33
  34         return 0;
  35 }
  36
  37 /* Calibration sequence to determine the read data capture delay register */
  38 static int spi_calibration(struct udevice *bus, uint hz)
  39 {
  40         struct cadence_spi_priv *priv = dev_get_priv(bus);
  41         void *base = priv->regbase;
  42         u8 opcode_rdid = 0x9F;
  43         unsigned int idcode = 0, temp = 0;
  44         int err = 0, i, range_lo = -1, range_hi = -1;
  45
  46         /* start with slowest clock (1 MHz) */
  47         cadence_spi_write_speed(bus, 1000000);
  48
  49         /* configure the read data capture delay register to 0 */
  50         cadence_qspi_apb_readdata_capture(base, 1, 0);
  51
  52         /* Enable QSPI */
  53         cadence_qspi_apb_controller_enable(base);
  54
  55         /* read the ID which will be our golden value */
  56         err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
  57                 3, (u8 *)&idcode);
  58         if (err) {
  59                 puts("SF: Calibration failed (read)\n");
  60                 return err;
  61         }
  62
  63         /* use back the intended clock and find low range */
  64         cadence_spi_write_speed(bus, hz);
  65         for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
  66                 /* Disable QSPI */
  67                 cadence_qspi_apb_controller_disable(base);
  68
  69                 /* reconfigure the read data capture delay register */
  70                 cadence_qspi_apb_readdata_capture(base, 1, i);
  71
  72                 /* Enable back QSPI */
  73                 cadence_qspi_apb_controller_enable(base);
  74
  75                 /* issue a RDID to get the ID value */
  76                 err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
  77                         3, (u8 *)&temp);
  78                 if (err) {
  79                         puts("SF: Calibration failed (read)\n");
  80                         return err;
  81                 }
  82
  83                 /* search for range lo */
  84                 if (range_lo == -1 && temp == idcode) {
  85                         range_lo = i;
  86                         continue;
  87                 }
  88
  89                 /* search for range hi */
  90                 if (range_lo != -1 && temp != idcode) {
  91                         range_hi = i - 1;
  92                         break;
  93                 }
  94                 range_hi = i;
  95         }
  96
  97         if (range_lo == -1) {
  98                 puts("SF: Calibration failed (low range)\n");
  99                 return err;
 100         }
 101
 102         /* Disable QSPI for subsequent initialization */
 103         cadence_qspi_apb_controller_disable(base);
 104
 105         /* configure the final value for read data capture delay register */
 106         cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
 107         debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
 108               (range_hi + range_lo) / 2, range_lo, range_hi);
 109
 110         /* just to ensure we do once only when speed or chip select change */
 111         priv->qspi_calibrated_hz = hz;
 112         priv->qspi_calibrated_cs = spi_chip_select(bus);
 113
 114         return 0;
 115 }
 116
 117 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
 118 {
 119         struct cadence_spi_platdata *plat = bus->platdata;
 120         struct cadence_spi_priv *priv = dev_get_priv(bus);
 121         int err;
 122
 123         if (hz > plat->max_hz)
 124                 hz = plat->max_hz;
 125
 126         /* Disable QSPI */
 127         cadence_qspi_apb_controller_disable(priv->regbase);
 128
 129         /*
 130          * Calibration required for different current SCLK speed, requested
 131          * SCLK speed or chip select
 132          */
 133         if (priv->previous_hz != hz ||
 134             priv->qspi_calibrated_hz != hz ||
 135             priv->qspi_calibrated_cs != spi_chip_select(bus)) {
 136                 err = spi_calibration(bus, hz);
 137                 if (err)
 138                         return err;
 139
 140                 /* prevent calibration run when same as previous request */
 141                 priv->previous_hz = hz;
 142         }
 143
 144         /* Enable QSPI */
 145         cadence_qspi_apb_controller_enable(priv->regbase);
 146
 147         debug("%s: speed=%d\n", __func__, hz);
 148
 149         return 0;
 150 }
 151
 152 static int cadence_spi_probe(struct udevice *bus)
 153 {
 154         struct cadence_spi_platdata *plat = bus->platdata;
 155         struct cadence_spi_priv *priv = dev_get_priv(bus);
 156         int ret;
 157
 158         priv->regbase = plat->regbase;
 159         priv->ahbbase = plat->ahbbase;
 160
 161         ret = reset_get_bulk(bus, &priv->resets);
 162         if (ret)
 163                 dev_warn(bus, "Can't get reset: %d\n", ret);
 164         else
 165                 reset_deassert_bulk(&priv->resets);
 166
 167         if (!priv->qspi_is_init) {
 168                 cadence_qspi_apb_controller_init(plat);
 169                 priv->qspi_is_init = 1;
 170         }
 171
 172         return 0;
 173 }
 174
 175 static int cadence_spi_remove(struct udevice *dev)
 176 {
 177         struct cadence_spi_priv *priv = dev_get_priv(dev);
 178
 179         return reset_release_bulk(&priv->resets);
 180 }
 181
 182 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
 183 {
 184         struct cadence_spi_priv *priv = dev_get_priv(bus);
 185
 186         /* Disable QSPI */
 187         cadence_qspi_apb_controller_disable(priv->regbase);
 188
 189         /* Set SPI mode */
 190         cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
 191
 192         /* Enable QSPI */
 193         cadence_qspi_apb_controller_enable(priv->regbase);
 194
 195         return 0;
 196 }
 197
 198 static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
 199                             const void *dout, void *din, unsigned long flags)
 200 {
 201         struct udevice *bus = dev->parent;
 202         struct cadence_spi_platdata *plat = bus->platdata;
 203         struct cadence_spi_priv *priv = dev_get_priv(bus);
 204         struct dm_spi_slave_platdata *dm_plat = dev_get_parent_platdata(dev);
 205         void *base = priv->regbase;
 206         u8 *cmd_buf = priv->cmd_buf;
 207         size_t data_bytes;
 208         int err = 0;
 209         u32 mode = CQSPI_STIG_WRITE;
 210
 211         if (flags & SPI_XFER_BEGIN) {
 212                 /* copy command to local buffer */
 213                 priv->cmd_len = bitlen / 8;
 214                 memcpy(cmd_buf, dout, priv->cmd_len);
 215         }
 216
 217         if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
 218                 /* if start and end bit are set, the data bytes is 0. */
 219                 data_bytes = 0;
 220         } else {
 221                 data_bytes = bitlen / 8;
 222         }
 223         debug("%s: len=%zu [bytes]\n", __func__, data_bytes);
 224
 225         /* Set Chip select */
 226         cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
 227                                     plat->is_decoded_cs);
 228
 229         if ((flags & SPI_XFER_END) || (flags == 0)) {
 230                 if (priv->cmd_len == 0) {
 231                         printf("QSPI: Error, command is empty.\n");
 232                         return -1;
 233                 }
 234
 235                 if (din && data_bytes) {
 236                         /* read */
 237                         /* Use STIG if no address. */
 238                         if (!CQSPI_IS_ADDR(priv->cmd_len))
 239                                 mode = CQSPI_STIG_READ;
 240                         else
 241                                 mode = CQSPI_INDIRECT_READ;
 242                 } else if (dout && !(flags & SPI_XFER_BEGIN)) {
 243                         /* write */
 244                         if (!CQSPI_IS_ADDR(priv->cmd_len))
 245                                 mode = CQSPI_STIG_WRITE;
 246                         else
 247                                 mode = CQSPI_INDIRECT_WRITE;
 248                 }
 249
 250                 switch (mode) {
 251                 case CQSPI_STIG_READ:
 252                         err = cadence_qspi_apb_command_read(
 253                                 base, priv->cmd_len, cmd_buf,
 254                                 data_bytes, din);
 255
 256                 break;
 257                 case CQSPI_STIG_WRITE:
 258                         err = cadence_qspi_apb_command_write(base,
 259                                 priv->cmd_len, cmd_buf,
 260                                 data_bytes, dout);
 261                 break;
 262                 case CQSPI_INDIRECT_READ:
 263                         err = cadence_qspi_apb_indirect_read_setup(plat,
 264                                 priv->cmd_len, dm_plat->mode, cmd_buf);
 265                         if (!err) {
 266                                 err = cadence_qspi_apb_indirect_read_execute
 267                                 (plat, data_bytes, din);
 268                         }
 269                 break;
 270                 case CQSPI_INDIRECT_WRITE:
 271                         err = cadence_qspi_apb_indirect_write_setup
 272                                 (plat, priv->cmd_len, dm_plat->mode, cmd_buf);
 273                         if (!err) {
 274                                 err = cadence_qspi_apb_indirect_write_execute
 275                                 (plat, data_bytes, dout);
 276                         }
 277                 break;
 278                 default:
 279                         err = -1;
 280                         break;
 281                 }
 282
 283                 if (flags & SPI_XFER_END) {
 284                         /* clear command buffer */
 285                         memset(cmd_buf, 0, sizeof(priv->cmd_buf));
 286                         priv->cmd_len = 0;
 287                 }
 288         }
 289
 290         return err;
 291 }
 292
 293 static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
 294 {
 295         struct cadence_spi_platdata *plat = bus->platdata;
 296         ofnode subnode;
 297
 298         plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
 299         plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1);
 300         plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
 301         plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
 302         plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
 303         plat->trigger_address = dev_read_u32_default(bus,
 304                                                      "cdns,trigger-address",
 305                                                      0);
 306
 307         /* All other paramters are embedded in the child node */
 308         subnode = dev_read_first_subnode(bus);
 309         if (!ofnode_valid(subnode)) {
 310                 printf("Error: subnode with SPI flash config missing!\n");
 311                 return -ENODEV;
 312         }
 313
 314         /* Use 500 KHz as a suitable default */
 315         plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
 316                                                500000);
 317
 318         /* Read other parameters from DT */
 319         plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
 320         plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
 321         plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
 322                                                  200);
 323         plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
 324                                                  255);
 325         plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
 326         plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
 327
 328         debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
 329               __func__, plat->regbase, plat->ahbbase, plat->max_hz,
 330               plat->page_size);
 331
 332         return 0;
 333 }
 334
 335 static const struct dm_spi_ops cadence_spi_ops = {
 336         .xfer           = cadence_spi_xfer,
 337         .set_speed      = cadence_spi_set_speed,
 338         .set_mode       = cadence_spi_set_mode,
 339         /*
 340          * cs_info is not needed, since we require all chip selects to be
 341          * in the device tree explicitly
 342          */
 343 };
 344
 345 static const struct udevice_id cadence_spi_ids[] = {
 346         { .compatible = "cdns,qspi-nor" },
 347         { }
 348 };
 349
 350 U_BOOT_DRIVER(cadence_spi) = {
 351         .name = "cadence_spi",
 352         .id = UCLASS_SPI,
 353         .of_match = cadence_spi_ids,
 354         .ops = &cadence_spi_ops,
 355         .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
 356         .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
 357         .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
 358         .probe = cadence_spi_probe,
 359         .remove = cadence_spi_remove,
 360         .flags = DM_FLAG_OS_PREPARE,
 361 };