1 // SPDX-License-Identifier: GPL-2.0+
4 * Altera Corporation <www.altera.com>
13 #include <linux/errno.h>
14 #include "cadence_qspi.h"
16 #define CQSPI_STIG_READ 0
17 #define CQSPI_STIG_WRITE 1
18 #define CQSPI_INDIRECT_READ 2
19 #define CQSPI_INDIRECT_WRITE 3
21 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
23 struct cadence_spi_platdata *plat = bus->platdata;
24 struct cadence_spi_priv *priv = dev_get_priv(bus);
26 cadence_qspi_apb_config_baudrate_div(priv->regbase,
27 CONFIG_CQSPI_REF_CLK, hz);
29 /* Reconfigure delay timing if speed is changed. */
30 cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
31 plat->tshsl_ns, plat->tsd2d_ns,
32 plat->tchsh_ns, plat->tslch_ns);
37 /* Calibration sequence to determine the read data capture delay register */
38 static int spi_calibration(struct udevice *bus, uint hz)
40 struct cadence_spi_priv *priv = dev_get_priv(bus);
41 void *base = priv->regbase;
42 u8 opcode_rdid = 0x9F;
43 unsigned int idcode = 0, temp = 0;
44 int err = 0, i, range_lo = -1, range_hi = -1;
46 /* start with slowest clock (1 MHz) */
47 cadence_spi_write_speed(bus, 1000000);
49 /* configure the read data capture delay register to 0 */
50 cadence_qspi_apb_readdata_capture(base, 1, 0);
53 cadence_qspi_apb_controller_enable(base);
55 /* read the ID which will be our golden value */
56 err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
59 puts("SF: Calibration failed (read)\n");
63 /* use back the intended clock and find low range */
64 cadence_spi_write_speed(bus, hz);
65 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
67 cadence_qspi_apb_controller_disable(base);
69 /* reconfigure the read data capture delay register */
70 cadence_qspi_apb_readdata_capture(base, 1, i);
72 /* Enable back QSPI */
73 cadence_qspi_apb_controller_enable(base);
75 /* issue a RDID to get the ID value */
76 err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
79 puts("SF: Calibration failed (read)\n");
83 /* search for range lo */
84 if (range_lo == -1 && temp == idcode) {
89 /* search for range hi */
90 if (range_lo != -1 && temp != idcode) {
98 puts("SF: Calibration failed (low range)\n");
102 /* Disable QSPI for subsequent initialization */
103 cadence_qspi_apb_controller_disable(base);
105 /* configure the final value for read data capture delay register */
106 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
107 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
108 (range_hi + range_lo) / 2, range_lo, range_hi);
110 /* just to ensure we do once only when speed or chip select change */
111 priv->qspi_calibrated_hz = hz;
112 priv->qspi_calibrated_cs = spi_chip_select(bus);
117 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
119 struct cadence_spi_platdata *plat = bus->platdata;
120 struct cadence_spi_priv *priv = dev_get_priv(bus);
123 if (hz > plat->max_hz)
127 cadence_qspi_apb_controller_disable(priv->regbase);
130 * Calibration required for different current SCLK speed, requested
131 * SCLK speed or chip select
133 if (priv->previous_hz != hz ||
134 priv->qspi_calibrated_hz != hz ||
135 priv->qspi_calibrated_cs != spi_chip_select(bus)) {
136 err = spi_calibration(bus, hz);
140 /* prevent calibration run when same as previous request */
141 priv->previous_hz = hz;
145 cadence_qspi_apb_controller_enable(priv->regbase);
147 debug("%s: speed=%d\n", __func__, hz);
152 static int cadence_spi_probe(struct udevice *bus)
154 struct cadence_spi_platdata *plat = bus->platdata;
155 struct cadence_spi_priv *priv = dev_get_priv(bus);
158 priv->regbase = plat->regbase;
159 priv->ahbbase = plat->ahbbase;
161 ret = reset_get_bulk(bus, &priv->resets);
163 dev_warn(bus, "Can't get reset: %d\n", ret);
165 reset_deassert_bulk(&priv->resets);
167 if (!priv->qspi_is_init) {
168 cadence_qspi_apb_controller_init(plat);
169 priv->qspi_is_init = 1;
175 static int cadence_spi_remove(struct udevice *dev)
177 struct cadence_spi_priv *priv = dev_get_priv(dev);
179 return reset_release_bulk(&priv->resets);
182 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
184 struct cadence_spi_priv *priv = dev_get_priv(bus);
187 cadence_qspi_apb_controller_disable(priv->regbase);
190 cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
193 cadence_qspi_apb_controller_enable(priv->regbase);
198 static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
199 const void *dout, void *din, unsigned long flags)
201 struct udevice *bus = dev->parent;
202 struct cadence_spi_platdata *plat = bus->platdata;
203 struct cadence_spi_priv *priv = dev_get_priv(bus);
204 struct dm_spi_slave_platdata *dm_plat = dev_get_parent_platdata(dev);
205 void *base = priv->regbase;
206 u8 *cmd_buf = priv->cmd_buf;
209 u32 mode = CQSPI_STIG_WRITE;
211 if (flags & SPI_XFER_BEGIN) {
212 /* copy command to local buffer */
213 priv->cmd_len = bitlen / 8;
214 memcpy(cmd_buf, dout, priv->cmd_len);
217 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
218 /* if start and end bit are set, the data bytes is 0. */
221 data_bytes = bitlen / 8;
223 debug("%s: len=%zu [bytes]\n", __func__, data_bytes);
225 /* Set Chip select */
226 cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
227 plat->is_decoded_cs);
229 if ((flags & SPI_XFER_END) || (flags == 0)) {
230 if (priv->cmd_len == 0) {
231 printf("QSPI: Error, command is empty.\n");
235 if (din && data_bytes) {
237 /* Use STIG if no address. */
238 if (!CQSPI_IS_ADDR(priv->cmd_len))
239 mode = CQSPI_STIG_READ;
241 mode = CQSPI_INDIRECT_READ;
242 } else if (dout && !(flags & SPI_XFER_BEGIN)) {
244 if (!CQSPI_IS_ADDR(priv->cmd_len))
245 mode = CQSPI_STIG_WRITE;
247 mode = CQSPI_INDIRECT_WRITE;
251 case CQSPI_STIG_READ:
252 err = cadence_qspi_apb_command_read(
253 base, priv->cmd_len, cmd_buf,
257 case CQSPI_STIG_WRITE:
258 err = cadence_qspi_apb_command_write(base,
259 priv->cmd_len, cmd_buf,
262 case CQSPI_INDIRECT_READ:
263 err = cadence_qspi_apb_indirect_read_setup(plat,
264 priv->cmd_len, dm_plat->mode, cmd_buf);
266 err = cadence_qspi_apb_indirect_read_execute
267 (plat, data_bytes, din);
270 case CQSPI_INDIRECT_WRITE:
271 err = cadence_qspi_apb_indirect_write_setup
272 (plat, priv->cmd_len, dm_plat->mode, cmd_buf);
274 err = cadence_qspi_apb_indirect_write_execute
275 (plat, data_bytes, dout);
283 if (flags & SPI_XFER_END) {
284 /* clear command buffer */
285 memset(cmd_buf, 0, sizeof(priv->cmd_buf));
293 static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
295 struct cadence_spi_platdata *plat = bus->platdata;
298 plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
299 plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1);
300 plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
301 plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
302 plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
303 plat->trigger_address = dev_read_u32_default(bus,
304 "cdns,trigger-address",
307 /* All other paramters are embedded in the child node */
308 subnode = dev_read_first_subnode(bus);
309 if (!ofnode_valid(subnode)) {
310 printf("Error: subnode with SPI flash config missing!\n");
314 /* Use 500 KHz as a suitable default */
315 plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
318 /* Read other parameters from DT */
319 plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
320 plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
321 plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
323 plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
325 plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
326 plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
328 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
329 __func__, plat->regbase, plat->ahbbase, plat->max_hz,
335 static const struct dm_spi_ops cadence_spi_ops = {
336 .xfer = cadence_spi_xfer,
337 .set_speed = cadence_spi_set_speed,
338 .set_mode = cadence_spi_set_mode,
340 * cs_info is not needed, since we require all chip selects to be
341 * in the device tree explicitly
345 static const struct udevice_id cadence_spi_ids[] = {
346 { .compatible = "cdns,qspi-nor" },
350 U_BOOT_DRIVER(cadence_spi) = {
351 .name = "cadence_spi",
353 .of_match = cadence_spi_ids,
354 .ops = &cadence_spi_ops,
355 .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
356 .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
357 .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
358 .probe = cadence_spi_probe,
359 .remove = cadence_spi_remove,
360 .flags = DM_FLAG_OS_PREPARE,