1 // SPDX-License-Identifier: GPL-2.0+
4 * Altera Corporation <www.altera.com>
9 #include <asm-generic/io.h>
16 #include <dm/device_compat.h>
17 #include <linux/err.h>
18 #include <linux/errno.h>
19 #include <linux/sizes.h>
20 #include "cadence_qspi.h"
22 #define CQSPI_STIG_READ 0
23 #define CQSPI_STIG_WRITE 1
27 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
29 struct cadence_spi_platdata *plat = bus->platdata;
30 struct cadence_spi_priv *priv = dev_get_priv(bus);
32 cadence_qspi_apb_config_baudrate_div(priv->regbase,
33 plat->ref_clk_hz, hz);
35 /* Reconfigure delay timing if speed is changed. */
36 cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
37 plat->tshsl_ns, plat->tsd2d_ns,
38 plat->tchsh_ns, plat->tslch_ns);
43 static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode)
45 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
48 SPI_MEM_OP_DATA_IN(len, idcode, 1));
50 return cadence_qspi_apb_command_read(reg_base, &op);
53 /* Calibration sequence to determine the read data capture delay register */
54 static int spi_calibration(struct udevice *bus, uint hz)
56 struct cadence_spi_priv *priv = dev_get_priv(bus);
57 void *base = priv->regbase;
58 unsigned int idcode = 0, temp = 0;
59 int err = 0, i, range_lo = -1, range_hi = -1;
61 /* start with slowest clock (1 MHz) */
62 cadence_spi_write_speed(bus, 1000000);
64 /* configure the read data capture delay register to 0 */
65 cadence_qspi_apb_readdata_capture(base, 1, 0);
68 cadence_qspi_apb_controller_enable(base);
70 /* read the ID which will be our golden value */
71 err = cadence_spi_read_id(base, 3, (u8 *)&idcode);
73 puts("SF: Calibration failed (read)\n");
77 /* use back the intended clock and find low range */
78 cadence_spi_write_speed(bus, hz);
79 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
81 cadence_qspi_apb_controller_disable(base);
83 /* reconfigure the read data capture delay register */
84 cadence_qspi_apb_readdata_capture(base, 1, i);
86 /* Enable back QSPI */
87 cadence_qspi_apb_controller_enable(base);
89 /* issue a RDID to get the ID value */
90 err = cadence_spi_read_id(base, 3, (u8 *)&temp);
92 puts("SF: Calibration failed (read)\n");
96 /* search for range lo */
97 if (range_lo == -1 && temp == idcode) {
102 /* search for range hi */
103 if (range_lo != -1 && temp != idcode) {
110 if (range_lo == -1) {
111 puts("SF: Calibration failed (low range)\n");
115 /* Disable QSPI for subsequent initialization */
116 cadence_qspi_apb_controller_disable(base);
118 /* configure the final value for read data capture delay register */
119 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
120 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
121 (range_hi + range_lo) / 2, range_lo, range_hi);
123 /* just to ensure we do once only when speed or chip select change */
124 priv->qspi_calibrated_hz = hz;
125 priv->qspi_calibrated_cs = spi_chip_select(bus);
130 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
132 struct cadence_spi_platdata *plat = bus->platdata;
133 struct cadence_spi_priv *priv = dev_get_priv(bus);
136 if (hz > plat->max_hz)
140 cadence_qspi_apb_controller_disable(priv->regbase);
143 * Calibration required for different current SCLK speed, requested
144 * SCLK speed or chip select
146 if (priv->previous_hz != hz ||
147 priv->qspi_calibrated_hz != hz ||
148 priv->qspi_calibrated_cs != spi_chip_select(bus)) {
149 err = spi_calibration(bus, hz);
153 /* prevent calibration run when same as previous request */
154 priv->previous_hz = hz;
158 cadence_qspi_apb_controller_enable(priv->regbase);
160 debug("%s: speed=%d\n", __func__, hz);
165 static int cadence_spi_probe(struct udevice *bus)
167 struct cadence_spi_platdata *plat = bus->platdata;
168 struct cadence_spi_priv *priv = dev_get_priv(bus);
172 priv->regbase = plat->regbase;
173 priv->ahbbase = plat->ahbbase;
175 if (plat->ref_clk_hz == 0) {
176 ret = clk_get_by_index(bus, 0, &clk);
178 #ifdef CONFIG_CQSPI_REF_CLK
179 plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
184 plat->ref_clk_hz = clk_get_rate(&clk);
186 if (IS_ERR_VALUE(plat->ref_clk_hz))
187 return plat->ref_clk_hz;
191 ret = reset_get_bulk(bus, &priv->resets);
193 dev_warn(bus, "Can't get reset: %d\n", ret);
195 reset_deassert_bulk(&priv->resets);
197 if (!priv->qspi_is_init) {
198 cadence_qspi_apb_controller_init(plat);
199 priv->qspi_is_init = 1;
205 static int cadence_spi_remove(struct udevice *dev)
207 struct cadence_spi_priv *priv = dev_get_priv(dev);
209 return reset_release_bulk(&priv->resets);
212 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
214 struct cadence_spi_platdata *plat = bus->platdata;
215 struct cadence_spi_priv *priv = dev_get_priv(bus);
218 cadence_qspi_apb_controller_disable(priv->regbase);
221 cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
223 /* Enable Direct Access Controller */
224 if (plat->use_dac_mode)
225 cadence_qspi_apb_dac_mode_enable(priv->regbase);
228 cadence_qspi_apb_controller_enable(priv->regbase);
233 static int cadence_spi_mem_exec_op(struct spi_slave *spi,
234 const struct spi_mem_op *op)
236 struct udevice *bus = spi->dev->parent;
237 struct cadence_spi_platdata *plat = bus->platdata;
238 struct cadence_spi_priv *priv = dev_get_priv(bus);
239 void *base = priv->regbase;
243 /* Set Chip select */
244 cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
245 plat->is_decoded_cs);
247 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
248 if (!op->addr.nbytes)
249 mode = CQSPI_STIG_READ;
253 if (!op->addr.nbytes || !op->data.buf.out)
254 mode = CQSPI_STIG_WRITE;
260 case CQSPI_STIG_READ:
261 err = cadence_qspi_apb_command_read(base, op);
263 case CQSPI_STIG_WRITE:
264 err = cadence_qspi_apb_command_write(base, op);
267 err = cadence_qspi_apb_read_setup(plat, op);
269 err = cadence_qspi_apb_read_execute(plat, op);
272 err = cadence_qspi_apb_write_setup(plat, op);
274 err = cadence_qspi_apb_write_execute(plat, op);
284 static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
286 struct cadence_spi_platdata *plat = bus->platdata;
289 plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
290 plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
292 plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
293 plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
294 plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
295 plat->trigger_address = dev_read_u32_default(bus,
296 "cdns,trigger-address",
298 /* Use DAC mode only when MMIO window is at least 8M wide */
299 if (plat->ahbsize >= SZ_8M)
300 plat->use_dac_mode = true;
302 /* All other paramters are embedded in the child node */
303 subnode = dev_read_first_subnode(bus);
304 if (!ofnode_valid(subnode)) {
305 printf("Error: subnode with SPI flash config missing!\n");
309 /* Use 500 KHz as a suitable default */
310 plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
313 /* Read other parameters from DT */
314 plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
315 plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
316 plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
318 plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
320 plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
321 plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
323 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
324 __func__, plat->regbase, plat->ahbbase, plat->max_hz,
330 static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
331 .exec_op = cadence_spi_mem_exec_op,
334 static const struct dm_spi_ops cadence_spi_ops = {
335 .set_speed = cadence_spi_set_speed,
336 .set_mode = cadence_spi_set_mode,
337 .mem_ops = &cadence_spi_mem_ops,
339 * cs_info is not needed, since we require all chip selects to be
340 * in the device tree explicitly
344 static const struct udevice_id cadence_spi_ids[] = {
345 { .compatible = "cdns,qspi-nor" },
346 { .compatible = "ti,am654-ospi" },
350 U_BOOT_DRIVER(cadence_spi) = {
351 .name = "cadence_spi",
353 .of_match = cadence_spi_ids,
354 .ops = &cadence_spi_ops,
355 .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
356 .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
357 .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
358 .probe = cadence_spi_probe,
359 .remove = cadence_spi_remove,
360 .flags = DM_FLAG_OS_PREPARE,