drivers/spi/cadence_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012
   4  * Altera Corporation <www.altera.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <fdtdec.h>
  11 #include <malloc.h>
  12 #include <reset.h>
  13 #include <spi.h>
  14 #include <linux/errno.h>
  15 #include "cadence_qspi.h"
  16
  17 #define CQSPI_STIG_READ                 0
  18 #define CQSPI_STIG_WRITE                1
  19 #define CQSPI_INDIRECT_READ             2
  20 #define CQSPI_INDIRECT_WRITE            3
  21
  22 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
  23 {
  24         struct cadence_spi_platdata *plat = bus->platdata;
  25         struct cadence_spi_priv *priv = dev_get_priv(bus);
  26
  27         cadence_qspi_apb_config_baudrate_div(priv->regbase,
  28                                              plat->ref_clk_hz, hz);
  29
  30         /* Reconfigure delay timing if speed is changed. */
  31         cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
  32                                plat->tshsl_ns, plat->tsd2d_ns,
  33                                plat->tchsh_ns, plat->tslch_ns);
  34
  35         return 0;
  36 }
  37
  38 /* Calibration sequence to determine the read data capture delay register */
  39 static int spi_calibration(struct udevice *bus, uint hz)
  40 {
  41         struct cadence_spi_priv *priv = dev_get_priv(bus);
  42         void *base = priv->regbase;
  43         u8 opcode_rdid = 0x9F;
  44         unsigned int idcode = 0, temp = 0;
  45         int err = 0, i, range_lo = -1, range_hi = -1;
  46
  47         /* start with slowest clock (1 MHz) */
  48         cadence_spi_write_speed(bus, 1000000);
  49
  50         /* configure the read data capture delay register to 0 */
  51         cadence_qspi_apb_readdata_capture(base, 1, 0);
  52
  53         /* Enable QSPI */
  54         cadence_qspi_apb_controller_enable(base);
  55
  56         /* read the ID which will be our golden value */
  57         err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
  58                 3, (u8 *)&idcode);
  59         if (err) {
  60                 puts("SF: Calibration failed (read)\n");
  61                 return err;
  62         }
  63
  64         /* use back the intended clock and find low range */
  65         cadence_spi_write_speed(bus, hz);
  66         for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
  67                 /* Disable QSPI */
  68                 cadence_qspi_apb_controller_disable(base);
  69
  70                 /* reconfigure the read data capture delay register */
  71                 cadence_qspi_apb_readdata_capture(base, 1, i);
  72
  73                 /* Enable back QSPI */
  74                 cadence_qspi_apb_controller_enable(base);
  75
  76                 /* issue a RDID to get the ID value */
  77                 err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
  78                         3, (u8 *)&temp);
  79                 if (err) {
  80                         puts("SF: Calibration failed (read)\n");
  81                         return err;
  82                 }
  83
  84                 /* search for range lo */
  85                 if (range_lo == -1 && temp == idcode) {
  86                         range_lo = i;
  87                         continue;
  88                 }
  89
  90                 /* search for range hi */
  91                 if (range_lo != -1 && temp != idcode) {
  92                         range_hi = i - 1;
  93                         break;
  94                 }
  95                 range_hi = i;
  96         }
  97
  98         if (range_lo == -1) {
  99                 puts("SF: Calibration failed (low range)\n");
 100                 return err;
 101         }
 102
 103         /* Disable QSPI for subsequent initialization */
 104         cadence_qspi_apb_controller_disable(base);
 105
 106         /* configure the final value for read data capture delay register */
 107         cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
 108         debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
 109               (range_hi + range_lo) / 2, range_lo, range_hi);
 110
 111         /* just to ensure we do once only when speed or chip select change */
 112         priv->qspi_calibrated_hz = hz;
 113         priv->qspi_calibrated_cs = spi_chip_select(bus);
 114
 115         return 0;
 116 }
 117
 118 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
 119 {
 120         struct cadence_spi_platdata *plat = bus->platdata;
 121         struct cadence_spi_priv *priv = dev_get_priv(bus);
 122         int err;
 123
 124         if (hz > plat->max_hz)
 125                 hz = plat->max_hz;
 126
 127         /* Disable QSPI */
 128         cadence_qspi_apb_controller_disable(priv->regbase);
 129
 130         /*
 131          * Calibration required for different current SCLK speed, requested
 132          * SCLK speed or chip select
 133          */
 134         if (priv->previous_hz != hz ||
 135             priv->qspi_calibrated_hz != hz ||
 136             priv->qspi_calibrated_cs != spi_chip_select(bus)) {
 137                 err = spi_calibration(bus, hz);
 138                 if (err)
 139                         return err;
 140
 141                 /* prevent calibration run when same as previous request */
 142                 priv->previous_hz = hz;
 143         }
 144
 145         /* Enable QSPI */
 146         cadence_qspi_apb_controller_enable(priv->regbase);
 147
 148         debug("%s: speed=%d\n", __func__, hz);
 149
 150         return 0;
 151 }
 152
 153 static int cadence_spi_probe(struct udevice *bus)
 154 {
 155         struct cadence_spi_platdata *plat = bus->platdata;
 156         struct cadence_spi_priv *priv = dev_get_priv(bus);
 157         int ret;
 158
 159         priv->regbase = plat->regbase;
 160         priv->ahbbase = plat->ahbbase;
 161
 162         ret = reset_get_bulk(bus, &priv->resets);
 163         if (ret)
 164                 dev_warn(bus, "Can't get reset: %d\n", ret);
 165         else
 166                 reset_deassert_bulk(&priv->resets);
 167
 168         if (!priv->qspi_is_init) {
 169                 cadence_qspi_apb_controller_init(plat);
 170                 priv->qspi_is_init = 1;
 171         }
 172
 173         return 0;
 174 }
 175
 176 static int cadence_spi_remove(struct udevice *dev)
 177 {
 178         struct cadence_spi_priv *priv = dev_get_priv(dev);
 179
 180         return reset_release_bulk(&priv->resets);
 181 }
 182
 183 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
 184 {
 185         struct cadence_spi_priv *priv = dev_get_priv(bus);
 186
 187         /* Disable QSPI */
 188         cadence_qspi_apb_controller_disable(priv->regbase);
 189
 190         /* Set SPI mode */
 191         cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
 192
 193         /* Enable QSPI */
 194         cadence_qspi_apb_controller_enable(priv->regbase);
 195
 196         return 0;
 197 }
 198
 199 static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
 200                             const void *dout, void *din, unsigned long flags)
 201 {
 202         struct udevice *bus = dev->parent;
 203         struct cadence_spi_platdata *plat = bus->platdata;
 204         struct cadence_spi_priv *priv = dev_get_priv(bus);
 205         struct dm_spi_slave_platdata *dm_plat = dev_get_parent_platdata(dev);
 206         void *base = priv->regbase;
 207         u8 *cmd_buf = priv->cmd_buf;
 208         size_t data_bytes;
 209         int err = 0;
 210         u32 mode = CQSPI_STIG_WRITE;
 211
 212         if (flags & SPI_XFER_BEGIN) {
 213                 /* copy command to local buffer */
 214                 priv->cmd_len = bitlen / 8;
 215                 memcpy(cmd_buf, dout, priv->cmd_len);
 216         }
 217
 218         if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
 219                 /* if start and end bit are set, the data bytes is 0. */
 220                 data_bytes = 0;
 221         } else {
 222                 data_bytes = bitlen / 8;
 223         }
 224         debug("%s: len=%zu [bytes]\n", __func__, data_bytes);
 225
 226         /* Set Chip select */
 227         cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
 228                                     plat->is_decoded_cs);
 229
 230         if ((flags & SPI_XFER_END) || (flags == 0)) {
 231                 if (priv->cmd_len == 0) {
 232                         printf("QSPI: Error, command is empty.\n");
 233                         return -1;
 234                 }
 235
 236                 if (din && data_bytes) {
 237                         /* read */
 238                         /* Use STIG if no address. */
 239                         if (!CQSPI_IS_ADDR(priv->cmd_len))
 240                                 mode = CQSPI_STIG_READ;
 241                         else
 242                                 mode = CQSPI_INDIRECT_READ;
 243                 } else if (dout && !(flags & SPI_XFER_BEGIN)) {
 244                         /* write */
 245                         if (!CQSPI_IS_ADDR(priv->cmd_len))
 246                                 mode = CQSPI_STIG_WRITE;
 247                         else
 248                                 mode = CQSPI_INDIRECT_WRITE;
 249                 }
 250
 251                 switch (mode) {
 252                 case CQSPI_STIG_READ:
 253                         err = cadence_qspi_apb_command_read(
 254                                 base, priv->cmd_len, cmd_buf,
 255                                 data_bytes, din);
 256
 257                 break;
 258                 case CQSPI_STIG_WRITE:
 259                         err = cadence_qspi_apb_command_write(base,
 260                                 priv->cmd_len, cmd_buf,
 261                                 data_bytes, dout);
 262                 break;
 263                 case CQSPI_INDIRECT_READ:
 264                         err = cadence_qspi_apb_indirect_read_setup(plat,
 265                                 priv->cmd_len, dm_plat->mode, cmd_buf);
 266                         if (!err) {
 267                                 err = cadence_qspi_apb_indirect_read_execute
 268                                 (plat, data_bytes, din);
 269                         }
 270                 break;
 271                 case CQSPI_INDIRECT_WRITE:
 272                         err = cadence_qspi_apb_indirect_write_setup
 273                                 (plat, priv->cmd_len, dm_plat->mode, cmd_buf);
 274                         if (!err) {
 275                                 err = cadence_qspi_apb_indirect_write_execute
 276                                 (plat, data_bytes, dout);
 277                         }
 278                 break;
 279                 default:
 280                         err = -1;
 281                         break;
 282                 }
 283
 284                 if (flags & SPI_XFER_END) {
 285                         /* clear command buffer */
 286                         memset(cmd_buf, 0, sizeof(priv->cmd_buf));
 287                         priv->cmd_len = 0;
 288                 }
 289         }
 290
 291         return err;
 292 }
 293
 294 static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
 295 {
 296         struct cadence_spi_platdata *plat = bus->platdata;
 297         ofnode subnode;
 298         struct clk clk;
 299         int ret;
 300
 301         plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
 302         plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1);
 303         plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
 304         plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
 305         plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
 306         plat->trigger_address = dev_read_u32_default(bus,
 307                                                      "cdns,trigger-address",
 308                                                      0);
 309
 310         /* All other paramters are embedded in the child node */
 311         subnode = dev_read_first_subnode(bus);
 312         if (!ofnode_valid(subnode)) {
 313                 printf("Error: subnode with SPI flash config missing!\n");
 314                 return -ENODEV;
 315         }
 316
 317         /* Use 500 KHz as a suitable default */
 318         plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
 319                                                500000);
 320
 321         /* Read other parameters from DT */
 322         plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
 323         plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
 324         plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
 325                                                  200);
 326         plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
 327                                                  255);
 328         plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
 329         plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
 330
 331         ret = clk_get_by_index(bus, 0, &clk);
 332         if (ret) {
 333 #ifdef CONFIG_CQSPI_REF_CLK
 334                 plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
 335 #else
 336                 return ret;
 337 #endif
 338         } else {
 339                 plat->ref_clk_hz = clk_get_rate(&clk);
 340                 clk_free(&clk);
 341                 if (IS_ERR_VALUE(plat->ref_clk_hz))
 342                         return plat->ref_clk_hz;
 343         }
 344
 345         debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
 346               __func__, plat->regbase, plat->ahbbase, plat->max_hz,
 347               plat->page_size);
 348
 349         return 0;
 350 }
 351
 352 static const struct dm_spi_ops cadence_spi_ops = {
 353         .xfer           = cadence_spi_xfer,
 354         .set_speed      = cadence_spi_set_speed,
 355         .set_mode       = cadence_spi_set_mode,
 356         /*
 357          * cs_info is not needed, since we require all chip selects to be
 358          * in the device tree explicitly
 359          */
 360 };
 361
 362 static const struct udevice_id cadence_spi_ids[] = {
 363         { .compatible = "cdns,qspi-nor" },
 364         { }
 365 };
 366
 367 U_BOOT_DRIVER(cadence_spi) = {
 368         .name = "cadence_spi",
 369         .id = UCLASS_SPI,
 370         .of_match = cadence_spi_ids,
 371         .ops = &cadence_spi_ops,
 372         .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
 373         .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
 374         .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
 375         .probe = cadence_spi_probe,
 376         .remove = cadence_spi_remove,
 377         .flags = DM_FLAG_OS_PREPARE,
 378 };