2 * Analog Devices SPI3 controller driver
4 * Copyright (c) 2011 Analog Devices Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <asm/blackfin.h>
25 #include <asm/clock.h>
27 #include <asm/portmux.h>
28 #include <asm/mach-common/bits/spi6xx.h>
30 struct bfin_spi_slave {
31 struct spi_slave slave;
33 struct bfin_spi_regs *regs;
37 #define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
39 #define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
40 #ifdef CONFIG_BFIN_SPI_GPIO_CS
41 # define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
43 # define is_gpio_cs(cs) 0
46 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
49 return gpio_is_valid(gpio_cs(cs));
51 return (cs >= 1 && cs <= MAX_CTRL_CS);
54 void spi_cs_activate(struct spi_slave *slave)
56 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
58 if (is_gpio_cs(slave->cs)) {
59 unsigned int cs = gpio_cs(slave->cs);
60 gpio_set_value(cs, bss->cs_pol);
63 ssel = bfin_read32(&bss->regs->ssel);
64 ssel |= 1 << slave->cs;
66 ssel |= (1 << 8) << slave->cs;
68 ssel &= ~((1 << 8) << slave->cs);
69 bfin_write32(&bss->regs->ssel, ssel);
75 void spi_cs_deactivate(struct spi_slave *slave)
77 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
79 if (is_gpio_cs(slave->cs)) {
80 unsigned int cs = gpio_cs(slave->cs);
81 gpio_set_value(cs, !bss->cs_pol);
84 ssel = bfin_read32(&bss->regs->ssel);
86 ssel &= ~((1 << 8) << slave->cs);
88 ssel |= (1 << 8) << slave->cs;
90 bfin_write32(&bss->regs->ssel, ssel);
93 ssel &= ~(1 << slave->cs);
94 bfin_write32(&bss->regs->ssel, ssel);
104 #define SPI_PINS(n) \
105 { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
106 static unsigned short pins[][5] = {
118 #define SPI_CS_PINS(n) \
120 P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
121 P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
124 static const unsigned short cs_pins[][7] = {
126 [0] = SPI_CS_PINS(0),
129 [1] = SPI_CS_PINS(1),
132 [2] = SPI_CS_PINS(2),
136 void spi_set_speed(struct spi_slave *slave, uint hz)
138 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
149 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
150 unsigned int max_hz, unsigned int mode)
152 struct bfin_spi_slave *bss;
155 if (!spi_cs_is_valid(bus, cs))
161 reg_base = SPI0_REGBASE;
166 reg_base = SPI1_REGBASE;
171 reg_base = SPI2_REGBASE;
175 debug("%s: invalid bus %u\n", __func__, bus);
179 bss = spi_alloc_slave(struct bfin_spi_slave, bus, cs);
183 bss->regs = (struct bfin_spi_regs *)reg_base;
184 bss->control = SPI_CTL_EN | SPI_CTL_MSTR;
186 bss->control |= SPI_CTL_CPHA;
188 bss->control |= SPI_CTL_CPOL;
189 if (mode & SPI_LSB_FIRST)
190 bss->control |= SPI_CTL_LSBF;
191 bss->control &= ~SPI_CTL_ASSEL;
192 bss->cs_pol = mode & SPI_CS_HIGH ? 1 : 0;
193 spi_set_speed(&bss->slave, max_hz);
198 void spi_free_slave(struct spi_slave *slave)
200 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
204 int spi_claim_bus(struct spi_slave *slave)
206 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
208 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
210 if (is_gpio_cs(slave->cs)) {
211 unsigned int cs = gpio_cs(slave->cs);
212 gpio_request(cs, "bfin-spi");
213 gpio_direction_output(cs, !bss->cs_pol);
214 pins[slave->bus][0] = P_DONTCARE;
216 pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
217 peripheral_request_list(pins[slave->bus], "bfin-spi");
219 bfin_write32(&bss->regs->control, bss->control);
220 bfin_write32(&bss->regs->clock, bss->clock);
221 bfin_write32(&bss->regs->delay, 0x0);
222 bfin_write32(&bss->regs->rx_control, SPI_RXCTL_REN);
223 bfin_write32(&bss->regs->tx_control, SPI_TXCTL_TEN | SPI_TXCTL_TTI);
229 void spi_release_bus(struct spi_slave *slave)
231 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
233 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
235 peripheral_free_list(pins[slave->bus]);
236 if (is_gpio_cs(slave->cs))
237 gpio_free(gpio_cs(slave->cs));
239 bfin_write32(&bss->regs->rx_control, 0x0);
240 bfin_write32(&bss->regs->tx_control, 0x0);
241 bfin_write32(&bss->regs->control, 0x0);
245 #ifndef CONFIG_BFIN_SPI_IDLE_VAL
246 # define CONFIG_BFIN_SPI_IDLE_VAL 0xff
249 static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
252 /* discard invalid rx data and empty rfifo */
253 while (!(bfin_read32(&bss->regs->status) & SPI_STAT_RFE))
254 bfin_read32(&bss->regs->rfifo);
257 u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
258 debug("%s: tx:%x ", __func__, value);
259 bfin_write32(&bss->regs->tfifo, value);
261 while (bfin_read32(&bss->regs->status) & SPI_STAT_RFE)
264 value = bfin_read32(&bss->regs->rfifo);
267 debug("rx:%x\n", value);
273 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
274 void *din, unsigned long flags)
276 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
279 uint bytes = bitlen / 8;
282 debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
283 slave->bus, slave->cs, bitlen, bytes, flags);
288 /* we can only do 8 bit transfers */
290 flags |= SPI_XFER_END;
294 if (flags & SPI_XFER_BEGIN)
295 spi_cs_activate(slave);
297 ret = spi_pio_xfer(bss, tx, rx, bytes);
300 if (flags & SPI_XFER_END)
301 spi_cs_deactivate(slave);