2 * Copyright (C) 2007 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/clk.h>
17 #include <asm/arch/hardware.h>
19 #include <asm/arch/at91_spi.h>
25 #include "atmel_spi.h"
29 static int spi_has_wdrbt(struct atmel_spi_slave *slave)
33 ver = spi_readl(slave, VERSION);
35 return (ATMEL_SPI_VERSION_REV(ver) >= 0x210);
43 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
44 unsigned int max_hz, unsigned int mode)
46 struct atmel_spi_slave *as;
51 if (!spi_cs_is_valid(bus, cs))
56 regs = (void *)ATMEL_BASE_SPI0;
58 #ifdef ATMEL_BASE_SPI1
60 regs = (void *)ATMEL_BASE_SPI1;
63 #ifdef ATMEL_BASE_SPI2
65 regs = (void *)ATMEL_BASE_SPI2;
68 #ifdef ATMEL_BASE_SPI3
70 regs = (void *)ATMEL_BASE_SPI3;
78 scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz;
79 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
80 /* Too low max SCK rate */
85 csrx = ATMEL_SPI_CSRx_SCBR(scbr);
86 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
87 if (!(mode & SPI_CPHA))
88 csrx |= ATMEL_SPI_CSRx_NCPHA;
90 csrx |= ATMEL_SPI_CSRx_CPOL;
92 as = spi_alloc_slave(struct atmel_spi_slave, bus, cs);
97 as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS
98 | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf);
99 if (spi_has_wdrbt(as))
100 as->mr |= ATMEL_SPI_MR_WDRBT;
102 spi_writel(as, CSR(cs), csrx);
107 void spi_free_slave(struct spi_slave *slave)
109 struct atmel_spi_slave *as = to_atmel_spi(slave);
114 int spi_claim_bus(struct spi_slave *slave)
116 struct atmel_spi_slave *as = to_atmel_spi(slave);
118 /* Enable the SPI hardware */
119 spi_writel(as, CR, ATMEL_SPI_CR_SPIEN);
122 * Select the slave. This should set SCK to the correct
123 * initial state, etc.
125 spi_writel(as, MR, as->mr);
130 void spi_release_bus(struct spi_slave *slave)
132 struct atmel_spi_slave *as = to_atmel_spi(slave);
134 /* Disable the SPI hardware */
135 spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS);
138 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
139 const void *dout, void *din, unsigned long flags)
141 struct atmel_spi_slave *as = to_atmel_spi(slave);
146 const u8 *txp = dout;
151 /* Finish any previously submitted transfers */
155 * TODO: The controller can do non-multiple-of-8 bit
156 * transfers, but this driver currently doesn't support it.
158 * It's also not clear how such transfers are supposed to be
159 * represented as a stream of bytes...this is a limitation of
160 * the current SPI interface.
163 /* Errors always terminate an ongoing transfer */
164 flags |= SPI_XFER_END;
171 * The controller can do automatic CS control, but it is
172 * somewhat quirky, and it doesn't really buy us much anyway
173 * in the context of U-Boot.
175 if (flags & SPI_XFER_BEGIN) {
176 spi_cs_activate(slave);
178 * sometimes the RDR is not empty when we get here,
179 * in theory that should not happen, but it DOES happen.
180 * Read it here to be on the safe side.
181 * That also clears the OVRES flag. Required if the
182 * following loop exits due to OVRES!
187 for (len_tx = 0, len_rx = 0; len_rx < len; ) {
188 status = spi_readl(as, SR);
190 if (status & ATMEL_SPI_SR_OVRES)
193 if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) {
198 spi_writel(as, TDR, value);
201 if (status & ATMEL_SPI_SR_RDRF) {
202 value = spi_readl(as, RDR);
210 if (flags & SPI_XFER_END) {
212 * Wait until the transfer is completely done before
216 status = spi_readl(as, SR);
217 } while (!(status & ATMEL_SPI_SR_TXEMPTY));
219 spi_cs_deactivate(slave);
227 #define MAX_CS_COUNT 4
229 struct atmel_spi_platdata {
230 struct at91_spi *regs;
233 struct atmel_spi_priv {
234 unsigned int freq; /* Default frequency */
237 #ifdef CONFIG_DM_GPIO
238 struct gpio_desc cs_gpios[MAX_CS_COUNT];
242 static int atmel_spi_claim_bus(struct udevice *dev)
244 struct udevice *bus = dev_get_parent(dev);
245 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
246 struct atmel_spi_priv *priv = dev_get_priv(bus);
247 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
248 struct at91_spi *reg_base = bus_plat->regs;
249 u32 cs = slave_plat->cs;
250 u32 freq = priv->freq;
251 u32 scbr, csrx, mode;
253 scbr = (priv->bus_clk_rate + freq - 1) / freq;
254 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
260 csrx = ATMEL_SPI_CSRx_SCBR(scbr);
261 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
263 if (!(priv->mode & SPI_CPHA))
264 csrx |= ATMEL_SPI_CSRx_NCPHA;
265 if (priv->mode & SPI_CPOL)
266 csrx |= ATMEL_SPI_CSRx_CPOL;
268 writel(csrx, ®_base->csr[cs]);
270 mode = ATMEL_SPI_MR_MSTR |
271 ATMEL_SPI_MR_MODFDIS |
273 ATMEL_SPI_MR_PCS(~(1 << cs));
275 writel(mode, ®_base->mr);
277 writel(ATMEL_SPI_CR_SPIEN, ®_base->cr);
282 static int atmel_spi_release_bus(struct udevice *dev)
284 struct udevice *bus = dev_get_parent(dev);
285 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
287 writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr);
292 static void atmel_spi_cs_activate(struct udevice *dev)
294 #ifdef CONFIG_DM_GPIO
295 struct udevice *bus = dev_get_parent(dev);
296 struct atmel_spi_priv *priv = dev_get_priv(bus);
297 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
298 u32 cs = slave_plat->cs;
300 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
303 dm_gpio_set_value(&priv->cs_gpios[cs], 0);
307 static void atmel_spi_cs_deactivate(struct udevice *dev)
309 #ifdef CONFIG_DM_GPIO
310 struct udevice *bus = dev_get_parent(dev);
311 struct atmel_spi_priv *priv = dev_get_priv(bus);
312 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
313 u32 cs = slave_plat->cs;
315 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
318 dm_gpio_set_value(&priv->cs_gpios[cs], 1);
322 static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen,
323 const void *dout, void *din, unsigned long flags)
325 struct udevice *bus = dev_get_parent(dev);
326 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
327 struct at91_spi *reg_base = bus_plat->regs;
329 u32 len_tx, len_rx, len;
331 const u8 *txp = dout;
339 * The controller can do non-multiple-of-8 bit
340 * transfers, but this driver currently doesn't support it.
342 * It's also not clear how such transfers are supposed to be
343 * represented as a stream of bytes...this is a limitation of
344 * the current SPI interface.
347 /* Errors always terminate an ongoing transfer */
348 flags |= SPI_XFER_END;
355 * The controller can do automatic CS control, but it is
356 * somewhat quirky, and it doesn't really buy us much anyway
357 * in the context of U-Boot.
359 if (flags & SPI_XFER_BEGIN) {
360 atmel_spi_cs_activate(dev);
363 * sometimes the RDR is not empty when we get here,
364 * in theory that should not happen, but it DOES happen.
365 * Read it here to be on the safe side.
366 * That also clears the OVRES flag. Required if the
367 * following loop exits due to OVRES!
369 readl(®_base->rdr);
372 for (len_tx = 0, len_rx = 0; len_rx < len; ) {
373 status = readl(®_base->sr);
375 if (status & ATMEL_SPI_SR_OVRES)
378 if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) {
383 writel(value, ®_base->tdr);
387 if (status & ATMEL_SPI_SR_RDRF) {
388 value = readl(®_base->rdr);
396 if (flags & SPI_XFER_END) {
398 * Wait until the transfer is completely done before
401 wait_for_bit_le32(®_base->sr,
402 ATMEL_SPI_SR_TXEMPTY, true, 1000, false);
404 atmel_spi_cs_deactivate(dev);
410 static int atmel_spi_set_speed(struct udevice *bus, uint speed)
412 struct atmel_spi_priv *priv = dev_get_priv(bus);
419 static int atmel_spi_set_mode(struct udevice *bus, uint mode)
421 struct atmel_spi_priv *priv = dev_get_priv(bus);
428 static const struct dm_spi_ops atmel_spi_ops = {
429 .claim_bus = atmel_spi_claim_bus,
430 .release_bus = atmel_spi_release_bus,
431 .xfer = atmel_spi_xfer,
432 .set_speed = atmel_spi_set_speed,
433 .set_mode = atmel_spi_set_mode,
435 * cs_info is not needed, since we require all chip selects to be
436 * in the device tree explicitly
440 static int atmel_spi_enable_clk(struct udevice *bus)
442 struct atmel_spi_priv *priv = dev_get_priv(bus);
447 ret = clk_get_by_index(bus, 0, &clk);
451 ret = clk_enable(&clk);
455 clk_rate = clk_get_rate(&clk);
459 priv->bus_clk_rate = clk_rate;
466 static int atmel_spi_probe(struct udevice *bus)
468 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
471 ret = atmel_spi_enable_clk(bus);
475 bus_plat->regs = (struct at91_spi *)devfdt_get_addr(bus);
477 #ifdef CONFIG_DM_GPIO
478 struct atmel_spi_priv *priv = dev_get_priv(bus);
481 ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios,
482 ARRAY_SIZE(priv->cs_gpios), 0);
484 pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
488 for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
489 if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
492 dm_gpio_set_dir_flags(&priv->cs_gpios[i],
493 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
497 writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr);
502 static const struct udevice_id atmel_spi_ids[] = {
503 { .compatible = "atmel,at91rm9200-spi" },
507 U_BOOT_DRIVER(atmel_spi) = {
510 .of_match = atmel_spi_ids,
511 .ops = &atmel_spi_ops,
512 .platdata_auto_alloc_size = sizeof(struct atmel_spi_platdata),
513 .priv_auto_alloc_size = sizeof(struct atmel_spi_priv),
514 .probe = atmel_spi_probe,