2 * Copyright (C) 2007 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/clk.h>
17 #include <asm/arch/hardware.h>
19 #include <asm/arch/at91_spi.h>
25 #include "atmel_spi.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 #define MAX_CS_COUNT 4
31 struct atmel_spi_platdata {
32 struct at91_spi *regs;
35 struct atmel_spi_priv {
36 unsigned int freq; /* Default frequency */
40 struct gpio_desc cs_gpios[MAX_CS_COUNT];
44 static int atmel_spi_claim_bus(struct udevice *dev)
46 struct udevice *bus = dev_get_parent(dev);
47 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
48 struct atmel_spi_priv *priv = dev_get_priv(bus);
49 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
50 struct at91_spi *reg_base = bus_plat->regs;
51 u32 cs = slave_plat->cs;
52 u32 freq = priv->freq;
55 scbr = (priv->bus_clk_rate + freq - 1) / freq;
56 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
62 csrx = ATMEL_SPI_CSRx_SCBR(scbr);
63 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
65 if (!(priv->mode & SPI_CPHA))
66 csrx |= ATMEL_SPI_CSRx_NCPHA;
67 if (priv->mode & SPI_CPOL)
68 csrx |= ATMEL_SPI_CSRx_CPOL;
70 writel(csrx, ®_base->csr[cs]);
72 mode = ATMEL_SPI_MR_MSTR |
73 ATMEL_SPI_MR_MODFDIS |
75 ATMEL_SPI_MR_PCS(~(1 << cs));
77 writel(mode, ®_base->mr);
79 writel(ATMEL_SPI_CR_SPIEN, ®_base->cr);
84 static int atmel_spi_release_bus(struct udevice *dev)
86 struct udevice *bus = dev_get_parent(dev);
87 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
89 writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr);
94 static void atmel_spi_cs_activate(struct udevice *dev)
97 struct udevice *bus = dev_get_parent(dev);
98 struct atmel_spi_priv *priv = dev_get_priv(bus);
99 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
100 u32 cs = slave_plat->cs;
102 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
105 dm_gpio_set_value(&priv->cs_gpios[cs], 0);
109 static void atmel_spi_cs_deactivate(struct udevice *dev)
111 #ifdef CONFIG_DM_GPIO
112 struct udevice *bus = dev_get_parent(dev);
113 struct atmel_spi_priv *priv = dev_get_priv(bus);
114 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
115 u32 cs = slave_plat->cs;
117 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
120 dm_gpio_set_value(&priv->cs_gpios[cs], 1);
124 static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen,
125 const void *dout, void *din, unsigned long flags)
127 struct udevice *bus = dev_get_parent(dev);
128 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
129 struct at91_spi *reg_base = bus_plat->regs;
131 u32 len_tx, len_rx, len;
133 const u8 *txp = dout;
141 * The controller can do non-multiple-of-8 bit
142 * transfers, but this driver currently doesn't support it.
144 * It's also not clear how such transfers are supposed to be
145 * represented as a stream of bytes...this is a limitation of
146 * the current SPI interface.
149 /* Errors always terminate an ongoing transfer */
150 flags |= SPI_XFER_END;
157 * The controller can do automatic CS control, but it is
158 * somewhat quirky, and it doesn't really buy us much anyway
159 * in the context of U-Boot.
161 if (flags & SPI_XFER_BEGIN) {
162 atmel_spi_cs_activate(dev);
165 * sometimes the RDR is not empty when we get here,
166 * in theory that should not happen, but it DOES happen.
167 * Read it here to be on the safe side.
168 * That also clears the OVRES flag. Required if the
169 * following loop exits due to OVRES!
171 readl(®_base->rdr);
174 for (len_tx = 0, len_rx = 0; len_rx < len; ) {
175 status = readl(®_base->sr);
177 if (status & ATMEL_SPI_SR_OVRES)
180 if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) {
185 writel(value, ®_base->tdr);
189 if (status & ATMEL_SPI_SR_RDRF) {
190 value = readl(®_base->rdr);
198 if (flags & SPI_XFER_END) {
200 * Wait until the transfer is completely done before
203 wait_for_bit_le32(®_base->sr,
204 ATMEL_SPI_SR_TXEMPTY, true, 1000, false);
206 atmel_spi_cs_deactivate(dev);
212 static int atmel_spi_set_speed(struct udevice *bus, uint speed)
214 struct atmel_spi_priv *priv = dev_get_priv(bus);
221 static int atmel_spi_set_mode(struct udevice *bus, uint mode)
223 struct atmel_spi_priv *priv = dev_get_priv(bus);
230 static const struct dm_spi_ops atmel_spi_ops = {
231 .claim_bus = atmel_spi_claim_bus,
232 .release_bus = atmel_spi_release_bus,
233 .xfer = atmel_spi_xfer,
234 .set_speed = atmel_spi_set_speed,
235 .set_mode = atmel_spi_set_mode,
237 * cs_info is not needed, since we require all chip selects to be
238 * in the device tree explicitly
242 static int atmel_spi_enable_clk(struct udevice *bus)
244 struct atmel_spi_priv *priv = dev_get_priv(bus);
249 ret = clk_get_by_index(bus, 0, &clk);
253 ret = clk_enable(&clk);
257 clk_rate = clk_get_rate(&clk);
261 priv->bus_clk_rate = clk_rate;
268 static int atmel_spi_probe(struct udevice *bus)
270 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
273 ret = atmel_spi_enable_clk(bus);
277 bus_plat->regs = (struct at91_spi *)devfdt_get_addr(bus);
279 #ifdef CONFIG_DM_GPIO
280 struct atmel_spi_priv *priv = dev_get_priv(bus);
283 ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios,
284 ARRAY_SIZE(priv->cs_gpios), 0);
286 pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
290 for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
291 if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
294 dm_gpio_set_dir_flags(&priv->cs_gpios[i],
295 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
299 writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr);
304 static const struct udevice_id atmel_spi_ids[] = {
305 { .compatible = "atmel,at91rm9200-spi" },
309 U_BOOT_DRIVER(atmel_spi) = {
312 .of_match = atmel_spi_ids,
313 .ops = &atmel_spi_ops,
314 .platdata_auto_alloc_size = sizeof(struct atmel_spi_platdata),
315 .priv_auto_alloc_size = sizeof(struct atmel_spi_priv),
316 .probe = atmel_spi_probe,