2 * Driver for ATMEL DataFlash support
3 * Author : Hamid Ikdoumi (Atmel)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/clk.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/io.h>
27 #include <asm/arch/at91_pio.h>
28 #include <asm/arch/at91_spi.h>
30 #include <dataflash.h>
32 #define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
33 #define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 1: NPCS1%1101 */
34 #define AT91_SPI_PCS2_DATAFLASH_CARD 0xB /* Chip Select 2: NPCS2%1011 */
35 #define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
37 void AT91F_SpiInit(void)
40 writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR);
42 /* Configure SPI in Master Mode with No CS selected !!! */
43 writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
44 AT91_BASE_SPI + AT91_SPI_MR);
47 writel(AT91_SPI_NCPHA |
48 (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
49 (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
50 ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
51 AT91_BASE_SPI + AT91_SPI_CSR(0));
53 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
55 writel(AT91_SPI_NCPHA |
56 (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
57 (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
58 ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
59 AT91_BASE_SPI + AT91_SPI_CSR(1));
61 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
63 writel(AT91_SPI_NCPHA |
64 (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
65 (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
66 ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
67 AT91_BASE_SPI + AT91_SPI_CSR(2));
69 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
71 writel(AT91_SPI_NCPHA |
72 (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
73 (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
74 ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
75 AT91_BASE_SPI + AT91_SPI_CSR(3));
79 writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
81 while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS));
84 * Add tempo to get SPI in a safe state.
85 * Should not be needed for new silicon (Rev B)
88 readl(AT91_BASE_SPI + AT91_SPI_SR);
89 readl(AT91_BASE_SPI + AT91_SPI_RDR);
93 void AT91F_SpiEnable(int cs)
98 case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
99 mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
101 writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
102 AT91_BASE_SPI + AT91_SPI_MR);
104 case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */
105 mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
107 writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
108 AT91_BASE_SPI + AT91_SPI_MR);
110 case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */
111 mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
113 writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
114 AT91_BASE_SPI + AT91_SPI_MR);
117 mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
119 writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
120 AT91_BASE_SPI + AT91_SPI_MR);
125 writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
128 unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
130 unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
132 unsigned int timeout;
136 writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
138 /* Initialize the Transmit and Receive Pointer */
139 writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR);
140 writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR);
142 /* Intialize the Transmit and Receive Counters */
143 writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR);
144 writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR);
146 if (pDesc->tx_data_size != 0) {
147 /* Initialize the Next Transmit and Next Receive Pointer */
148 writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR);
149 writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR);
151 /* Intialize the Next Transmit and Next Receive Counters */
152 writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR);
153 writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR);
156 /* arm simple, non interrupt dependent timer */
157 reset_timer_masked();
160 writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
161 while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
162 ((timeout = get_timer_masked()) < CONFIG_SYS_SPI_WRITE_TOUT));
163 writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
166 if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
167 printf("Error Timeout\n\r");
168 return DATAFLASH_ERROR;